CN113453108A - Wireless earphone, wireless earphone system and wireless earphone shutdown method - Google Patents

Abstract

The application discloses wireless earphone, wireless earphone system and wireless earphone shutdown method, wireless earphone includes: the power supply module is used for supplying power to the wireless earphone; and the processor is connected with the power supply module and used for shutdown after the data is stored according to the shutdown instruction and powered down after the data is stored. The wireless earphone of the embodiment of the application ensures that the processor is powered off after being completely powered off through time delay, and obviously improves the stability and reliability of the system.

Description

Wireless earphone, wireless earphone system and wireless earphone shutdown method

Technical Field

The present application relates to the field of earphone technologies, and in particular, to a wireless earphone, a wireless earphone system, and a method for turning off a wireless earphone.

Background

The TWS (True Wireless Stereo) headset shown in fig. 1 and 2 cancels a wire rod compared with the traditional wired headset, adopts bluetooth connection, and realizes Wireless separated use of left and right sound channels of bluetooth, so that the TWS headset has diversity in use modes, such as exclusive use and sharing, and one set can be used as two sets.

At present, when a TWS earphone leaves a factory, some manufacturers shut down the TWS earphone, the current of the TWS earphone is about 10uA when the TWS earphone is in a shutdown state, and the TWS earphone consumes more than four months of electricity under the condition of full electricity for a 30mAh battery.

In the current scheme, a charging chip with a low power consumption mode is generally used, other power supplies of the earphone are connected to an output pin of the earphone as far as possible, and the earphone is enabled to enter the low power consumption mode when leaving a factory, so that the usable time of a battery can be prolonged. Generally, the power consumption of the charging chip is about 1uA, the power consumption of the charging chip protected by a lithium battery is about 4uA, the total power consumption is about 5uA, and the power is consumed in more than eight months under the full power condition.

At present, a common method is to directly send a command to a charging chip through an I2C (Inter-Integrated Circuit) bus, so that the charging chip enters a low power consumption mode, and power down the system. However, this method has the disadvantage that direct power down of the system may cause system instability.

Disclosure of Invention

The application provides a wireless earphone, and power failure after the earphone system is shut down thoroughly is guaranteed through time delay, so that the stability and reliability of the system are remarkably improved.

An embodiment of a first aspect of the present application provides a wireless headset, including: the power supply module is used for supplying power to the wireless earphone; and the processor is connected with the power supply module and used for shutdown after the data is saved according to the shutdown instruction and powered down after the data is saved.

According to the wireless earphone of the embodiment of the application, the power supply module supplies power to the wireless earphone, and the processor is used for powering off after data is saved according to the power-off instruction and powering off after the data is saved. The wireless earphone ensures that the processor is powered off after being completely shut down through time delay, and obviously improves the stability and reliability of the system.

The embodiment of the second aspect of the present application provides a wireless headset system, which includes a charging box and the wireless headset described above.

According to the wireless earphone system, the power failure of the processor after the data is stored is guaranteed through time delay, and the stability and the reliability of the system are remarkably improved.

An embodiment of a third aspect of the present application provides a method for powering off a wireless headset, where the wireless headset includes: the wireless earphone power supply system comprises a power supply module for supplying power to the wireless earphone and a processor connected with the power supply module, wherein the power-off method comprises the following steps: the processor is shut down after the data is saved according to the shutdown instruction; the processor is powered down after saving the data.

According to the shutdown method of the wireless earphone, the processor is guaranteed to be powered off after data is stored through time delay, and the stability and reliability of the system are remarkably improved.

Drawings

FIG. 1 is a schematic diagram of a TWS headset of the related art;

FIG. 2 is a schematic diagram of another TWS headset in the related art;

FIG. 3 is a block schematic diagram of a wireless headset according to an embodiment of the present application;

fig. 4 is a block schematic diagram of a wireless headset system according to one embodiment of the present application;

fig. 5 is a waveform diagram of a control module of a wireless headset system according to one embodiment of the present application;

fig. 6 is a waveform schematic diagram of a control module of a wireless headset system according to another embodiment of the present application;

fig. 7 is a waveform diagram of a control module of a wireless headset system according to an example one of the present application;

FIG. 8 is a schematic block diagram of a switch module according to one embodiment of the present application;

fig. 9 is a waveform schematic diagram of a control module of a wireless headset system according to yet another embodiment of the present application; and

fig. 10 is a flowchart of a method for powering off a wireless headset according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

The wireless headset and the wireless headset system according to the embodiments of the present application will be described with reference to the accompanying drawings.

Fig. 3 is a block schematic diagram of a wireless headset according to an embodiment of the application. As shown in fig. 3, the wireless headset of the embodiment of the present application includes: a power module 10 and a processor 20.

The power module 10 is used for supplying power to the wireless headset, the processor 20 is connected with the power module 10, and the processor 20 is used for powering off after data is saved according to a power-off instruction and powering off after the data is saved.

That is to say, in the present application, the processor 20 is enabled to power down the power module 10 after storing data through a shutdown instruction, so as to ensure that the system reliably enters the low power consumption mode or the transportation power saving mode shipmode, where the shutdown instruction may be from the charging box or a shutdown instruction generated by the shutdown operation of the wireless headset.

It should be noted that in the present application, instability caused by power failure when the processor 20 does not store data in the shutdown process may be avoided by a power failure delaying manner, where the delaying may be implemented at the charging box end, for example, a power failure instruction is sent in a delayed manner, where the delay of the power failure instruction may be based on a period of time after the shutdown instruction is sent, or may be based on a period of time after the charging box receives a feedback signal for representing that the headset receives the shutdown instruction; the delay may also be implemented at the earphone end, where the delay control may be implemented by the power module 10 itself, or may be implemented by another module to delay control the connection between the power module 10 and the processor 20. Because powering down after shutdown may trigger the processor 20 to reboot in some design schemes, the selection of the power down time needs to be considered in combination with aspects such as shutdown time and instruction setting conditions.

A power down mode according to an embodiment of the present application will be described with reference to fig. 4 to 9.

According to one embodiment of the present application, the processor wireless headset controls the processor 20 to power down after saving data by disconnecting the power module 10 from the processor 20.

As shown in fig. 4, the wireless headset further includes: the metal interface POGO PIN can be connected with the charging box; processor 20 is connected with metal interface POGO PIN, and processor 20 is also used for: and receiving a shutdown instruction sent by the charging box through a POGO PIN (polymer optical identification number) of a metal interface.

As shown in fig. 4, the wireless headset further includes: a switch module 30 and a control module 40. Wherein, the power module 10 is connected with the processor 20 through the switch module 30; the control module 40 is configured to control the switch module 30 to disconnect the power module 10 from the processor 20 according to the first power-down instruction, so as to power down the processor 20 after storing the data.

According to an embodiment of the present application, the control module 40 is connected to the metal interface POGO PIN, and the control module 40 is further configured to: and receiving a first power-down instruction sent by the charging box through a metal interface POGO PIN.

It should be noted that the metal interface POGO PIN is used for charging and communication of the wireless headset, and the common metal interface POGO PIN has two PINs or three PINs, and some PINs are disposed at the bottom of the headset rod (as shown in fig. 1), and some PINs are disposed below the earplugs (as shown in fig. 2). The effect of the box that charges is accomodate wireless earphone, and there is the battery simultaneously to charge box the inside, has the function of charging for wireless earphone like this, and the inside has two copper posts that charge.

In the embodiment of the application, the time for the charging box to send the first power-down instruction is not earlier than the time for the charging box to send the shutdown instruction; the control module 40 is specifically configured to: after the first power-down instruction is received and the first time is delayed, the control switch module 30 disconnects the connection between the power module 10 and the processor 20. In order to ensure that the earphone processor 20 is powered off after the earphone processor is powered off, the first time may be determined by the power-off time of the processor 20, and certainly, the processor 20 may also be powered off before the earphone processor is powered off after data is stored, so the first time may also be related to the data storage time.

The processor 20 may be a bluetooth system including a bluetooth chip, a Wireless module such as a wifi (Wireless Fidelity) system, or another processor, such as a CPU (Central Processing Unit).

Specifically, when the wireless earphone is put into the charging box and the wireless earphone needs to be powered off (for example, the wireless earphone is fully charged and the earphone is powered off), the charging box sends a power-off instruction to the wireless earphone through the POGO PIN, the shutdown command is transmitted to the processor 20, and after the processor 20 resolves the command (at this time, an answer signal may be fed back to the charging box), when the response signal indicates that the wireless earphone receives a shutdown instruction and enters a shutdown process, the charging box sends a first power-down instruction to the control module 40 in the wireless earphone through the POGO PIN, the switch module 30 between the power module 10 and the processor 20 is controlled to be switched off, the control module 40 delays for the first time after recognizing the first power-down instruction, and the switch module 30 is switched off, so that the abnormal condition caused by power-down when the processor 20 is powered off without storing data is avoided.

For example, if the control module 40 outputs a high level signal to control the switch module 30 to be turned on, the control module 40 outputs a low level signal to control the switch module 30 to be turned off. In FIG. 5, it can be seen that during the time 0-t1, the control module 40 outputs a high signal; the control module 40 starts timing after receiving the first power down command t1, and outputs a low level signal at time t2, so that the switch module 30 is turned off.

The whole control flow can comprise the following steps:

and S1, the charging box sends a shutdown instruction to the wireless headset.

S2, the processor receives the shutdown command, and the processor shuts down.

S3, the charging box sends a first power-down instruction to the wireless earphone through the POGO PIN at the time of t 1.

And S4, the control module in the wireless earphone, such as the control chip IC, receives the first power-down instruction and analyzes the first power-down instruction.

S5, the control module starts to time, and the switch module is controlled to be switched off after delaying the first time such as t2-t 1.

It should be noted that, in other embodiments of the present application, the encoding manner of the control module 40 may also be the number of transmission pulses, for example, when the control module 40 receives 4 high levels (as shown in fig. 6) with a pulse width of 20ms, the control switch module 30 is turned off.

Therefore, the stability and the reliability of the processor are guaranteed through time delay processing, namely power failure after data are saved. In this way, current consumption is significantly reduced, increasing the storage time of the power supply module. The shutdown is carried out according to the method, only a plurality of parts of consumption such as self-consumption of a battery, an analysis control module and the like are consumed, and the power consumption of the analysis control module is very low, so that the extremely low power consumption of the system is ensured; the reliability is obviously improved, abnormal conditions such as data loss and the like in the processor caused by power failure of a power supply module in the shutdown process are avoided, so that the system is stable, and in addition, the power failure is carried out after the shutdown, so that the stability of the system is further improved; the difficulty of purchase is obviously improved, and the control chip and the switch module (MOS tube can be used) that this scheme adopted, the material is comparatively conventional material, and it is more convenient to purchase.

On the basis of the above embodiment, the following extensions of example one to example three are made:

example one:

on the basis of the above embodiment, after receiving the first power down instruction, the control module 40 delays for the first time, and then the level output by the output port changes, so that there is a problem that the user takes out the wireless headset from the charging box within the delayed time, and after a short time, the wireless headset enters a shutdown mode and cannot be used. To solve this problem, the present application further optimizes the function of the control module 40, and the control module 40 is further configured to: receiving a cover opening instruction sent by a charging box through a POGO PIN (polymer optical identification number) of a metal interface; if the cover opening instruction is received within the first time after the first power-down instruction is received, the control switch module 30 does not disconnect the connection between the power module 10 and the processor 20 after delaying the first time.

Specifically, referring to fig. 7, in the process of delaying from t1 to t2, once the control module 40 detects that the door opening command is sent from the charging box to the control module 40, it is originally required to output a low level signal to cancel at time t2, and a high level signal is still output after time t2, so that it can be ensured that the processor does not power down.

For example, the user places the headset into the charging box and closes the lid of the charging box so that the charging box charges the wireless headset. After the charging box is fully charged for the wireless headset, a shutdown instruction is sent to the processor 20 through the metal interface POGO PIN, so that the processor 20 is shut down, a first power-down instruction is sent to the control module 40 through the metal interface POGO PIN at the moment of t1, the control module 40 is delayed to power down after receiving the power-down instruction, and power down at the moment of t2 is predicted. At time t', if the control module 40 receives an uncovering command sent from the charging box through the metal interface POGO PIN, the control module controls the processor 20 not to power down at time t 2. Therefore, the problem that the earphone cannot be used due to the fact that the earphone enters a power-off mode after the wireless earphone is taken out in the time delay period is avoided.

Example two:

in this example, the processor 20 is specifically configured to: delaying the shutdown for a second time after the data is saved according to the shutdown instruction; the control module 40 is specifically configured to: after receiving the first power-down instruction, the control switch module 30 disconnects the power module 10 from the processor 20, and the time when the charging box sends the first power-down instruction is later than the time when the charging box sends the shutdown instruction by a third time. The second time is set to avoid that the processor 20 is restarted due to power failure caused by too fast shutdown after data is saved, which causes instability, and for this reason, the third time is controlled before shutdown after the data is saved, so that the third time controls the power failure time to be between the latest time for maintaining the data and the earliest time for shutdown according to the actual situation of the processor 20, that is, two critical values of the third time may be the maximum data writing time and the earliest shutdown time (the minimum data writing time + the second time), respectively.

Specifically, in the shutdown process, the shutdown function can be realized by delaying the shutdown process of the earphone, and the specific operations are as follows: after receiving the shutdown instruction, the processor 20 in the wireless headset starts the shutdown process, and after storing the data, the wireless headset is shut down in a delayed manner. As long as the processor 20 can save the data and then power down, the wireless headset system will not be affected. Because the shutdown time of the processor 20 fluctuates within a certain range, that is, the time for writing data also fluctuates, for example, 1 to 4 seconds, the processor can be completely shut down after delaying the second time, for example, 4 seconds, after writing data, that is, the processor is shut down only 5 to 9 seconds, so that the charging box only needs to send the first power-down instruction to the control module 40 at the third time, for example, 4 to 5 seconds, and the control module 40 immediately powers down after receiving the first power-down instruction, thereby ensuring that the processor is shut down and powered down, and avoiding the unstable problem that the processor is restarted and powered down due to the power-down signal after the processor is powered down.

Example three:

in this example, the control module 40 is specifically configured to: after receiving a first power-down instruction, the control switch module 30 disconnects the power module 10 from the processor 20, where the first power-down instruction is sent by the charging box after detecting that the processor 20 is powered off.

It should be noted that the solution described in example three is provided that it is necessary to ensure that the first power-down instruction is sent to the control module 40 without causing the start-up of the processor 20. Because the voltage used for sending the command to the control module 40 in some circuits is 5V, when the command is sent to the control module 40, if the processor 20 is in the power-off state at this time, the processor 20 is restarted, which may cause the wireless headset to power down when the processor 20 is started, which may cause the wireless headset to be unstable. The scheme provides a new solution, so that the power-on identification voltage of the processor 20 (voltage corresponding to the power-on instruction of the processor) is different from the detection voltage of the control module 40 (voltage corresponding to the first power-down instruction), for example, the voltage corresponding to the first power-down instruction is smaller than the voltage corresponding to the power-on instruction of the processor, or a waveform signal corresponding to the first power-down instruction is different from a waveform signal corresponding to the power-on instruction of the processor, which means that power-down can be performed after the processor 20 is shut down, thereby ensuring the stability of the system.

In this example, processor 20 may further include a detection module to detect a voltage transmitted on metal interface POGO PIN, where two voltages are transmitted on metal interface POGO PIN: the power-on identification voltage V1 of the processor 20 and the detection voltage V2 of the control module 40 are enabled to be V2 < V1, so that the first power-down instruction is sent to the control module 40 after the processor 20 is actually powered off, the power-down of the processor can be realized after the processor is powered off, and the stability of the system is ensured. Of course, the use of different voltages can also be applied to the situation that power is lost before shutdown after data is saved.

To implement the above principle, the input of the control module 40 needs to be voltage configured, as well as the detection module of the processor 20, to ensure consistency.

A switch module 30 according to one particular embodiment of the present application is described below in conjunction with fig. 8.

As shown in fig. 8, the switch module 30 according to the embodiment of the present application includes: the power supply comprises an N-type metal oxide semiconductor field effect transistor Q and a resistor R, wherein a control electrode of the N-type metal oxide semiconductor field effect transistor Q is connected with the control module 40, a first electrode of the N-type metal oxide semiconductor field effect transistor Q is connected with the power supply module 10, a second electrode of the N-type metal oxide semiconductor field effect transistor Q is connected with the processor 20, a first end of the resistor R is connected with the power supply module 10, and a second end of the resistor R is connected with the control electrode of the N-type metal oxide semiconductor field effect transistor Q.

Specifically, the charging box sends a shutdown instruction to the processor 20 through the metal interface POGO PIN so as to shutdown the processor, and at the same time, the charging box sends a first power-down instruction to the control module 40 of the wireless headset through the metal interface POGO PIN, the control module 40 outputs a corresponding level signal according to the instruction, for example, when a high level signal is output, the N-type metal oxide semiconductor field effect transistor Q is closed, and the power supply module 10 supplies power to the processor 20; when a low level signal is output, the N-type metal oxide semiconductor field effect transistor Q is turned off, the power module 10 does not supply power to the processor 20, and the wireless headset is powered off.

Another power down manner according to the embodiment of the present application is described below with reference to fig. 9.

According to another embodiment of the present application, the wireless headset controls the processor 20 to power down after saving data by controlling the power module 10 to power down.

In one particular example, the processor 20 is further configured to: sending a second power-down instruction to the power module 10 after the data is saved; the power module 10 is also configured to: and powering down after receiving the second power down instruction.

Specifically, in this embodiment, the power module 10 used in the wireless headset has a power-down function, and after the processor is powered off and stores data, a second power-down instruction is sent to the power module 10 through the I2C bus or in another manner, and the power module 10 is powered down after receiving the second power-down instruction, so that the stability of the system can be ensured, and the system is more reliable.

In another specific example, the processor 20 is further configured to: after receiving the shutdown instruction, sending a second power-down instruction to the power module 10; the power module 10 is also configured to: and delaying the power down of the fourth time after receiving the second power down instruction. The fourth time is generally set to be longer than the longest data storage time in the shutdown process, so as to ensure that the power is lost after the data is stored.

It should be noted that, in this embodiment, the power module 10 is provided with a delayed power-down function. Specifically, after the charging box sends the shutdown instruction, the shutdown instruction is sent to the processor 20 through the metal interface POGO PIN, the processor 20 sends the second power-down instruction to the power module 10 after receiving the shutdown instruction, at this time, the power module 10 does not immediately power down, if the fourth time is delayed to power down after receiving the second power-down instruction, the stability of the system can be ensured, and therefore the system is more reliable.

In summary, according to the wireless headset of the embodiment of the present application, the power module supplies power to the wireless headset, and the processor is configured to shutdown after saving the data according to the shutdown instruction, and is powered down after saving the data. The wireless earphone ensures that the processor is powered off after being completely shut down through time delay, and obviously improves the stability and reliability of the system.

Based on the above embodiment, the present application further provides a wireless headset system, which includes the charging box and the above wireless headset.

According to the wireless earphone system, the power failure after the processor is completely shut down is ensured through time delay, and the stability and the reliability of the system are remarkably improved.

Based on the above embodiment, the present application further provides a shutdown method for a wireless headset.

In an embodiment of the present application, as shown in fig. 3, a wireless headset includes: a power module 10 for supplying power to the wireless headset and a processor 20 connected to the power module.

As shown in fig. 10, the method for turning off a wireless headset according to the embodiment of the present application includes the following steps:

and S11, the processor is shut down after saving the data according to the shutdown instruction.

S12, the processor is powered down after saving the data.

In an embodiment of the application, the processor is powered down after saving the data, including: the wireless earphone controls the processor to power down after data is saved by disconnecting the power module and the processor; or the wireless earphone controls the processor to power down after the data is stored by controlling the power-down mode of the power supply module.

It should be noted that, details that are not disclosed in the power-off method of the wireless headset according to the embodiment of the present application refer to details that are disclosed in the wireless headset according to the embodiment of the present application, and detailed descriptions thereof are omitted here.

According to the shutdown method of the wireless earphone, the processor is guaranteed to be powered off after data is stored through time delay, and the stability and reliability of the system are remarkably improved.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims (15)

1. A wireless headset, comprising:

the power supply module is used for supplying power to the wireless earphone;

and the processor is connected with the power supply module and used for shutdown after the data is saved according to the shutdown instruction and powered down after the data is saved.

2. The wireless headset of claim 1, wherein the wireless headset controls the processor to power down after saving data by disconnecting the power module from the processor; or;

the wireless earphone controls the processor to power down after data is stored by controlling the power-down mode of the power supply module.

3. The wireless headset of claim 2, further comprising:

the metal interface can be connected with the charging box;

the processor is connected with the metal interface, and the processor is further configured to: receiving the shutdown instruction sent by the charging box through the metal interface; alternatively, the processor is further configured to: and receiving a shutdown instruction generated by the shutdown operation of the wireless earphone.

4. The wireless headset of claim 3, further comprising:

the power supply module is connected with the processor through the switch module;

and the control module is used for controlling the switch module to disconnect the connection between the power supply module and the processor according to a first power-down instruction so as to enable the processor to be powered down after data is stored.

5. The wireless headset of claim 4, wherein the control module is coupled to the metal interface, the control module further configured to:

and receiving the first power-down instruction sent by the charging box through the metal interface.

6. The wireless headset of claim 5, wherein the time at which the charging box sends the first power-down command is no earlier than the time at which the charging box sends the power-off command; the control module is specifically configured to:

after the first power-down instruction is received and the first time is delayed, the switch module is controlled to disconnect the power module and the processor.

7. The wireless headset of claim 6, wherein the control module is further configured to:

receiving a cover opening instruction sent by the charging box through the metal interface;

and if the cover opening instruction is received within the first time after the first power-down instruction is received, controlling the switch module to not disconnect the connection between the power supply module and the processor after the first time is delayed.

8. The wireless headset of claim 5, wherein the processor is specifically configured to: delaying the shutdown for a second time after the data is saved according to the shutdown instruction;

the control module is specifically configured to: after the first power-down instruction is received, the switch module is controlled to disconnect the power module and the processor, and the time for sending the first power-down instruction by the charging box is later than the time for sending the shutdown instruction by the charging box by a third time.

9. The wireless headset of claim 5, wherein the control module is specifically configured to:

after the first power-down instruction is received, the switch module is controlled to disconnect the connection between the power supply module and the processor, and the first power-down instruction is sent by the charging box after the processor is detected to be shut down.

10. The wireless headset of claim 9, wherein the voltage corresponding to the first power-down command is less than the voltage corresponding to the power-on command of the processor; alternatively, the first and second electrodes may be,

and the waveform signal corresponding to the first power-down instruction is different from the waveform signal corresponding to the starting instruction of the processor.

11. The wireless headset of claim 3, wherein the processor is further configured to: sending a second power-down instruction to the power module after the data is saved;

the power module is further configured to: and powering down after the second power down instruction is received.

12. The wireless headset of claim 3, wherein the processor is further configured to: after receiving the shutdown instruction, sending a second power-down instruction to the power supply module;

the power module is further configured to: and delaying the power down of a fourth time after receiving the second power down instruction.

13. A wireless headset system, comprising: a charging box and a wireless headset according to any of claims 1-12.

14. A method for powering off a wireless headset, the wireless headset comprising: the wireless earphone power supply system comprises a power supply module for supplying power to the wireless earphone and a processor connected with the power supply module, wherein the power-off method comprises the following steps:

the processor is shut down after the data is saved according to the shutdown instruction;

the processor is powered down after saving the data.

15. The method of shutdown of claim 14, wherein the processor is powered down after saving the data, comprising:

the wireless earphone controls the processor to power down after data is stored by disconnecting the power module from the processor; or;

the wireless earphone controls the processor to power down after data is stored by controlling the power-down mode of the power supply module.

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