CN113452789B - Frequency domain combining system and frequency domain combining method for forward interface - Google Patents
Frequency domain combining system and frequency domain combining method for forward interface Download PDFInfo
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Abstract
The invention provides a frequency domain combining system and a frequency domain combining method for a fronthaul interface, which comprise the following steps: the device comprises an input module, a frequency domain combining module and an output module, wherein at least one path of signal is input from the input module, and is output by the output module after time delay compensation and combination are carried out by the frequency domain combining module; the input module comprises at least one CPRI framing input unit for inputting the at least one path of signal; the frequency domain combining module is used for carrying out time delay adjustment and packet header combination on the at least one path of signals based on a preset time delay compensation mechanism to obtain adjusted packed data; the output module is used for outputting the adjusted packed data. The invention ensures that the uplink frequency domain data of each antenna can reach the upper BBU at the same time by improving the frequency domain packet transmission format in the prior forward transmission interface and adopting a time delay compensation mechanism, occupies lower transmission bandwidth and can relieve the pressure of the BBU for caching a plurality of antennas.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a frequency domain combining system and a frequency domain combining method for a fronthaul interface.
Background
In a 5G base station system, the function of an AAU (Active Antenna Unit) is introduced, and in particular, the cascade connection among multiple AAUs relates to a combining processing scheme of a forward interface.
The Interface between BBU and AAU is called a fronthaul Interface, and generally adopts CPRI (Common Public Radio Interface) or enhanced Common Public Radio Interface (eCPRI) protocol. Unlike 4G systems, the concept of frequency domain processing is enhanced in AAU, i.e. the CPRI/eccri protocol increases the need for transmitting frequency domain data of each antenna/channel, as shown in fig. 1. In an AAU cascade environment, uplink frequency domain data of the current-level AAU and uplink frequency domain data of the next-level AAU need to be merged together and uploaded to a BBU through a CPRI/eCPRI interface. The local AAU and the subordinate AAU correspond to different signal sources of the radio frequency channel, and cannot be directly combined in the frequency domain, and different AAUs can be shared by a packet header (carrying information such as a slot number, a symbol number, and a PRB number) in a frequency domain data packet. A more direct approach is to pack the frequency domain data of different antennas/channels separately and upload them sequentially, as shown in fig. 2.
In the above combining scheme, the multi-channel data needs to be combined and aligned on the BBU, which increases the resource overhead and the operation load of the BBU, and packet header information of different channels is repeatedly transmitted, resulting in low transmission efficiency of the forwarding interface, i.e. no more transmission channels can be supported under the transmission bandwidth of the same rate, and in addition, carrier aggregation is realized on the BBU, depending on the 1588 time service system.
Disclosure of Invention
The invention provides a frequency domain combining system and a frequency domain combining method for a forward interface, which are used for overcoming the defects in the prior art.
In a first aspect, the present invention provides a frequency domain combining system for a forwarding interface, including:
the device comprises an input module, a frequency domain combining module and an output module, wherein at least one path of signal is input from the input module, and is output by the output module after time delay compensation and combination are carried out by the frequency domain combining module;
the input module comprises at least one CPRI framing input unit for inputting the at least one path of signal;
the frequency domain combining module is used for carrying out time delay adjustment and packet header combination on the at least one path of signals based on a preset time delay compensation mechanism to obtain adjusted packed data;
the output module is used for outputting the adjusted packed data.
In one embodiment, the input module includes a present-stage CPRI framing input unit and a cascade interface CPRI receiving unit;
the current-stage CPRI framing input unit is used for outputting current-stage signal data and a current-stage signal packet header;
the cascade interface CPRI receiving unit is used for outputting lower signal data and a lower signal packet header.
In one embodiment, the frequency domain combining module comprises a current-level RAM unit, a current-level RAM write control unit, a current-level RAM read control unit, a lower-level RAM write control unit, a lower-level RAM read control unit, a frame header control unit, a Head sample-keeping unit and a MUX unit;
the local-level RAM unit is used for storing the local-level signal data based on preset cache depth time, the preset cache depth time is larger than the upper-level BBU advance, and the read address and the write address of the local-level RAM unit are made to poll an integer circle;
the current-stage RAM write control unit is used for sequentially writing the signal data output by the current-stage CPRI framing input unit into the current-stage RAM unit;
the local-level RAM reading control unit is used for reading the local-level signal data cached in the local-level RAM unit based on the triggering of the local-level CPRI frame header signal;
the lower level RAM unit is used for storing the lower level signal data;
the lower RAM write control unit is used for sequentially writing the signal data output by the CPRI receiving unit of the cascade interface into the lower RAM unit;
the Head sample keeping unit is used for recording the packet header information of each signal slice chip in the lower-level RAM unit and providing packet header matching detection with the data stream output by the current-level RAM unit;
the lower-level RAM read control unit is used for monitoring the packet Head of the current-level signal output by the current-level RAM unit in real time by taking a chip as a unit and inquiring whether a matched sample-reserving record exists in the Head sample-reserving unit;
the frame header control unit is used for generating the preset cache depth time;
and the MUX unit is used for converging the data streams output by the current-level RAM unit and the lower-level RAM unit to obtain a merged data stream.
In one embodiment, the output module comprises a GT unit for outputting the adjusted packetized data to an upper level BBU.
In a second aspect, the present invention further provides a frequency domain combining method for a fronthaul interface, including:
determining at least one signal;
performing delay adjustment and packet header combination on the at least one path of signal based on a preset delay compensation mechanism to obtain adjusted packed data;
and outputting the adjusted packed data to a superior BBU unit.
In one embodiment, performing delay adjustment and packet header combination on the at least one signal based on a preset delay compensation mechanism to obtain adjusted packed data includes:
respectively acquiring the present-level signal data, the present-level signal packet header, the lower-level signal data and the lower-level signal packet header in the at least one path of signal;
when the rising edge of the head of the current-stage signal packet arrives, the writing address of the current-stage RAM unit returns to 0, the lower-stage signal data is written into the address 0, and when the next clock beat is reached, the writing address is added by 1 until the writing address of the current-stage RAM unit automatically returns to 0 at the next clock beat after the writing address of the current-stage RAM unit is accumulated to the maximum value;
when the rising edge of the frame head signal of the CPRI frame comes, the reading address of the RAM unit at the current level returns to 0, when the next clock beat is reached, the reading address is added with 1 until the reading address of the RAM unit at the current level is automatically returned to 0 at the next clock beat after the reading address of the RAM unit at the current level is accumulated to the maximum value;
if the current-level signal packet header output by the current-level RAM unit matches the lower-level signal packet header cached in a lower-level RAM unit, caching a plurality of signal slices by the lower-level RAM unit;
recording the packet header information of each signal slice chip in the lower-level RAM unit in a Head sample retention unit, and providing packet header matching detection with the output data stream of the current-level RAM unit;
monitoring the packet Head of the signal of the current level output by the RAM unit of the current level in real time by taking a chip as a unit in a read control unit of a lower level RAM, and inquiring whether a matched sample reserving record exists in a Head sample reserving unit;
and merging the data streams output by the current-level RAM unit and the lower-level RAM unit by the MUX unit to obtain a merged data stream.
In an embodiment, the merging, by the MUX unit, the data streams output by the present-stage RAM unit and the lower-stage RAM unit to obtain a merged data stream, further includes:
delaying the data stream output by the RAM unit of the current stage by a plurality of beats based on a preset register beat mode to obtain the delayed data stream;
and performing preset addition operation on the delayed data stream and the data stream output by the lower-level RAM unit based on the matching result of the lower-level RAM read control unit to obtain a combined data stream.
In one embodiment, the lower level RAM read control unit matches results, comprising:
judging whether the current beat is a frequency domain field, if so, adopting the signal data of the current stage to replace the part of the merged data stream except the frequency domain field;
if the lower-level RAM read control unit cannot acquire the matching packet header, the corresponding lower-level AAU does not participate in combining;
if the CPRI/eCPRI protocol of the subordinate AAU cannot be synchronized, the subordinate AAU does not participate in combining;
if the cell of the current-level AAU is not activated, the CPRI/eCPRI protocol of the next-level AAUC is synchronous and the cell is activated, the current-level AAU does not participate in the combining way.
In a third aspect, the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of any of the foregoing frequency domain combining methods for the forwarding interfaces when executing the program.
In a fourth aspect, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the frequency domain combining method for a forwarding interface as described in any one of the above.
The frequency domain combining system and the frequency domain combining method of the fronthaul interface provided by the invention have the advantages that the uplink frequency domain data of each antenna can reach the upper BBU at the same time by improving the frequency domain packet transmission format in the existing fronthaul interface and adopting a time delay compensation mechanism, the lower transmission bandwidth is occupied, and the pressure of the BBU for caching multiple antennas can be relieved.
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In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of the function of an AAU in a 5G base station provided in the prior art;
fig. 2 is a schematic diagram of a frequency domain data packet transmission format in a 5G forwarding interface provided by the prior art;
fig. 3 is a schematic diagram of an improvement of a frequency domain data packet transmission format in a 5G forwarding interface provided by the present invention;
FIG. 4 is a block diagram of a frequency domain combining scheme provided by the present invention;
fig. 5 is a diagram of the input and output alignment relationship of the frequency domain combining module provided by the present invention;
FIG. 6 is a timing diagram of a RAM0 write control module provided by the present invention;
FIG. 7 is a timing diagram of a read control module of RAM0 according to the present invention;
fig. 8 is a schematic flow chart of a frequency domain combining method for a forwarding interface according to the present invention;
FIG. 9 is a schematic diagram of frame header timing relationship of two-stage AAU cascade connection provided by the present invention;
FIG. 10 is a schematic diagram of frame header time relationship of three-stage AAU cascade connection provided by the present invention;
fig. 11 is a schematic structural diagram of an electronic device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Aiming at the problems in the prior art, the frequency domain packet transmission format of the forwarding interface is improved, as shown in fig. 3, on the premise that the data format is defined, the AAU combines the AAU data of the current stage and the following AAUs data by implementing a frequency domain combining module, uniformly packs the combined data and sends the packed data to the BBU, namely, the function of antenna convergence is implemented in the AAU, and partial baseband processing of the original BBU is sunk to the AAU for implementation so as to share the load and cost pressure of the BBU.
Fig. 4 is a block diagram of a frequency domain combining scheme provided by the present invention, as shown in fig. 4, including:
the device comprises an input module, a frequency domain combining module and an output module, wherein at least one path of signal is input from the input module, and is output by the output module after being subjected to time delay compensation and combining by the frequency domain combining module;
the input module comprises at least one CPRI framing input unit for inputting the at least one path of signal;
the frequency domain combining module is used for carrying out time delay adjustment and packet header combination on the at least one path of signals based on a preset time delay compensation mechanism to obtain adjusted packed data;
the output module is used for outputting the adjusted packed data.
The input module comprises a current-stage CPRI framing input unit and a cascade interface CPRI receiving unit;
the current-stage CPRI framing input unit is used for outputting current-stage signal data and a current-stage signal packet header;
the cascade interface CPRI receiving unit is used for outputting lower signal data and a lower signal packet header.
The frequency domain combining module comprises a current-level RAM unit, a current-level RAM writing control unit, a current-level RAM reading control unit, a lower-level RAM writing control unit, a lower-level RAM reading control unit, a frame header control unit, a Head sample-reserving unit and a MUX unit;
the local-level RAM unit is used for storing the local-level signal data based on preset cache depth time, the preset cache depth time is larger than the upper-level BBU advance, and the read address and the write address of the local-level RAM unit are made to poll an integer circle;
the current-stage RAM write control unit is used for sequentially writing the signal data output by the current-stage CPRI framing input unit into the current-stage RAM unit;
the local-level RAM reading control unit is used for reading the local-level signal data cached in the local-level RAM unit based on the triggering of the local-level CPRI frame header signal;
the lower level RAM unit is used for storing the lower level signal data;
the lower RAM write control unit is used for sequentially writing the signal data output by the CPRI receiving unit of the cascade interface into the lower RAM unit;
the Head sample reserving unit is used for recording the packet header information of each signal slice chip in the lower-level RAM unit and providing packet header matching detection with the data stream output by the current-level RAM unit;
the lower-level RAM read control unit is used for monitoring the packet Head of the current-level signal output by the current-level RAM unit in real time by taking a chip as a unit and inquiring whether a matched sample-reserving record exists in the Head sample-reserving unit;
the frame header control unit is used for generating the preset cache depth time;
and the MUX unit is used for converging the data streams output by the current-level RAM unit and the lower-level RAM unit to obtain a merged data stream.
The output module comprises a GT unit, and the GT unit is used for outputting the adjusted packed data to a superior BBU.
Specifically, the frequency domain combining system of the fronthaul interface provided by the invention comprises an input module, a frequency domain combining module and an output module.
The frequency domain combining module comprises a RAM0 unit, a RAM0 writing control unit, a RAM0 reading control unit, a RAM1 unit, a RAM1 writing control unit, a RAM1 reading control unit, a frame header control unit, a Head sample reserving unit and a MUX unit.
The input of the frequency domain combining module is from two units, namely two parts of the input module, namely, the current-stage CPRI framing unit, and the other is the cascade interface CPRI receiving unit, namely, the combination of the two signals is realized. The data after combining is sent to the upper unit of the AAU through the GT, which is the Gigabyte transmitter, and is the hardware unit for CPRI protocol transmission. In order to achieve the design effect, the CPRI framing unit and the CPRI receiving unit at the cascade interface need to provide CPRI data and frame headers aligned with the CPRI data. As shown in fig. 4, local _ tx _ data and local _ tx _ hd respectively indicate data and a frame header of a CPRI framing unit at the current stage, and next _ cppri _ data and next _ cppri _ hd respectively indicate data and a frame header of a CPRI receiving unit at the cascade port. Since the frame structure defined in the CPRI protocol has a periodic characteristic (generally 10ms, and unless otherwise specified, the following is represented by a 10ms period), the alignment relationship between the frame header and the data can be expressed as follows: when the rising edge of the frame header comes, it corresponds exactly to the beginning of the 10ms period in the data stream. One of the problems to be solved by the frequency domain combining module is that frame headers of the CPRI framing unit and the CPRI receiving unit at the cascade interface are aligned. On the other hand, since different AAUs have chip-level delay differences during frequency domain packing, the combination can be realized only by performing header alignment after frame header alignment, and the alignment relationship is shown in fig. 5.
It should be noted that the RAM0 is a main medium for storing the local _ tx _ data stream, and is a standard RAM unit. The cache depth of the RAM0 needs to be larger than the advance Ta of the BBU. Considering the periodicity (10ms) of the RAM0 read and write triggers, the design must ensure that the RAM's read and write addresses are polling exactly an integer number of turns within a 10ms period. By combining these two conditions, an optimal RAM0 depth can be obtained, which can meet design requirements and save resources.
The RAM0 write control unit writes the data output by the CPRI framing unit in the RAM0 unit in sequence. When the local _ tx _ hd rising edge arrives, the write address of the RAM0 is returned to 0, while next _ cpri _ data is written to address 0. And adding 1 to the write address in the next clock beat, and so on. When the write address of the RAM0 is accumulated to the maximum value, it is automatically reset to 0 at the next clock cycle. Fig. 6 shows the timing of writing control units to RAM0, and the maximum address value 0x7FF is merely exemplary.
The RAM0 read control unit reads out the local _ tx _ data stream buffered in the RAM0 under the trigger of the local _ cpri _ hd _ pre signal. When the rising edge of local _ cpri _ hd _ pre arrives, the read address of RAM0 is returned to 0. And when the next clock beat is started, adding 1 to the read address, and so on. When the read address of the RAM0 is accumulated to the maximum value, it is automatically reset to 0 in the next clock cycle. FIG. 7 shows the timing of the RAM0 read control unit, where the maximum address value 0x7FF is exemplary only.
The RAM1 is the main medium for storing the next _ cpri _ data stream, and is a standard RAM unit. In terms of design effect, the local _ tx _ data stream is delayed by the RAM0 and is roughly aligned with the next _ cpri _ data stream, and there is only a few chip deviations. The premise that the final two-stage AAU frequency domain data can be combined is that the header information in the data stream output by the RAM0 can be matched with the buffer header in the RAM 1. Therefore, the RAM1 only needs to buffer several chips, and specifically, several chips need to be considered comprehensively according to the packing error and the delay measurement error of the AAU system.
The design principle of the RAM1 write control unit is the same as that of the RAM0 write control unit, differing only in the object of processing.
The Head sample keeping unit records the packet header information in each chip in the RAM1, and the user subsequently detects the matching of the packet header in the output data stream of the RAM 0.
The RAM1 read control unit monitors the packet header output in the RAM0 in real time by taking chip as a unit, and inquires whether a sample reservation record which can be matched with the Head sample reservation unit exists in the Head sample reservation unit. Here, the matching means that the header information is the same. If the chip can be matched, the chip can participate in the combining. The RAM1 read control unit outputs the matching result to the MUX unit, and simultaneously reads out all information of the matched upper chip from the RAM 1.
The MUX unit merges the data streams output by the RAM0 unit and the RAM1 unit, and finally forms a data stream to the GT unit.
The invention ensures that the uplink frequency domain data of each antenna can reach the upper BBU at the same time by improving the frequency domain packet transmission format in the prior forward transmission interface and adopting a time delay compensation mechanism, occupies lower transmission bandwidth and can relieve the pressure of the BBU for caching a plurality of antennas.
Fig. 8 is a schematic flow diagram of a frequency domain combining method for a forwarding interface provided by the present invention, as shown in fig. 8, including:
s1, determining at least one path of signal;
s2, performing delay adjustment and packet header combination on the at least one path of signal based on a preset delay compensation mechanism to obtain adjusted packed data;
and S3, outputting the adjusted packed data to an upper BBU unit.
Performing delay adjustment and packet header combination on the at least one path of signal based on a preset delay compensation mechanism to obtain adjusted packed data, including:
respectively acquiring the present-level signal data, the present-level signal packet header, the lower-level signal data and the lower-level signal packet header in the at least one path of signal;
when the rising edge of the header of the current-stage signal packet arrives, the write address of the current-stage RAM unit returns to 0, the lower-stage signal data is written into the address 0, and when the next clock beat is reached, the write address is added by 1 until the write address of the current-stage RAM unit is automatically returned to 0 at the next clock beat after being accumulated to the maximum value;
when the rising edge of the frame head signal of the CPRI frame comes, the reading address of the RAM unit at the current level returns to 0, when the next clock beat is reached, the reading address is added with 1 until the reading address of the RAM unit at the current level is automatically returned to 0 at the next clock beat after the reading address of the RAM unit at the current level is accumulated to the maximum value;
if the current-level signal packet header output by the current-level RAM unit matches the lower-level signal packet header cached in a lower-level RAM unit, caching a plurality of signal slices by the lower-level RAM unit;
recording the packet header information of each signal slice chip in the lower-level RAM unit in a Head sample-keeping unit, and providing packet header matching detection with the data stream output by the current-level RAM unit;
monitoring the packet Head of the signal of the current level output by the RAM unit of the current level in real time by taking a chip as a unit in a read control unit of a lower level RAM, and inquiring whether a matched sample reserving record exists in a Head sample reserving unit;
and merging the data streams output by the current-level RAM unit and the lower-level RAM unit by using a MUX unit to obtain a merged data stream.
The merging, by the MUX unit, the data streams output by the present-level RAM unit and the lower-level RAM unit to obtain a merged data stream, further comprising:
delaying the data stream output by the RAM unit of the current stage by a plurality of beats based on a beat printing mode of a preset register to obtain the delayed data stream;
and performing preset addition operation on the delayed data stream and the data stream output by the lower-level RAM unit based on the matching result of the lower-level RAM read control unit to obtain a merged data stream.
Specifically, the frequency domain combining method for the forwarding interface provided by the invention mainly operates in a frequency domain combining module, and the inputs of the frequency domain combining module are from two modules, one is a current-stage CPRI framing unit, and the other is a cascade interface CPRI receiving unit, namely, the signals of the two modules are combined. The data after combining is sent to the upper unit of the AAU through the GT, which is the Gigabyte transmitter, and is the hardware unit for CPRI protocol transmission. In order to achieve the design effect, the CPRI framing unit and the CPRI receiving unit at the cascade interface need to provide CPRI data and frame headers aligned with the CPRI data. The local _ tx _ data and the local _ tx _ hd respectively represent data and a frame header of a CPRI framing unit at the current stage, and the next _ cppri _ data and the next _ cppri _ hd respectively represent data and a frame header of a CPRI receiving unit at the cascade port. Since the frame structure defined in the CPRI protocol has a periodic characteristic (generally 10ms, and unless otherwise specified, the following is represented by a 10ms period), the alignment relationship between the frame header and the data can be expressed as follows: when the rising edge of the frame header comes, it corresponds exactly to the beginning of the 10ms period in the data stream. One of the problems to be solved by the frequency domain combining module is frame header alignment between the CPRI framing unit of the current stage and the CPRI receiving unit of the cascade interface. On the other hand, since different AAUs have chip-level delay differences during frequency domain packing, the combination can be realized only by performing header alignment after frame header alignment.
The RAM0 is a main medium for storing local _ tx _ data stream, and is a standard RAM unit. The cache depth of the RAM0 needs to be larger than the advance Ta of the BBU. On the other hand, considering the periodicity (10ms) of the read and write triggers of RAM0, it is a design guarantee that the read and write addresses of the RAM are polling exactly an integer number of turns in a 10ms cycle. By combining these two conditions, an optimal RAM0 depth can be obtained, which can meet design requirements and save resources. The RAM0 write control unit writes the data output by the CPRI framing unit in the RAM0 unit in sequence. When the local _ tx _ hd rising edge arrives, the write address of the RAM0 is returned to 0, while next _ cpri _ data is written to address 0. And adding 1 to the write address in the next clock beat, and so on. When the write address of the RAM0 is accumulated to the maximum value, it is automatically reset to 0 at the next clock cycle. The RAM0 read control unit reads out the local _ tx _ data stream buffered in the RAM0 under the trigger of the local _ cpri _ hd _ pre signal. When the local _ cpri _ hd _ pre rising edge arrives, the read address of RAM0 goes to 0. And when the next clock beat is started, adding 1 to the read address, and so on. When the read address of the RAM0 is accumulated to the maximum value, it is automatically reset to 0 in the next clock cycle.
The RAM1 is the main medium for storing the next _ cpri _ data stream, and is a standard RAM unit. In terms of design effect, after the local _ tx _ data stream is delayed by the RAM0, the local _ tx _ data stream is roughly aligned with the next _ cpri _ data stream, and only a few chips of deviation exist. The premise that the final two-stage AAU frequency domain data can be combined is that the header information in the data stream output by the RAM0 can be matched with the buffer header in the RAM 1. Therefore, the RAM1 only needs to cache a few chips. Specifically, for several chips, the packing error and the delay measurement error of the AAU system need to be considered comprehensively. The design principle of the RAM1 write control unit is the same as that of the RAM0 write control unit, and only the object of processing is different. And a Head sample keeping unit for recording the packet header information in each chip in the RAM1, and subsequently detecting the matching of the user with the packet header in the data stream output by the RAM 0. The RAM1 reads the control unit, monitors the packet header output in the RAM0 in real time by taking chip as a unit, and inquires whether there is a sample record which can be matched with the Head sample unit in the Head sample unit. Here, the matching means that the header information is the same. If the chip can be matched, the chip can participate in the combining. The RAM1 read control unit outputs the matching result to the MUX unit, and simultaneously reads out all information of the matched upper chip from the RAM 1. The MUX unit merges the data streams output by the RAM0 unit and the RAM1 unit, and finally forms a data stream to the GT unit.
The invention combines the AAU data of the current level and below by combining the frequency domain in the AAU, uniformly packs the combined data and sends the packed data to the BBU, realizes the antenna convergence function in the AAU, and sinks part of the baseband processing function of the original BBU to the AAU to realize so as to share the load and cost pressure of the BBU.
Based on the above embodiment, the lower RAM read control unit matching result includes:
judging whether the current beat is a frequency domain field, if so, replacing the part of the frequency domain field in the merged data stream with the signal data of the current stage;
if the lower-level RAM read control unit cannot acquire the matching packet header, the corresponding lower-level AAU does not participate in combining;
if the CPRI/eCPRI protocol of the subordinate AAU cannot be synchronized, the subordinate AAU does not participate in combining;
if the cell of the current-level AAU is not activated, the CPRI/eCPRI protocol of the next-level AAUC is synchronous and the cell is activated, the current-level AAU does not participate in the combining way.
Specifically, since the read address output by the RAM1 read control unit depends on the result of the data stream of the RAM0 unit, and there is a certain time delay in reading data from the RAM1, the data streams output by the RAM0 unit and the RAM1 unit inevitably have a deviation of several clock cycles, and cannot be directly combined. Here, the output data stream of the RAM0 unit is delayed by several beats (specifically, several beats are delayed based on design) by means of register beat, and the delayed data is added (bitwise exclusive or) to the data stream of the RAM 1. Considering the fact that the addition operation of the two is not always effective, a switch (i.e. the matching result of the RAM1 read control unit) is needed to control whether the combination is currently enabled (addition operation). The specific reason is as follows:
1) from the service perspective, only frequency domain data needs to be combined between the current stage AAU (corresponding to the data stream output by the RAM0 unit) and the next stage AAU (corresponding to the data stream output by the RAM1 unit), while the data streams of the RAM0 unit and the RAM1 unit are the whole CPRI/eccri data, so that it needs to determine whether the current beat is a frequency domain field. Except for the frequency domain field, the combined data stream is uniformly replaced by the data stream of the AAU of the current stage;
2) if the RAM1 read control unit cannot find the matched packet header, the next-level AAU does not participate in the combining, and only outputs the frequency domain data of the current-level AAU;
3) if the CPRI/eCPRI protocol of the subordinate AAU cannot be synchronized, the subordinate AAU does not participate in combining;
4) if the cell of the current-level AAU is not activated (the frequency domain data is not available), but the CPRI/eCPRI protocol of the next-level AAU is synchronous and the cell is activated, the frequency domain data of the current-level AAU does not participate in combining.
In addition, the frame header relationship between the modules needs to be combed:
in fig. 4, local _ cppri _ hd _ pre triggers RAM0 read control unit to read out the data stream from RAM0 unit and then through MUX unit output with fixed delay (typically within 10 clock ticks), which is ignored here for the time being. Therefore, local _ cpri _ hd _ pre is temporarily equivalent to local _ cpri _ hd;
the time delay between local _ tx _ hd and local _ cppri _ hd _ pre, that is, the time for buffering the frequency domain data of the current stage of the AAU in the RAM0 unit, is generated by the frame header control unit;
and the local _ tx _ hd _ pre triggers the CPRI/eCPRI frame of the current CPRI framing unit group to output local _ tx _ hd. Empirically, both delays are also small, and are ignored here for the moment. If the delay is so great that it is not negligible in the actual design, it can be compensated for in the control unit. Therefore, local _ tx _ hd _ pre is temporarily equivalent to local _ tx _ hd;
the delay of the lower AAU data in the RAM1 is equivalent to the delay of next _ cpri _ hd and local _ cpri _ hd, regardless of the processing delay of the MUX unit. This delay will be represented in fig. 9 by Δ T.
In summary, the above-mentioned time relationship is represented by fig. 9, in which a signal beginning with "AAU 1" indicates a frame header in the first-stage AAU, and a signal beginning with "AAU 2" indicates a frame header in the second-stage AAU. In fig. 9, the local _ tx _ hd indicates the local _ tx _ hd frame header of each AAU stage, and the time difference with respect to the GPS 10ms air interface is fixed. The BBU _ rx _ cpri _ hd is a theoretical time point when the BBU receives the uplink cppri frame header, and the expected effect of the design is that the time difference between BBU _ rx _ cpri _ hd and the GPS 10ms air interface is fixed (not changed with the remote length of the optical fiber), that is, the time delay from local _ tx _ hd to BBU _ rx _ cpri _ hd is fixed, which is denoted as Ta in fig. 9. L1 represents the fiber delay between the BBU and the first stage AAU, and L2 represents the fiber delay between the BBU and the second stage AAU (this delay is the cumulative delay, i.e., L1 plus the delay between the first stage AAU and the second stage AAU).
It should be noted that the dotted arrow in fig. 9 is not the actual position of the frame header, but is marked in the figure for reference, and the solid line beside the dotted arrow indicates the actual position of the frame header. For example, AAU2_ local _ cpri _ hd, the time at which local _ cpri _ hd of the second level AAU advances from bbu _ rx _ cpri _ hd is (L2+ (Δ T)). AAU2_ local _ cpri _ hd is delayed by the fiber to the first level AAU, i.e., AAU1_ next _ cpir _ hd in the figure, which is ahead of bbu _ rx _ cpri _ hd by (L1+ Δ T). And delta T is the time delay generated by the 2 nd-level frequency domain data combining. The frame header after the two-stage frequency domain data combination is aau1_ local _ cpri _ hd, and the time ahead of BBU _ rx _ cpri _ hd is just L1, namely the BBU can be reached on time.
Based on the frame header time relationship of the two-stage AAU cascade, it is not difficult to obtain the time delay relationship of three-stage or more AAU cascades, and fig. 10 depicts the time delay relationship of three-stage AAU cascades.
It can be obtained that the time that local _ cpri _ hd in the nth stage RRU advances from bbu _ rx _ cpri _ hd is Ln + (n-1) × Δ T, where Ln is the accumulated fiber delay between the nth stage RRU and the AAU.
The frame header control unit in fig. 4 may obtain Ln according to the delay measurement result, and calculate and provide local _ cpri _ hd _ pre and local _ tx _ hd _ pre according to the stage number where the current RRU is located. In light of the foregoing description, local _ cpri _ hd _ pre is substantially equivalent to local _ cpri _ hd, and local _ tx _ hd _ pre is substantially equivalent to local _ tx _ hd. The actual time difference can be easily compensated in the frame header control unit.
Fig. 11 illustrates a physical structure diagram of an electronic device, and as shown in fig. 11, the electronic device may include: a processor (processor)1110, a communication Interface (Communications Interface)1120, a memory (memory)1130, and a communication bus 1140, wherein the processor 1110, the communication Interface 1120, and the memory 1130 communicate with each other via the communication bus 1140. Processor 1110 may invoke logic instructions in memory 1130 to perform a fronthaul interface frequency domain combining method comprising: determining at least one path of signal; performing delay adjustment and packet header combination on the at least one path of signal based on a preset delay compensation mechanism to obtain adjusted packed data; and outputting the adjusted packed data to a superior BBU unit.
In addition, the logic instructions in the memory 1130 may be implemented in software functional units and stored in a computer readable storage medium when sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention or a part thereof which substantially contributes to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, the computer program includes program instructions, when the program instructions are executed by a computer, the computer is capable of executing the fronthaul interface frequency domain combining method provided by the above methods, the method includes: determining at least one path of signal; performing delay adjustment and packet header combination on the at least one path of signal based on a preset delay compensation mechanism to obtain adjusted packed data; and outputting the adjusted packed data to a superior BBU unit.
In yet another aspect, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, the computer program being implemented by a processor to perform the foregoing methods for frequency-domain combining of forwarding interfaces, the methods including: determining at least one signal; performing delay adjustment and packet header combination on the at least one path of signal based on a preset delay compensation mechanism to obtain adjusted packed data; and outputting the adjusted packed data to a superior BBU unit.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A frequency domain combining system of a forward interface comprises: the device comprises an input module, a frequency domain combining module and an output module, wherein at least one path of signal is input from the input module, and is output by the output module after time delay compensation and combination are carried out by the frequency domain combining module;
the input module comprises at least one CPRI framing input unit for inputting the at least one path of signal;
the frequency domain combining module is used for carrying out time delay adjustment and packet header combination on the at least one path of signals based on a preset time delay compensation mechanism to obtain adjusted packed data;
the output module is used for outputting the adjusted packed data.
2. The frequency-domain combining system of the forwarding interface of claim 1, wherein the input module comprises a present-stage CPRI framing input unit and a cascade-port CPRI receiving unit;
the current-stage CPRI framing input unit is used for outputting current-stage signal data and a current-stage signal packet header;
the cascade interface CPRI receiving unit is used for outputting lower signal data and a lower signal packet header.
3. The fronthaul interface frequency-domain combining system according to claim 2, wherein the frequency-domain combining module comprises a local RAM unit, a local RAM write control unit, a local RAM read control unit, a lower RAM write control unit, a lower RAM read control unit, a frame header control unit, a Head sample retention unit, and a MUX unit;
the local-level RAM unit is used for storing the local-level signal data based on preset cache depth time, the preset cache depth time is larger than the upper-level BBU advance, and the read address and the write address of the local-level RAM unit are made to poll an integer circle;
the current-stage RAM write control unit is used for sequentially writing the signal data output by the current-stage CPRI framing input unit into the current-stage RAM unit;
the local-level RAM reading control unit is used for reading the local-level signal data cached in the local-level RAM unit based on the triggering of the local-level CPRI frame header signal;
the lower level RAM unit is used for storing the lower level signal data;
the lower RAM write control unit is used for sequentially writing the signal data output by the CPRI receiving unit of the cascade interface into the lower RAM unit;
the Head sample reserving unit is used for recording the packet header information of each signal slice chip in the lower-level RAM unit and providing packet header matching detection with the data stream output by the current-level RAM unit;
the lower-level RAM read control unit is used for monitoring the packet Head of the current-level signal output by the current-level RAM unit in real time by taking a chip as a unit and inquiring whether a matched sample-reserving record exists in the Head sample-reserving unit;
the frame header control unit is used for generating the preset cache depth time;
and the MUX unit is used for converging the data streams output by the current-level RAM unit and the lower-level RAM unit to obtain a merged data stream.
4. The fronthaul interface frequency-domain combiner system of claim 2, wherein the output module comprises a GT unit configured to output the adjusted packetized data to an upper level BBU.
5. A frequency domain combining method for a forwarding interface is based on the frequency domain combining system for the forwarding interface of any claim 1 to 4, and is characterized by comprising the following steps:
determining at least one path of signal;
performing delay adjustment and packet header combination on the at least one path of signal based on a preset delay compensation mechanism to obtain adjusted packed data;
and outputting the adjusted packed data to a superior BBU unit.
6. The frequency domain combining method of the forwarding interface of claim 5, wherein the performing delay adjustment and packet header combination on the at least one signal based on a preset delay compensation mechanism to obtain adjusted packed data comprises:
respectively acquiring the present-level signal data, the present-level signal packet header, the lower-level signal data and the lower-level signal packet header in the at least one path of signal;
when the rising edge of the header of the current-stage signal packet arrives, the write address of the current-stage RAM unit returns to 0, the lower-stage signal data is written into the address 0, and when the next clock beat is reached, the write address is added by 1 until the write address of the current-stage RAM unit is automatically returned to 0 at the next clock beat after being accumulated to the maximum value;
when the rising edge of the frame head signal of the CPRI frame comes, the reading address of the RAM unit at the current level returns to 0, when the next clock beat is reached, the reading address is added with 1 until the reading address of the RAM unit at the current level is automatically returned to 0 at the next clock beat after the reading address of the RAM unit at the current level is accumulated to the maximum value;
if the current-level signal packet header output by the current-level RAM unit matches the lower-level signal packet header cached in a lower-level RAM unit, caching a plurality of signal slices by the lower-level RAM unit;
recording the packet header information of each signal slice chip in the lower-level RAM unit in a Head sample retention unit, and providing packet header matching detection with the output data stream of the current-level RAM unit;
monitoring the packet Head of the signal of the current level output by the RAM unit of the current level in real time by taking a chip as a unit in a read control unit of a lower level RAM, and inquiring whether a matched sample reserving record exists in a Head sample reserving unit;
and merging the data streams output by the current-level RAM unit and the lower-level RAM unit by using a MUX unit to obtain a merged data stream.
7. The frequency-domain combining method for forwarding interface as claimed in claim 6, wherein the merging, by the MUX unit, the data streams output by the present RAM unit and the lower RAM unit to obtain a merged data stream further comprises:
delaying the data stream output by the RAM unit of the current stage by a plurality of beats based on a beat printing mode of a preset register to obtain the delayed data stream;
and performing preset addition operation on the delayed data stream and the data stream output by the lower-level RAM unit based on the matching result of the lower-level RAM read control unit to obtain a combined data stream.
8. The frequency-domain combining method for the forwarding interface of claim 7, wherein the matching result of the lower RAM read control unit comprises:
judging whether the current beat is a frequency domain field, if so, adopting the signal data of the current stage to replace the part of the merged data stream except the frequency domain field;
if the lower-level RAM read control unit cannot acquire the matching packet header, the corresponding lower-level AAU does not participate in combining;
if the CPRI/eCPRI protocol of the subordinate AAU cannot be synchronized, the subordinate AAU does not participate in combining;
if the cell of the current-level AAU is not activated, the CPRI/eCPRI protocol of the next-level AAUC is synchronous and the cell is activated, the current-level AAU does not participate in the combining way.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the frequency domain combining method according to any one of claims 5 to 8 when executing the program.
10. A non-transitory computer-readable storage medium, having stored thereon a computer program, wherein the computer program, when being executed by a processor, implements the steps of the frequency-domain combining method for forwarding interfaces according to any one of claims 5 to 8.
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| CN111373838A (en) * | 2017-11-24 | 2020-07-03 | 华为技术有限公司 | Method, base station and system for transmitting uplink signal |
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