CN113452367A

CN113452367A - Oscillation circuit and self-starting control circuit

Info

Publication number: CN113452367A
Application number: CN202010227471.1A
Authority: CN
Inventors: 王钧弘
Original assignee: Himax Technologies Ltd
Current assignee: Himax Technologies Ltd
Priority date: 2020-03-27
Filing date: 2020-03-27
Publication date: 2021-09-28

Abstract

A self-starting control circuit suitable for an oscillating circuit comprises a state circuit, a reset circuit and a control circuit, wherein the state circuit generates a reset signal according to the level of a control voltage of a voltage-controlled oscillator of the oscillating circuit; and a starting circuit for generating an enabling signal according to the reset signal so as to start the voltage-controlled oscillator.

Description

Oscillation circuit and self-starting control circuit

[ technical field ] A method for producing a semiconductor device

The present invention relates to an oscillator, and more particularly, to a self-start control circuit for an oscillator.

[ background of the invention ]

An oscillator is an electronic circuit that generates a periodic oscillating signal, and is used as a reference for coordinating various circuits in an electronic system.

An oscillator (e.g., a voltage-controlled oscillator) may be used in an oscillating circuit, such as a frequency-locked loop (PLL) or a phase-locked loop (PLL). The oscillator may not be able to oscillate at some point, and therefore some mechanism is needed to start up or wake up the oscillator to resume oscillation.

[ summary of the invention ]

In view of the foregoing, an object of the embodiments of the present invention is to provide a self-starting control circuit suitable for an oscillator circuit, and an oscillator for the self-starting oscillator circuit.

According to the embodiment of the invention, the self-starting control circuit suitable for the oscillating circuit comprises a state circuit and a starting circuit. The state circuit generates a reset signal according to a level of a control voltage of a voltage-controlled oscillator of the oscillation circuit. The starting circuit generates an enabling signal according to the reset signal so as to start the voltage-controlled oscillator.

[ description of the drawings ]

Fig. 1A shows a circuit diagram of a self-start control circuit for a frequency-locked loop oscillator circuit according to a first embodiment of the present invention.

FIG. 1B illustrates a timing diagram of signals associated with the self-start control circuit and the PLL circuit.

Fig. 1C illustrates a circuit diagram of the oscillator of fig. 1A.

FIG. 2A is a schematic diagram of the status circuit of FIG. 1A according to an embodiment of the present invention.

FIG. 2B shows a block diagram of the power up circuit of FIG. 1A according to an embodiment of the present invention.

Fig. 3 illustrates a timing diagram of signals associated with an oscillation circuit of a frequency locked loop that does not use a self-start control circuit.

Fig. 4 is a circuit diagram of a self-start control circuit for a pll oscillator according to a second embodiment of the present invention.

[ notation ] to show

100A: self-starting control circuit

100B: self-starting control circuit

11: status circuit

111: comparison circuit

12: starting circuit

121: counter with a memory

122: pulse generator

13: forced switch

200: frequency-locked loop oscillating circuit

21: voltage controlled oscillator

22: comparator with a comparator circuit

400: phase locked loop oscillating circuit

41: frequency divider

42: phase frequency detector

43: charge pump

44: low-pass filter

FBCK: output of oscillation

VCT: control voltage

opp: positive input

opn: negative input

Vdd: supply voltage

R1: a first resistor

R2: second resistor

R3: third resistor

C1: capacitor with a capacitor element

C: capacitor with a capacitor element

SW 1: first switch

SW 2: second switch

SW: switch with a switch body

VC _ RST: reset signal

EN _ VCO: enabling signal

Vref _ H: a first reference voltage

Vref _ L: second reference voltage

t 1-t 5: time of day

out: output signal

ref: reference signal

[ detailed description ] embodiments

Fig. 1A shows a circuit diagram of a self-start control circuit 100A for a Frequency Locked Loop (FLL) oscillator circuit 200 according to a first embodiment of the present invention, and fig. 1B illustrates a timing diagram of signals related to the self-start control circuit 100A and the frequency locked loop oscillator circuit 200.

The frequency-locked loop oscillating circuit 200 may include a voltage-controlled oscillator (VCO)21 for generating an oscillating output FBCK whose oscillation frequency is controlled by a control voltage VCT. The PLL oscillator circuit 200 may include a comparator 22 (e.g., an operational amplifier and a capacitor, connected as shown) that compares a positive input opp (electrically connected to the positive input node "+") with a negative input opn (electrically connected to the negative input node "-") to generate a control voltage VCT. The node of the positive input opp may be electrically connected to the power supply voltage Vdd through a first resistor R1 and to ground through a capacitor C1. The node of the positive input opp may be electrically connected to a capacitor C through a first switch SW1, the capacitor C being electrically grounded through a second switch SW2, wherein the first switch SW1 is connected in series with the second switch SW2 and operated in opposite states (i.e., one switch is on and the other switch is off). The node of the negative input opn is connected to a voltage divider, which is composed of a second resistor R2 and a third resistor R3, connected as shown.

In the present embodiment, the self-start-up control circuit 100A may include a state circuit 11 for determining a level or a state of the control voltage VCT to generate the reset signal VC _ RST. When the control voltage VCT is higher than the preset first reference voltage Vref _ H, the reset signal VC _ RST is in a first state (e.g., high level); when the control voltage VCT is lower than the preset second reference voltage Vref _ L, the reset signal VC _ RST is in a second state (e.g., a low level). FIG. 2A is a schematic diagram of the status circuit 11 of FIG. 1A according to an embodiment of the present invention. In the present embodiment, the status circuit 11 may include a comparison circuit 111 for generating the reset signal VC _ RST by comparing the control voltage VCT with a first reference voltage Vref _ H and a second reference voltage Vref _ L, wherein the first reference voltage Vref _ H is greater than the second reference voltage Vref _ L. As illustrated in fig. 1B, at time t1 or t3, when the control voltage VCT is higher than the preset first reference voltage Vref _ H, the reset signal VC _ RST becomes high (i.e., a first state); at time t2 or t4, when the control voltage VCT is lower than the preset second reference voltage Vref _ L, the reset signal VC _ RST becomes low (i.e., a second state). In one embodiment, as illustrated in FIG. 1B, the comparator circuit 111 may contain hysteresis (hystersis) to prevent unwanted frequent switching.

The self-start control circuit 100A of the present embodiment may include a start circuit 12 for generating an enable signal EN _ VCO according to a reset signal VC _ RST to start the voltage-controlled oscillator 21. FIG. 2B shows a block diagram of the power up circuit 12 of FIG. 1A according to an embodiment of the present invention. In the present embodiment, the start-up circuit 12 may include a counter 121 that stores the number of times a particular state transition (e.g., a transition from a first state to a second state) of the reset signal VC _ RST occurs. As illustrated in fig. 1B, at time t2, counter 121 stores a digital "1" representing a first transition of reset signal VC _ RST from a first state to a second state; at time t4, counter 121 stores a digital "2" representing the second transition of reset signal VC _ RST from the first state to the second state.

In the present embodiment, the start circuit 12 may include a pulse generator 122, and when the number of times of the specific state transition (e.g., the transition from the first state to the second state) of the reset signal VC _ RST is less than or equal to a predetermined count value, the pulse generator 122 generates an enable signal EN _ VCO with a predetermined width. As illustrated in fig. 1B, at time t2 or t4, when the reset signal VC _ RST transitions from the first state to the second state and the number stored by the counter 121 is less than or equal to two (i.e., a predetermined count value), the pulse generator 122 generates the enable signal EN _ VCO.

Fig. 1C illustrates a circuit diagram of the voltage-controlled oscillator 21 of fig. 1A. In the present embodiment, the vco 21 may include a plurality of inverters 211 connected in series and respectively controlled by a current source 212, wherein the current source 212 is controlled by a control voltage VCT. The VCO 21 may include a switch SW including a P-type Metal Oxide Semiconductor (MOS) transistor, a gate controlled by the enable signal EN _ VCO, a source connected to the power voltage Vdd, and a drain connected to an input node of one of the inverters 211 (e.g., the first inverter shown). When the enable signal EN _ VCO goes low, the input node of the inverter 211 connected to the switch SW is pulled high (e.g., Vdd), thereby causing the VCO 21 to oscillate.

The self-start-up control circuit 100A of the present embodiment may further include a force switch 13 for grounding an internal node of the oscillation circuit (in the present embodiment, the frequency-locked loop oscillation circuit 200), thereby lowering the control voltage VCT. In the present embodiment, the force switch 13 may include a Metal Oxide Semiconductor (MOS) transistor (e.g., an N-type MOS transistor) connected between ground and the node of the positive input opp, and the force switch 13 may connect the node of the positive input opp to ground when the reset signal VC _ RST is in a first state (e.g., a high level).

When the self-start control circuit 100A and the frequency-locked loop oscillating circuit 200 are operated, no oscillation occurs until time t 5. When the control voltage VCT is higher than the first reference voltage Vref _ H, the reset signal VC _ RST (during t 1-t 2 or t 3-t 4) goes high, turning on the force switch 13 to forcibly discharge the node of the positive input opp, thereby lowering the control voltage VCT. Therefore, the locking of the voltage-controlled oscillator 21 caused by too high control voltage VCT can be avoided. As illustrated in fig. 1B, after the number stored in the counter 212 reaches two (i.e., the preset count value), the vco 21 starts oscillation at time t5 to output a stable oscillation output FBCK.

Fig. 3 illustrates a timing diagram of signals associated with the frequency-locked loop oscillating circuit 200 without using the self-start control circuit 100A. In this example, the positive input opp and the control voltage VCT remain high, locking the vco 21 and no oscillation occurs. Here, the oscillation output FBCK does not swing any more, so that the first switch SW1 and the second switch SW stop switching. The supply voltage Vdd continues to charge the capacitor C1 through the first resistor R1, further increasing the positive input opp and further aggravating the locking of the vco 21.

Fig. 4 shows a circuit diagram of a self-start control circuit 100B for a Phase Locked Loop (PLL) oscillating circuit 400 according to a second embodiment of the present invention. The pll oscillating circuit 400 may include a voltage-controlled oscillator 21 for generating an output signal out whose oscillating frequency is controlled by a control voltage VCT. The pll oscillator circuit 400 may include a frequency divider 41 for dividing the oscillation frequency of the output signal out to generate the oscillation output FBCK. The PLL oscillating circuit 400 may include a Phase Frequency Detector (PFD)42 for comparing a reference signal ref with an oscillation output FBCK, and feeding the result to a Charge Pump (CP)43, thereby generating a control voltage VCT to the VCO 21. The phase-locked loop oscillation circuit 400 may further include a low-pass filter 44 that passes components of the control voltage VCT that are lower than the cutoff frequency and attenuates components of the control voltage VCT that are higher than the cutoff frequency.

In the present embodiment, the self-start-up control circuit 100B may include a state circuit 11 for determining a level or a state of the control voltage VCT to generate the reset signal VC _ RST. The self-start control circuit 100B of the present embodiment may include a start circuit 12 for generating an enable signal EN _ VCO according to a reset signal VC _ RST to start the voltage-controlled oscillator 21. The self-start-up control circuit 100B of the present embodiment may further include a forced switch 13 (e.g., nmos transistor) for grounding the internal node of the oscillating circuit (in the present embodiment, the pll oscillating circuit 400). In the present embodiment, when the reset signal VC _ RST is in a first state (e.g., high level), the force switch 13 may ground the node of the control voltage VCT. The status circuit 11, the start circuit 12 and the force switch 13 of the self-start control circuit 100B are similar to the corresponding components of the self-start control circuit 100A, and details thereof are not repeated.

In operating the self-start control circuit 100B and the phase-locked loop oscillating circuit 400, when the frequency of the oscillating output FBCK is higher than the frequency of the reference signal ref, the charge pump 43 discharges, thereby lowering the control voltage VCT and the oscillating frequency of the output signal out. When the frequency of the oscillation output FBCK is lower than the frequency of the reference signal ref, the charge pump 43 charges, thereby increasing the oscillation frequencies of the control voltage VCT and the output signal out. When the vco 21 has no oscillation, the charge pump 43 continues to charge to raise the control voltage VCT, which locks the vco 21 and no oscillation occurs. The self-start control circuit 100B can prevent the vco 21 from being locked due to the too high control voltage VCT, and can start the vco 21, which is similar to the self-start control circuit 100A of the previous embodiment, and details thereof are not repeated.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; it is intended that all such equivalent changes and modifications be included within the scope of the following claims without departing from the spirit of the invention as disclosed.

Claims

1. A self-start-up control circuit for an oscillator circuit, the self-start-up control circuit comprising:

a state circuit that generates a reset signal according to a level of a control voltage of a voltage-controlled oscillator of the oscillation circuit; and

and the starting circuit generates an enabling signal according to the reset signal so as to start the voltage-controlled oscillator.

2. The self-start-up control circuit for an oscillator circuit as claimed in claim 1, wherein the reset signal is in a first state when the control voltage is higher than a predetermined first reference voltage, and the reset signal is in a second state when the control voltage is lower than a predetermined second reference voltage, wherein the first reference voltage is greater than the second reference voltage.

3. The self-start-up control circuit for an oscillator circuit as claimed in claim 2, wherein the status circuit comprises a comparison circuit for comparing the control voltage with the first reference voltage and the second reference voltage to generate the reset signal.

4. The self-start-up control circuit for an oscillator circuit of claim 1, wherein the start-up circuit comprises:

a counter that stores the number of times a particular state transition of the reset signal occurs; and

and the pulse generator generates the enabling signal with a preset width when the times stored by the counter is less than or equal to a preset counting value.

5. The self-start control circuit for an oscillator circuit as claimed in claim 1, wherein said voltage controlled oscillator comprises:

a plurality of inverters connected in series; and

and the switch is controlled by the enabling signal and is connected between the power supply voltage and an input node of one of the inverters.

6. The self-start-up control circuit for an oscillator circuit of claim 1, further comprising:

a force switch for grounding an internal node of the oscillation circuit to thereby lower the control voltage.

7. A frequency-locked loop oscillating circuit and a self-starting control circuit are provided, which is characterized in that the frequency-locked loop oscillating circuit and the self-starting control circuit comprise:

a voltage controlled oscillator for generating an oscillating output, the oscillating frequency of which is controlled by a control voltage; and

a comparator comparing a positive input with a negative input to generate the control voltage;

wherein the self-start control circuit comprises:

a state circuit generating a reset signal according to a level of the control voltage; and

8. The PLL oscillator circuit and self-start-up control circuit of claim 7, further comprising:

a first resistor for electrically connecting the node of the positive input to a supply voltage;

a capacitor;

a first switch for electrically connecting the node of the positive input to the capacitor;

a second switch for electrically grounding the capacitor, wherein the first switch is connected in series with the second switch and operated in an opposite state; and

and the voltage divider consists of a second resistor and a third resistor and is used for providing a voltage to the node of the negative input.

9. The PLL oscillator circuit and self-start-up control circuit of claim 7, wherein the reset signal is in a first state when the control voltage is higher than a predetermined first reference voltage, and the reset signal is in a second state when the control voltage is lower than a predetermined second reference voltage, wherein the first reference voltage is higher than the second reference voltage.

10. The PLL circuit of claim 9, wherein the status circuit comprises a comparator circuit configured to compare the control voltage with the first reference voltage and the second reference voltage to generate the reset signal.

11. The PLL oscillator circuit of claim 7, wherein the start-up circuit comprises:

12. The PLL oscillator circuit and self-start-up control circuit of claim 7, wherein the VCO comprises:

a plurality of inverters connected in series; and

13. The PLL oscillator circuit of claim 7, wherein the self-start control circuit further comprises:

a force switch for grounding the node of the positive input, thereby reducing the control voltage.

14. A PLL oscillating circuit and a self-starting control circuit, the PLL oscillating circuit and the self-starting control circuit comprising:

a voltage controlled oscillator for generating an output signal whose oscillation frequency is controlled by a control voltage;

a frequency divider for dividing an oscillation frequency of the output signal to generate an oscillation output;

a phase frequency detector for comparing a reference signal with the oscillating output; and

a charge pump receiving the result of the phase frequency detector to generate the control voltage;

wherein the self-start control circuit comprises:

15. The PLL oscillator circuit and self-start control circuit of claim 14, further comprising:

a low pass filter that passes components lower than a cutoff frequency among the control voltages and attenuates components higher than the cutoff frequency among the control voltages.

16. The PLL oscillator circuit and self-start-up control circuit of claim 14, wherein the reset signal is in a first state when the control voltage is higher than a predetermined first reference voltage and in a second state when the control voltage is lower than a predetermined second reference voltage, wherein the first reference voltage is higher than the second reference voltage.

17. The PLL oscillator circuit and self-start-up control circuit of claim 16, wherein the status circuit comprises a comparator circuit configured to generate the reset signal by comparing the control voltage with the first and second reference voltages.

18. The PLL oscillator circuit of claim 14, wherein the start-up circuit comprises:

19. The PLL oscillator circuit and self-start control circuit of claim 14, wherein the voltage controlled oscillator comprises:

a plurality of inverters connected in series; and

20. The PLL oscillator circuit of claim 14, wherein the self-start control circuit further comprises:

and the forced switch is used for grounding the node of the control voltage.