CN113451360A - Display panel, preparation method of display panel and display device - Google Patents

Display panel, preparation method of display panel and display device Download PDF

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Publication number
CN113451360A
CN113451360A CN202010214621.5A CN202010214621A CN113451360A CN 113451360 A CN113451360 A CN 113451360A CN 202010214621 A CN202010214621 A CN 202010214621A CN 113451360 A CN113451360 A CN 113451360A
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Prior art keywords
substrate
unit
shielding unit
shielding
display panel
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CN202010214621.5A
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CN113451360B (en
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许传志
张露
谢正芳
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

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  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The invention discloses a display panel, a preparation method of the display panel and a display device, wherein the display panel is provided with a first display area and a second display area, and comprises the following components: the semiconductor device comprises a substrate, a first driving transistor, a second driving transistor, a first lead unit, a second lead unit, a first shielding unit and a second shielding unit, wherein the first driving transistor comprises a first grid electrode, and the second driving transistor comprises a second grid electrode; the first lead unit is electrically connected with the first grid electrode, and the second lead unit is electrically connected with the second grid electrode; the orthographic projection of the first shielding unit on the substrate covers the orthographic projection of the first lead unit on the substrate; the orthographic projection of the second shielding unit on the substrate covers the orthographic projection of the second lead unit on the substrate; the first shielding unit and the second shielding unit are both connected to a fixed potential. The display panel provided by the invention enables the display brightness of the first display area and the second display area to be uniform, and improves the display effect of the display panel.

Description

Display panel, preparation method of display panel and display device
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a preparation method of the display panel and a display device.
Background
With the rapid development of electronic devices, the requirements of users on screen occupation ratio are higher and higher, so that the comprehensive screen display of the electronic devices is concerned more and more in the industry.
Conventional electronic devices such as mobile phones, tablet computers, etc. need to integrate components such as front-facing cameras, earphones, infrared sensing elements, etc. In order to increase the light transmittance of the front camera area, for example, in the electronic device in the prior art, the structure of the front camera area is improved, so that the display brightness of the front camera area is different from that of other areas.
Disclosure of Invention
The invention provides a display panel, a preparation method of the display panel and a display device, which are convenient for integrating a camera under a screen, so that the display brightness of a first display area and the display brightness of a second display area are uniform, and the display effect of the display panel is improved.
In one aspect, according to an embodiment of the present invention, there is provided a display panel having a first display area and a second display area, a pixel density of the first display area being smaller than a pixel density of the second display area, the display panel including: a substrate; the first driving transistor and the second driving transistor are positioned on the substrate, the first driving transistor is positioned in the first display area and comprises a first grid electrode, and the second driving transistor is positioned in the second display area and comprises a second grid electrode; the first lead unit is electrically connected with the first grid and is positioned on one side of the first grid, which is far away from the substrate, and the second lead unit is electrically connected with the second grid and is positioned on one side of the second grid, which is far away from the substrate; the first shielding unit is positioned on one side of the first lead unit, which is far away from the substrate, and the orthographic projection of the first shielding unit on the substrate covers the orthographic projection of the first lead unit on the substrate; the second shielding unit is positioned on one side of the second lead unit, which is far away from the substrate, and the orthographic projection of the second shielding unit on the substrate covers the orthographic projection of the second lead unit on the substrate; the first shielding unit and the second shielding unit are both connected to a fixed potential.
According to an aspect of the embodiment of the invention, the first wire unit and the second wire unit are respectively connected to the reset signal terminal.
According to an aspect of the embodiments of the present invention, the plurality of first shielding units are arranged in a plurality of first shielding unit rows, and the first shielding units in each of the first shielding unit rows are arranged along a first direction and are electrically connected to each other; optionally, the plurality of second shielding units are arranged in a plurality of second shielding unit rows, and the second shielding units in each second shielding unit row are arranged along the first direction and are mutually communicated; optionally, the plurality of second shielding units are arranged in a plurality of second shielding unit rows, each second shielding unit in each second shielding unit row is arranged along the first direction and is conducted with each other, the plurality of second shielding unit rows are arranged along the second direction and are conducted with each other to form a mesh structure, and the first direction intersects with the second direction; optionally, the first shielding unit row and the second shielding unit row corresponding to the first direction position are electrically connected to each other.
According to an aspect of an embodiment of the present invention, the display panel further includes: the first light-emitting elements are positioned in the first display area and on one side, away from the substrate, of the first driving transistor, each first light-emitting element comprises a first electrode, a first light-emitting layer positioned on the first electrode and a second electrode positioned on the first light-emitting layer, the orthographic projection of at least part of the first electrodes on the substrate and the orthographic projection of the first wire units on the substrate are overlapped to form a first projection pattern, and the orthographic projection of the first shielding units on the substrate covers the first projection pattern; the second light-emitting elements are positioned in the second display area and on one side, away from the substrate, of the second driving transistor and comprise third electrodes, second light-emitting layers positioned on the third electrodes and fourth electrodes positioned on the second light-emitting layers, orthographic projections of at least part of the third electrodes on the substrate and orthographic projections of the second wire units on the substrate are overlapped to form second projection patterns, the second projection patterns are different from the first projection patterns, and orthographic projections of the second shielding units on the substrate cover the second projection patterns.
According to an aspect of an embodiment of the present invention, the display panel further includes: the first planarization layer is positioned between the first wire unit and the first shielding unit and between the second wire unit and the second shielding unit; and the second planarization layer is positioned between the first shielding unit and the first electrode and between the second shielding unit and the third electrode.
According to an aspect of an embodiment of the present invention, the first planarization layer includes a first opening at the first display region and a second opening at the second display region, and the display panel further includes: the power supply line is located on one side, away from the first shielding unit, of the first planarization layer and on one side, away from the second shielding unit, of the first planarization layer respectively, the power supply line is used for supplying power to the first light-emitting element and the second light-emitting element, the first shielding unit is electrically connected with the power supply line through the first opening, and the second shielding unit is electrically connected with the power supply line through the second opening.
According to an aspect of an embodiment of the present invention, the display panel further includes: the third shielding unit is positioned in the first display area and between the first grid and the first wire unit, and the orthographic projection of the third shielding unit on the substrate and the orthographic projection of the first shielding unit on the substrate are overlapped to cover the orthographic projection of the first grid on the substrate; the fourth shielding unit is positioned in the second display area and between the second grid and the second wire unit, and the orthographic projection of the fourth shielding unit on the substrate and the orthographic projection of the second shielding unit on the substrate are overlapped to cover the orthographic projection of the second grid on the substrate; optionally, the first shielding unit comprises a transparent conductive material, and the second shielding unit comprises a conductive material; optionally, the first shielding unit comprises indium tin oxide, and the second shielding unit comprises indium tin oxide; optionally, the first shielding unit and the second shielding unit are connected to one of the anode power supply line or the cathode power supply line.
On the other hand, an embodiment of the present invention further provides a method for manufacturing a display panel, where the display panel has a first display area and a second display area, and a pixel density of the first display area is less than a pixel density of the second display area, and the method for manufacturing the display panel includes: forming a first driving transistor and a second driving transistor on a substrate, wherein the first driving transistor is positioned in a first display area and comprises a first grid electrode, and the second driving transistor is positioned in a second display area and comprises a second grid electrode; forming a first lead unit on one side of the first grid electrode, which is far away from the substrate, and forming a second lead unit on one side of the second grid electrode, which is far away from the substrate; forming a first shielding unit on one side of the first lead unit, which is far away from the substrate, wherein the orthographic projection of the first shielding unit on the substrate covers the orthographic projection of the first lead unit on the substrate; and a second shielding unit is formed on one side of the second lead unit, which is far away from the substrate, and the orthographic projection of the second shielding unit on the substrate covers the orthographic projection of the second lead unit on the substrate, wherein the first shielding unit and the second shielding unit are both connected to a fixed potential.
According to an aspect of the embodiments of the present invention, after forming the first wire unit on a side of the first gate electrode facing away from the substrate and forming the second wire unit on a side of the second gate electrode facing away from the substrate, the method for manufacturing a display panel further includes: forming a first planarization layer on one side of the first lead unit and one side of the second lead unit, which are far away from the substrate; optionally, after forming the first shielding unit on a side of the first wire unit away from the substrate and forming the second shielding unit on a side of the second wire unit away from the substrate, the method for manufacturing a display panel further includes: forming a second planarization layer on the first shielding unit and one side of the second shielding unit, which is far away from the substrate; optionally, the first shielding unit and the second shielding unit are both connected to a fixed potential, and the first shielding unit and the second shielding unit are connected to one of the anode power supply line and the cathode power supply line.
In another aspect, an embodiment of the present invention further provides a display device, including the display panel according to any one of the above embodiments, or a display panel manufactured by the method for manufacturing a display panel according to any one of the above embodiments.
According to the display panel, the preparation method of the display panel and the display device provided by the embodiment of the invention, the display panel is provided with the first display area with lower pixel density and the second display area with higher pixel density, so that the light transmittance of the first display area is higher than that of the second display area, and the back surface of the display panel can be integrated with the photosensitive assembly, and the under-screen integration of the photosensitive assembly such as a camera is realized. Further, the display panel includes a substrate, a first driving transistor and a second driving transistor, a first wire unit and a second wire unit, and a first shielding unit and a second shielding unit, wherein the first wire unit is electrically connected to the first gate so as to electrically connect an electrical signal terminal, such as an initialization signal terminal, to the first gate, and the second wire unit is electrically connected to the second gate so as to electrically connect an electrical signal terminal, such as an initialization signal terminal, to the second gate, so as to initialize the first gate and the second gate.
The orthographic projection of the first shielding unit on the substrate is covered, the orthographic projection of the first wire unit on the substrate is covered, the first shielding unit is connected to the fixed potential, parasitic capacitance generated by coupling between the conductive film layer structure manufactured in the later stage of the first shielding unit and the first wire unit can be prevented, and uniformity of display of each pixel in the first display area is facilitated. Simultaneously, cover the orthographic projection of second wire unit on the substrate and second shielding unit is connected to fixed potential through setting up the orthographic projection of second shielding unit on the substrate, can prevent to produce parasitic capacitance between the electrically conductive membranous layer structure of second shielding unit post manufacture and second wire unit, is convenient for realize the homogeneity that each pixel shows in the second display area. And because first display area and second display area all are provided with shielding element, can make the display luminance uniformity in first display area and second display area, improve display panel's display effect.
Drawings
Other features, objects and advantages of the invention will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
FIG. 1 is a top view of a display panel provided in accordance with one embodiment of the present invention;
FIG. 2 is a cross-sectional view taken in the direction N-N of FIG. 1;
FIG. 3 is an enlarged view of the area Q1 in FIG. 1;
fig. 4 is a top view of a first active layer and a second active layer provided in one embodiment of the present invention;
FIG. 5 is a top view of a first conductive layer provided in accordance with one embodiment of the present invention;
FIG. 6 is a top view of a second conductive layer provided in accordance with one embodiment of the present invention;
FIG. 7 is a top view of a third conductive layer provided in accordance with one embodiment of the present invention;
FIG. 8 is a top view of a display panel according to another embodiment of the present invention;
FIG. 9 is a top view of a display panel according to yet another embodiment of the present invention;
FIG. 10 is an enlarged view of the area Q2 in FIG. 8;
FIG. 11 is a cross-sectional view taken along line B-B of FIG. 10;
FIG. 12 is a cross-sectional view taken along the line C-C of FIG. 10;
FIG. 13 is a cross-sectional view taken along line D-D of FIG. 10;
FIG. 14 is a top view of a display panel according to yet another embodiment of the present invention;
FIG. 15 is an enlarged view of the area Q3 in FIG. 14;
FIG. 16 is a cross-sectional view taken along the line E-E in FIG. 15;
fig. 17 is a schematic flow chart of a method for manufacturing a display panel according to an embodiment of the present invention;
fig. 18 is a schematic flow chart of a method for manufacturing a display panel according to another embodiment of the present invention.
In the figure:
100-a display panel; AA 1-first display area; AA 2-second display area; TG-light transmissive display region; TA-transition display area; x-a first direction; y-a second direction; m1 — first conductive layer; m2 — second conductive layer; m3 — third conductive layer;
10-a substrate;
20-a device layer;
21 a-a first drive transistor; 211 a-first gate; 212 a-first active layer; 22 a-a first wire unit; 23 a-a first shielding element; 24 a-a third shielding element;
21 b-a second drive transistor; 211 b-second gate; 212 b-a second active layer; 22 b-a second wire unit; 23 b-a second shielding element; 24 b-a fourth shielding element;
25-a first dielectric layer; 26-a second dielectric layer; 27-a first planarizing layer; 28-a second planarizing layer;
30 a-a first light emitting element; 31 a-a first electrode; 32 a-a first light-emitting layer; 33 a-a second electrode;
30 b-a second light emitting element; 31 b-a third electrode; 32 b-a second light emitting layer; 33 b-a fourth electrode;
40-pixel definition layer;
50-a power supply line; 51-cathode supply line; 52-anode supply line;
60-reset signal terminal.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
Features and exemplary embodiments of various aspects of the present invention will be described in detail below. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
On electronic devices such as mobile phones and tablet computers, it is necessary to integrate a photosensitive component such as a front camera, an infrared light sensor, a proximity light sensor, and the like on the side where the display panel is provided. In some embodiments, a transparent display area may be disposed on the electronic device, and the photosensitive component is disposed on the back of the transparent display area, so that full-screen display of the electronic device is achieved under the condition that the photosensitive component is ensured to work normally.
In order to improve the light transmittance of the transparent display region, it is common to set the pixel density of the transparent display region to be small and reduce the number of wirings of the transparent display region. In order to reduce the number of wirings in the transparent display region, a pixel driving circuit of the transparent display region is usually disposed at the periphery of the transparent display region or anodes of a plurality of same-color sub-pixels of the transparent display region are connected, and one pixel driving circuit is used to drive the plurality of same-color sub-pixels to perform light-emitting display. However, as the pixel structure or the wiring position of the transparent display area is changed, a parasitic capacitance is generated by coupling between the anode of the sub-pixel of one color and the pixel driving circuit of the sub-pixel of another color, for example, the gate of the driving transistor, and then crosstalk is generated between the light emitting brightness of the sub-pixels of different colors. Therefore, in order to prevent crosstalk between the light emitting luminance of different sub-pixels between the transparent display regions, a shielding layer is disposed between the gate of the driving transistor and the anode of the sub-pixel to prevent coupling between the anode of each sub-pixel and the gate of the driving transistor.
However, the pixel density of the transparent display area is different from that of the conventional display area, so that the coupling degree of the pixel anode of the transparent display area and the pixel anode of the conventional display area to the gate of the driving transistor is different, and the problem of difference in brightness between the transparent display area and the conventional display area exists.
In order to solve the above problem, embodiments of the present invention provide a display panel 100, a method for manufacturing the display panel, and a display device. The display panel 100, the method for manufacturing the display panel, and the display device according to the embodiment of the invention are described in detail below with reference to fig. 1 to 18.
An embodiment of the invention provides a display panel 100, and the display panel 100 may be an Organic Light Emitting Diode (OLED) display panel 100.
Referring to fig. 1 to 7 together, fig. 1 illustrates a top view of a display panel according to an embodiment of the present invention, fig. 2 illustrates a top view of the N-N direction in fig. 1, fig. 3 illustrates an enlarged view of a region Q1 in fig. 1, fig. 4 illustrates a top view of a first active layer and a second active layer according to an embodiment of the present invention, fig. 5 illustrates a top view of a first conductive layer according to an embodiment of the present invention, fig. 6 illustrates a top view of a second conductive layer according to an embodiment of the present invention, and fig. 7 illustrates a top view of a third conductive layer according to an embodiment of the present invention. In the drawings, the filling lines with the same color are used for indicating that the film layer structures are manufactured in the same layer, and the specific structures of all the film layers are schematic, so that the film can be improved by a person skilled in the art according to the requirements.
The embodiment of the invention provides a display panel 100, the display panel 100 has a first display area AA1, a second display area AA2, and a non-display area surrounding the first display area AA1 and the second display area AA2, and the pixel density of the first display area AA1 is less than the pixel density of the second display area AA 2.
The display panel 100 includes a substrate 10 and a device layer 20 on the substrate 10, the device layer 20 including first and second driving transistors 21a and 21b on the substrate 10, first and second wire units 22a and 22b, a first shielding unit 23a, and a second shielding unit 23 b.
The first driving transistor 21a is disposed in the first display area AA1 and includes a first gate 211a, and the second driving transistor 21b is disposed in the second display area AA2 and includes a second gate 211 b. The first wire unit 22a is electrically connected to the first gate 211a and located on a side of the first gate 211a facing away from the substrate 10, and the second wire unit 22b is electrically connected to the second gate 211b and located on a side of the second gate 211b facing away from the substrate 10. The first shielding element 23a is located on a side of the first conductor element 22a facing away from the substrate 10, and an orthographic projection of the first shielding element 23a on the substrate 10 covers an orthographic projection of the first conductor element 22a on the substrate 10. The second shielding unit 23b is located on a side of the second lead unit 22b facing away from the substrate 10, and an orthographic projection of the second shielding unit 23b on the substrate 10 covers an orthographic projection of the second lead unit 22b on the substrate 10; the first shielding unit 23a and the second shielding unit 23b are both connected to a fixed potential.
In some embodiments, in a manufacturing process of the display panel 100, a 3-layer Metal (3Metal) process may be used such that the display panel 100 includes a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 sequentially disposed in a direction away from the substrate 10. Wherein the first gate 211a and the second gate 211b are formed in the first conductive layer M1, one substrate of the capacitor may be formed in the second conductive layer M2, and the first wire unit 22a and the second wire unit 22b are formed in the third conductive layer M3. And an insulating medium layer is arranged between the conducting layers to prevent short circuit between the conducting layers.
According to the display panel 100 provided by the embodiment of the invention, by setting the orthographic projection of the first shielding unit 23a on the substrate 10 to cover the orthographic projection of the first conducting wire unit 22a on the substrate 10 and connecting the first shielding unit 23a to the fixed potential, the fixed potential provides a stable electric signal, so that the first shielding unit 23a can stabilize the potential of the first conducting wire unit 22a, prevent the potential of the first conducting wire unit 22a and the first grid 211a from changing due to parasitic capacitance generated by coupling between the conducting film layer structure manufactured at the later stage of the first shielding unit 23a and the first conducting wire unit 22a, and facilitate the uniformity of the display of each pixel in the first display area AA 1. Meanwhile, by setting the orthographic projection of the second shielding element 23b on the substrate 10 to cover the orthographic projection of the second wire element 22b on the substrate 10 and connecting the second shielding element 23b to a fixed potential, the second shielding element 23b can stabilize the potential of the second wire element 22b, and can prevent the potential of the second wire element 22b and the second gate 211b from changing due to the parasitic capacitance generated between the conductive film layer structure manufactured at the later stage of the second shielding element 23b and the second wire element 22b, so that the uniformity of the display of each pixel in the second display area AA2 can be realized. In addition, since the shielding units are disposed in the first display area AA1 and the second display area AA2, the display brightness of the first display area AA1 and the display brightness of the second display area AA2 can be uniform, and the display effect of the display panel 100 can be improved.
The first driving transistor 21a further includes a first active layer 212a, the first gate electrode 211a is located on a side of the first active layer 212a facing away from the substrate 10, the second driving transistor 21b further includes a second active layer 212b, and the second gate electrode 211b is located on a side of the second active layer 212b facing away from the substrate 10. The first active layer 212a and the second active layer 212b may be fabricated in the same layer, and the specific structures of the first driving transistor 21a and the second driving transistor 21b are not limited in the present invention.
Referring to fig. 8, fig. 8 is a top view of a display panel according to another embodiment of the invention. In order to make each pixel on the display panel 100 display better, the gate of the driving transistor needs to be initialized, and in some embodiments, the display panel further includes a reset signal terminal 60, the first wire unit 22a and the second wire unit 22b are respectively connected to the reset signal terminal 60, and the reset signal terminal 60 can provide a fixed voltage. Optionally, the display panel further includes a reset circuit, and the reset circuit is electrically connected to the first wire unit 22a and the second wire unit 22b, respectively. When the first gate 211a needs to be initialized, the reset circuit sends a reset voltage signal to the first gate 211a through the first conductive line unit 22a under the voltage control of the reset signal terminal 60 to initialize the first gate 211a, so as to prevent the display panel 100 from generating short-term afterimage or poor display such as brightness difference. Similarly, when the second gate 211b needs to be initialized, the reset circuit sends the reset voltage signal to the second gate 211b through the second conductive line unit 22b under the control of the voltage of the reset signal terminal 60 to initialize the second gate 211b, so as to prevent the display panel 100 from generating the display defects such as short-term image sticking.
Referring to fig. 8 and 9, fig. 9 is a top view of a display panel according to still another embodiment of the invention. In some embodiments, the plurality of first shielding units 23a are arranged in a plurality of first shielding unit rows, and the first shielding units 23a in each first shielding unit row are arranged along the first direction X and are in conduction with each other. With the above arrangement, the plurality of first shielding units 23a are electrically connected to each other so that the shielding effect of the first shielding units 23a to the first wire unit 22a is uniform, the display uniformity of the first display area AA1 is improved, and at the same time, the first shielding unit rows can be integrally connected to a fixed potential, which can simplify the process compared to connecting each of the first shielding units 23a to a fixed potential. Further, by electrically connecting the plurality of first shielding units 23a to the plurality of first shielding unit rows, it can be effectively prevented that the plurality of first shielding units 23a electrically connect other film layer structures disposed on the same layer, which may cause a short circuit of the other film layer structures or affect the display of the display panel 100.
In a specific implementation, the first display area AA1 may include a transparent display area TG and a transition display area TA disposed between the transparent display area TG and the second display area AA2, and the first driving transistor 21a and the first shielding unit 23a are located in the transition display area TA.
In order to further improve the display uniformity of the second display area AA2, the plurality of second shielding units 23b are arranged in a plurality of second shielding unit rows, and the second shielding units 23b in each second shielding unit row are arranged along the first direction X and are in conduction with each other; or, when the plurality of second shielding units 23b are arranged in a plurality of second shielding unit rows, and the second shielding units 23b in each second shielding unit row are arranged along the first direction X and are conducted with each other, the plurality of second shielding unit rows are arranged along the second direction Y and are conducted with each other to form a mesh structure, and the first direction X intersects with the second direction Y. Alternatively, the first direction X may be a row direction of the display panel 100, and the second direction Y may be a column direction of the display panel 100. Through the above arrangement, the second shielding units 23b in the second display area AA2 are electrically connected to each other, so that the shielding effects of the second shielding units 23b on the second wire units 22b are consistent, and the uniformity of the display brightness of the sub-pixels in the second display area AA2 is improved. At this time, the second shielding unit row or the mesh structure may be electrically connected to a fixed potential as a whole, and the process can be simplified compared to connecting each of the second shielding units 23b to a fixed potential.
In order to make the display luminance of the first and second display areas AA1 and AA2 uniform, the first and second shielding cell rows corresponding to the first and second positions X in the first direction are electrically connected to each other when the white screen is switched to the monochrome screen or the monochrome screen is switched to the white screen.
Referring further to fig. 3, 10 to 13, fig. 10 shows an enlarged view of a region Q2 in fig. 8, fig. 11 shows a sectional view taken along a direction B-B in fig. 10, fig. 12 shows a sectional view taken along a direction C-C in fig. 10, and fig. 13 shows a sectional view taken along a direction D-D in fig. 10.
In order to realize the display of the display panel 100, in some embodiments, the display panel 100 further includes a plurality of first light emitting elements 30a, the plurality of first light emitting elements 30a are located in the first display area AA1 and located on a side of the first driving transistor 21a facing away from the substrate 10, the first light emitting elements 30a include a first electrode 31a, a first light emitting layer 32a located on the first electrode 31a, and a second electrode 33a located on the first light emitting layer 32a, an orthographic projection of at least a portion of the first electrode 31a on the substrate 10 overlaps an orthographic projection of the first wire unit 22a on the substrate 10 to form a first projection pattern, and the orthographic projection of the first shielding unit 23a on the substrate 10 covers the first projection pattern. When the orthographic projection of the first electrode 31a on the substrate 10 overlaps with the orthographic projection of the first lead unit 22a on the substrate 10, at least part of the first electrode 31a and the first lead unit 22a have no other conductive film layer structure, so that parasitic capacitance is generated by coupling between the first electrode 31a and the first lead unit 22a, and the first shielding unit 23a is orthographically projected on the substrate 10 to cover the first projection pattern, so that the coupling between the first electrode 31a and the first lead unit 22a can be effectively prevented, the voltage of the first gate 211a electrically connected with the first lead unit 22a is prevented from being changed, and the influence on the brightness of each first light-emitting element 30a is prevented. One of the first electrode 31a and the second electrode 33a is an anode, and the other is a cathode. The first electrode 31a is used as an anode and the second electrode 33a is used as a cathode. It is understood that the display panel 100 further includes a pixel defining layer 40, the pixel defining layer 40 includes a first pixel opening, and the first light emitting layer 32a is filled into the first pixel opening.
In a specific implementation, when the first display area AA1 includes a transparent display area TG and a transition display area TA disposed between the transparent display area TG and the second display area AA2, a plurality of first light emitting elements 30a may be disposed in the transparent display area TG, and a pixel driving circuit for driving the first light emitting elements 30a to emit light for display may be disposed in the transition display area TA to increase the light transmittance of the transparent display area TG.
In some embodiments, the display panel 100 further includes a plurality of second light emitting elements 30b, the plurality of second light emitting elements 30b are located in the second display area AA2 and located on a side of the second driving transistor 21b facing away from the substrate 10, the second light emitting elements 30b include a third electrode 31b, a second light emitting layer 32b located on the third electrode 31b, and a fourth electrode 33b located on the second light emitting layer 32b, an orthogonal projection of at least a portion of the third electrode 31b on the substrate 10 overlaps an orthogonal projection of the second wire unit 22b on the substrate 10 to form a second projection pattern, no other conductive film layer structure is located between at least a portion of the third electrode 31b and the second wire unit 22b, the second projection pattern is different from the first projection pattern, and the orthogonal projection of the second shielding unit 23b on the substrate 10 covers the second projection pattern. One of the third electrode 31b and the fourth electrode 33b is an anode, and the other is a cathode. The third electrode 31b is an anode and the fourth electrode 33b is a cathode. It is understood that the display panel 100 further includes a pixel defining layer 40, the pixel defining layer 40 includes a second pixel opening, and the second light emitting layer 32b is filled into the second pixel opening.
When the orthographic projection of the third electrode 31b on the substrate 10 overlaps with the orthographic projection of the second lead unit 22b on the substrate 10, the third electrode 31b is coupled with the second lead unit 22b to generate a parasitic capacitance, and the second shielding unit 23b is orthographically projected on the substrate 10 to cover the second projection pattern, so that the coupling between the third electrode 31b and the second lead unit 22b can be effectively prevented, the voltage of the second gate 211b electrically connected with the second lead unit 22b is prevented from being changed, and the influence on the brightness of each second light-emitting element 30b is prevented.
Meanwhile, since the second projection pattern is different from the first projection pattern, the coupling condition of the third electrode 31b of the second light emitting element 30b to the second wire unit 22b is different from the coupling condition of the first electrode 31a of the first light emitting element 30a to the first wire unit 22a, so that when the white image is displayed in the second display area AA2 and the first display area AA1, an optimal Gamma (Gamma) parameter needs to be adjusted to keep the brightness of the two display areas consistent, but when the white image is switched to a monochrome image, the display brightness of the first display area AA1 and the second display area AA2 will be different. In order to solve the above problem, the embodiment of the invention orthographically projects the second shielding unit 23b on the substrate 10 to cover the second projection pattern, and orthographically projects the first shielding unit 23a on the substrate 10 to cover the first projection pattern, so that the first electrode 31a of the first display area AA1 is not coupled to the first gate 211a and thus does not cause a change in voltage of the first gate 211a, and the third electrode 31b is not coupled to the second gate 211b and thus does not cause a change in voltage of the second gate 211b, thereby achieving uniform brightness of the two display areas.
In some embodiments, in order to improve the light transmittance of the first display area AA1, the first electrode 31a is a light-transmissive electrode, and optionally, the first electrode 31a includes an Indium Tin Oxide (ITO) layer or an Indium zinc Oxide (izo) layer.
In some embodiments, the first electrode 31a is a reflective electrode and an area of an orthographic projection of the first electrode 31a on the substrate 10 is smaller than an area of an orthographic projection of the third electrode 31b on the substrate 1010, and the first electrode 31a may include a first light-transmissive conductive layer, a reflective layer on the first light-transmissive conductive layer, and a second light-transmissive conductive layer on the reflective layer. The first and second transparent conductive layers may be ITO, indium zinc oxide, etc., and the reflective layer may be a metal layer, such as made of silver. The third electrode 31b may include the same film structure as the first electrode 31 a.
In some embodiments, the constituent material of the second electrode 33a includes magnesium, silver, or a magnesium-silver alloy. The fourth electrode 33b may be formed of the same material as the second electrode 33 a. In some embodiments, the second and fourth electrodes 33a, 33b may be interconnected as a common electrode.
In some embodiments, the orthographic projection of each first light-emitting layer 32a on the substrate 10 is composed of one first graphic element or is composed of a concatenation of more than two first graphic elements, the first graphic elements including at least one selected from the group consisting of a circle, an ellipse, a dumbbell, a gourd, a rectangle.
In some embodiments, the orthographic projection of each first electrode 31a on the substrate 10 is composed of one second pattern unit or is composed of a concatenation of two or more second pattern units, the second pattern unit including at least one selected from the group consisting of a circle, an ellipse, a dumbbell, a gourd, and a rectangle. With the above arrangement, diffraction of the first display area AA1 can be effectively reduced.
Referring to fig. 11 to 12, in some embodiments, the display panel 100 further includes a first planarization layer 27 and a second planarization layer 28, the first planarization layer 27 is located between the first conductive line unit 22a and the first shielding unit 23a, and between the second conductive line unit 22b and the second shielding unit 23b, the second planarization layer 28 is located between the first shielding unit 23a and the first electrode 31a, and between the second shielding unit 23b and the third electrode 31 b. Through the arrangement, on one hand, the insulation performance of the display panel 100 can be improved, on the other hand, a flat surface can be provided for manufacturing the light-emitting element, the poor connection condition of the light-emitting element is prevented, and the quality of the film layer structure of the light-emitting element of the display panel 100 is improved.
Referring further to fig. 14 to 16, fig. 14 is a plan view of a display panel according to still another embodiment of the present invention, fig. 15 is an enlarged view of a region Q3 in fig. 14, and fig. 16 is a cross-sectional view taken along a direction E-E in fig. 15. In some embodiments, the first planarization layer 27 includes a first opening located in the first display area AA1 and a second opening located in the second display area AA2, the display panel 100 further includes a power supply line 50, the power supply line 50 is respectively located on a side of the first planarization layer 27 facing away from the first shielding unit 23a and a side of the first planarization layer 27 facing away from the second shielding unit 23b, the power supply line 50 is used for supplying power to the first light emitting element 30a and the second light emitting element 30b, the first shielding unit 23a is electrically connected with the power supply line through the first opening, the second shielding unit 23b is electrically connected with the power supply line through the second opening, and optionally, the power supply line 50 includes an anode power supply line (VDD) 52. Through the arrangement, the first shielding unit 23a and the second shielding unit 23b are stably connected to a fixed potential end such as the anode power supply line 52 through the via hole, so that the first shielding unit 23a and the second shielding unit 23b have a good shielding effect.
In practical implementation, each of the first light emitting elements 30a is correspondingly connected to the anode supply line 52, and when the first electrode 31a is an anode, the anode supply line 52 is electrically connected to the first electrode 31a to supply power to the first electrode 31 a. By connecting the first shielding unit 23a to the anode supply line 52 through the via hole such that there is no coupling between the single first light emitting element 30a and the first gate electrode 211a, each second light emitting element 30b is correspondingly connected to the anode supply line 52, and when the second electrode 31b is an anode, the anode supply line 52 is electrically connected to the second electrode 31b to supply power to the second electrode 31 b. By connecting the second shielding units 23b to the anode supply lines 52 through the via holes, no coupling is generated between the single second light emitting elements 30b and the second grid 211b, and since the anode supply lines 52 of the plurality of first light emitting elements 30a are electrically connected to each other and the anode supply lines 52 of the plurality of second light emitting elements 30b are electrically connected to each other, the shielding effect of each first grid 211a and each second grid 211b is further achieved, at this time, the plurality of first shielding units 23a may be in an independent relationship with each other as shown in fig. 15, optionally, the plurality of first shielding units 23a may be in conduction with each other, and similarly, the plurality of second shielding units 23b may be in conduction with each other or in no connection relationship with each other.
In some embodiments, the power supply line 50 may further include a cathode power supply line (VSS)51, and referring to fig. 8, the plurality of first shielding units 23a and the plurality of second shielding units 23b may also be conductively connected to the cathode power supply line 51, so as to achieve a better shielding effect. In practical implementation, when the second electrode 33a and the fourth electrode 33b are cathodes, the second electrode 33a and the fourth electrode 33b are electrically connected to the cathode supply lines 51, respectively, to supply power to the cathodes.
Referring to fig. 2 to 12, in some embodiments, the display panel 100 further includes a third shielding unit 24a and a fourth shielding unit 24b, the third shielding unit 24a is located in the first display area AA1 and located between the first gate 211a and the first wire unit 22a, and an orthographic projection of the third shielding unit 24a on the substrate 10 and an orthographic projection of the first shielding unit 23a on the substrate 10 are overlapped to cover an orthographic projection of the first gate 211a on the substrate 10. The fourth shielding unit 24b is located in the second display area AA2 and between the second gate electrode 211b and the second wire unit 22b, and an orthographic projection of the fourth shielding unit 24b on the substrate 10 overlaps an orthographic projection of the second shielding unit 23b on the substrate 10 to cover the second gate electrode 211b on the substrate 10. With the above arrangement, the first gate 211a and the second gate 211b are better shielded and can be free from the coupling effect of the film structure of the light emitting element, such as the anode to the first gate 211a and the second gate 211 b.
Alternatively, the third shielding element 24a and the fourth shielding element 24b may be fabricated on the second conductive layer M2, the third shielding element 24a may be reused as one of the plates of the capacitor or other conducting structure, and the fourth shielding element 24b may also be reused as one of the plates of the capacitor or other conducting structure, as defined herein.
In some embodiments, the constituent material of the first shielding unit 23a includes a transparent conductive material, and the constituent material of the second shielding unit 23b includes a conductive material; alternatively, the first shielding unit 23a may include indium tin oxide, and the second shielding unit 23b may include indium tin oxide. Through the reasonable constitution material that sets up first shielding element 23a and second shielding element 23b, can reduce the influence to first display area AA 1's luminousness, can also play good shielding effect simultaneously.
In order to make the display panel 100 display well, in some embodiments, the display panel 100 further includes a first dielectric layer 25 and a second dielectric layer 26, the first dielectric layer 25 is located between the first active layer 212a and the first gate 211a and between the second active layer 212b and the second gate 211b, and the second dielectric layer 26 is located between the first gate 211a and the third shielding unit 24a and between the second gate 211b and the fourth shielding unit 24 b. Through the arrangement, good insulation effect can be achieved between the film layers, and short circuit is prevented.
In summary, according to the display panel 100 provided by the embodiment of the invention, the display panel 100 has the first display area AA1 with a smaller pixel density and the second display area AA2 with a larger pixel density, so that the light transmittance of the first display area AA1 is greater than that of the second display area AA2, and therefore, the back surface of the display panel 100 can be integrated with the photosensitive component, and the under-screen integration of the photosensitive component such as a camera is realized. Further, the display panel 100 includes a substrate 10, a first driving transistor 21a and a second driving transistor 21b, a first wire unit 22a and a second wire unit 22b, and a first shielding unit 23a and a second shielding unit 23b, wherein the first wire unit 22a is electrically connected to the first gate electrode 211a so as to electrically connect an electrical signal terminal, e.g., an initialization signal terminal, to the first gate electrode 211a, and the second wire unit 22b is electrically connected to the second gate electrode 211b so as to electrically connect an electrical signal terminal, e.g., an initialization signal terminal, to the second gate electrode 211b so as to initialize the first gate electrode 211a and the second gate electrode 211 b.
By setting the orthographic projection of the first shielding element 23a on the substrate 10 to cover the orthographic projection of the first lead element 22a on the substrate 10 and connecting the first shielding element 23a to a fixed potential, parasitic capacitance generated by coupling between a conductive film structure manufactured at the later stage of the first shielding element 23a and the first lead element 22a can be prevented, and uniformity of display of each pixel in the first display area AA1 can be realized. Meanwhile, by setting the orthographic projection of the second shielding element 23b on the substrate 10 to cover the orthographic projection of the second conducting wire element 22b on the substrate 10 and connecting the second shielding element 23b to a fixed potential, parasitic capacitance generated between a conducting film layer structure manufactured at the later stage of the second shielding element 23b and the second conducting wire element 22b can be prevented, and uniformity of display of each pixel in the second display area AA2 can be realized conveniently. In addition, since the shielding units are disposed in the first display area AA1 and the second display area AA2, the display brightness of the first display area AA1 and the display brightness of the second display area AA2 can be uniform, and the display effect of the display panel 100 can be improved.
Referring to fig. 17 and 18, fig. 17 is a schematic flow chart illustrating a method for manufacturing a display panel according to an embodiment of the present invention, and fig. 18 is a schematic flow chart illustrating a method for manufacturing a display panel according to another embodiment of the present invention. On the other hand, the embodiment of the present invention further provides a method for manufacturing a display panel, where the display panel 100 has a first display area AA1 and a second display area AA2, and the pixel density of the first display area AA1 is less than the pixel density of the second display area AA2, and the method for manufacturing the display panel includes:
s110, forming a first driving transistor 21a and a second driving transistor 21b on the substrate 10, wherein the first driving transistor 21a is located in the first display area AA1 and includes a first gate 211a, and the second driving transistor 21b is located in the second display area AA2 and includes a second gate 211 b.
S120, forming a first wire unit 22a on a side of the first gate 211a facing away from the substrate 10, and forming a second wire unit 22b on a side of the second gate 211b facing away from the substrate 10.
S130, a first shielding unit 23a is formed on a side of the first wire unit 22a away from the substrate 10, and an orthographic projection of the first shielding unit 23a on the substrate 10 covers an orthographic projection of the first wire unit 22a on the substrate 10.
S140, a second shielding unit 23b is formed on a side of the second wire unit 22b away from the substrate 10, an orthographic projection of the second shielding unit 23b on the substrate 10 covers an orthographic projection of the second wire unit 22b on the substrate 10, wherein the first shielding unit 23a and the second shielding unit 23b are both connected to a fixed potential.
According to the preparation method of the display panel provided by the embodiment of the invention, the orthographic projection of the first shielding unit 23a on the substrate 10 is arranged to cover the orthographic projection of the first lead unit 22a on the substrate 10, and the first shielding unit 23a is connected to a fixed potential, so that parasitic capacitance generated by coupling between a conductive film layer structure manufactured at the later stage of the first shielding unit 23a and the first lead unit 22a can be prevented, and the uniformity of display of each pixel in the first display area AA1 can be realized. Meanwhile, by setting the orthographic projection of the second shielding unit 23b on the substrate 10 to cover the orthographic projection of the second conducting wire unit 22b on the substrate 10 and connecting the second shielding unit 23b to a fixed potential, parasitic capacitance generated between a conductive film layer structure manufactured at the later stage of the second shielding unit 23b and the second conducting wire unit 22b can be prevented, and uniformity of display of each pixel in the second display area AA2 can be realized conveniently. In addition, since the shielding units are disposed in the first display area AA1 and the second display area AA2, the display brightness of the first display area AA1 and the display brightness of the second display area AA2 can be uniform, and the display effect of the display panel 100 can be improved.
In practical implementation, in order to improve the manufacturing efficiency of the display panel 100 and simplify the manufacturing process, the first shielding unit 23a and the second shielding unit 23b may be made of the same material, and the step S130 and the step S140 can be manufactured simultaneously.
In some embodiments, after forming the first wire unit 22a on the side of the first gate electrode 211a facing away from the substrate 10 and forming the second wire unit 22b on the side of the second gate electrode 211b facing away from the substrate 10, the method for manufacturing a display panel further includes:
s125, forming a first planarization layer 27 on the side of the first wire unit 22a and the second wire unit 22b away from the substrate 10.
After forming the first planarizing layer 27 at the side of the first wire unit 22a and the second wire unit 22b facing away from the substrate 10 at step S125, steps S130 and S140 may be performed, i.e., forming the first shielding unit 23a at the side of the first wire unit 22a facing away from the substrate 10 and forming the second shielding unit 23b at the side of the second wire unit 22b facing away from the substrate 10.
Optionally, after forming the first shielding unit 23a on a side of the first wire unit 22a facing away from the substrate 10 and forming the second shielding unit 23b on a side of the second wire unit 22b facing away from the substrate 10, the method for manufacturing a display panel further includes:
s150, forming a second planarizing layer 28 on a side of the first shielding unit 23a and the second shielding unit 23b facing away from the substrate 10.
With the above arrangement, the first shielding unit 23a is insulated from the first wire unit 22a, and the second shielding unit 23b is insulated from the second wire unit 22b, thereby preventing short circuit. Meanwhile, by forming the second planarizing layer 28, the film formation of the first light-emitting element 30a and the second light-emitting element 30b can be facilitated, and the quality of the display panel 100 can be improved.
Alternatively, after forming the first planarizing layer 27 on the side of the first wire unit 22a and the second wire unit 22b facing away from the substrate 10 at step S125, the first planarizing layer 27 may be subjected to a patterning process such that the first planarizing layer 27 includes a first opening at the first display area AA1 and a second opening at the second display area AA2, then, when steps S130 and 140 are performed, it is possible to electrically connect the first shielding unit 23a to the power supply line 50, for example to the anode power supply line 52, while the second shielding unit 23b is electrically connected to the power supply line 50 through the second opening, for example, to one of the anode power supply line 52 or to the cathode power supply line 51, the anode power supply line 52 or the cathode power supply line 51 can provide a stabilization signal to stabilize the potentials of the first gate electrode 211a and the second gate electrode 211 b.
In some embodiments, the display panel 100 further includes a third shielding unit 24a and a fourth shielding unit 24b, the third shielding unit 24a is formed between the first gate electrode 211a and the first wire unit 22a, and the fourth shielding unit 24b may be formed between the second gate electrode 211b and the second wire unit 22 b.
In another aspect, an embodiment of the present invention further provides a display device, including the display panel 100 of any one of the above embodiments. The display panel 100 has a first display area AA1 and a second display area AA2, and the pixel density of the first display area AA1 is less than that of the second display area AA2, so that the light transmittance of the first display area AA1 is greater than that of the second display area AA 2.
The display panel 100 includes a first surface and a second surface opposite to each other, wherein the first surface is a display surface. The display device further includes a photosensitive member located on the second surface side of the display panel 100, the photosensitive member corresponding to the first display area AA 1.
The photosensitive component can be an image acquisition device and is used for acquiring external image information. In this embodiment, the photosensitive component is a Complementary Metal Oxide Semiconductor (CMOS) image capture Device, and in other embodiments, the photosensitive component 200 may also be a Charge-coupled Device (CCD) image capture Device or other types of image capture devices. It will be appreciated that the photosensitive component may not be limited to an image capture device, for example, in some embodiments, the photosensitive component may also be an infrared sensor, a proximity sensor, an infrared lens, a flood sensing element, an ambient light sensor, and a light sensor such as a dot matrix projector. In addition, the display device may further integrate other components, such as an earpiece, a speaker, etc., on the second surface of the display panel 100.
According to the display device provided by the embodiment of the invention, the light transmittance of the first display area AA1 is greater than that of the second display area AA2, so that the display panel 100 can integrate photosensitive components on the back of the first display area AA1, for example, under-screen integration of the photosensitive components of an image acquisition device is realized, and meanwhile, the first display area AA1 can display pictures, so that the display area of the display panel 100 is increased, and the full-screen design of the display device is realized. Meanwhile, the first shielding unit 23a is disposed in the first display area AA1, and the second shielding unit 23b is disposed in the second display area AA2, so that there is no coupling between the first gate 211a of the first display area AA1 and the pixel anode, and there is no coupling between the second gate 211b of the second display area AA2 and the pixel anode, thereby improving the uniformity of the display luminance of the first display area AA1 and the second display area AA2, and preventing the display panel 100 from causing the non-uniform display luminance of the two display areas when the display panel 100 switches the image.
In accordance with the above embodiments of the present invention, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A display panel having a first display region and a second display region, the first display region having a pixel density smaller than that of the second display region, the display panel comprising:
a substrate;
the first driving transistor and the second driving transistor are positioned on the substrate, the first driving transistor is positioned in the first display area and comprises a first grid electrode, and the second driving transistor is positioned in the second display area and comprises a second grid electrode;
the first lead unit is electrically connected with the first grid and is positioned on one side of the first grid, which is far away from the substrate, and the second lead unit is electrically connected with the second grid and is positioned on one side of the second grid, which is far away from the substrate;
the first shielding unit is positioned on one side, away from the substrate, of the first lead unit, and the orthographic projection of the first shielding unit on the substrate covers the orthographic projection of the first lead unit on the substrate;
the second shielding unit is positioned on one side, away from the substrate, of the second lead unit, and the orthographic projection of the second shielding unit on the substrate covers the orthographic projection of the second lead unit on the substrate;
the first shielding unit and the second shielding unit are both connected to a fixed potential.
2. The display panel according to claim 1, wherein the first and second wire units are respectively connected to a reset signal terminal.
3. The display panel according to claim 1, wherein the plurality of first shielding units are arranged in a plurality of first shielding unit rows, and the first shielding units in each of the first shielding unit rows are arranged along a first direction and are in conduction with each other;
preferably, the plurality of second shielding units are arranged in a plurality of second shielding unit rows, and the second shielding units in each second shielding unit row are arranged along the first direction and are mutually conducted;
preferably, the plurality of second shielding units are arranged in a plurality of second shielding unit rows, each of the second shielding units in each of the second shielding unit rows is arranged along a first direction and is conducted with each other, the plurality of second shielding unit rows are arranged along a second direction and are conducted with each other to form a mesh structure, and the first direction intersects with the second direction;
preferably, the first shielding unit row and the second shielding unit row corresponding to the first direction position are electrically connected to each other.
4. The display panel according to claim 1, further comprising:
a plurality of first light-emitting elements located in the first display area and on a side of the first driving transistor facing away from the substrate, each first light-emitting element including a first electrode, a first light-emitting layer located on the first electrode, and a second electrode located on the first light-emitting layer, an orthogonal projection of at least a portion of the first electrode on the substrate and an orthogonal projection of the first wire unit on the substrate overlap to form a first projection pattern, and an orthogonal projection of the first shielding unit on the substrate covers the first projection pattern;
a plurality of second light emitting elements located in the second display region and on a side of the second driving transistor facing away from the substrate, the second light emitting elements including a third electrode, a second light emitting layer located on the third electrode, and a fourth electrode located on the second light emitting layer, an orthogonal projection of at least a portion of the third electrode on the substrate and an orthogonal projection of the second wire unit on the substrate overlap to form a second projection pattern, the second projection pattern being different from the first projection pattern,
and the second shielding unit orthographically projects the second projection pattern on the substrate.
5. The display panel according to claim 4, further comprising:
a first planarization layer between the first wire unit and the first shielding unit, and between the second wire unit and the second shielding unit;
a second planarization layer between the first shielding unit and the first electrode and between the second shielding unit and the third electrode.
6. The display panel according to claim 5, wherein the first planarizing layer includes a first opening in the first display region and a second opening in the second display region,
the display panel further includes:
a power supply line respectively located on a side of the first planarization layer departing from the first shielding unit and a side of the first planarization layer departing from the second shielding unit, the power supply line being used for supplying power to the first light emitting element and the second light emitting element, the first shielding unit being electrically connected with the power supply line through the first opening, the second shielding unit being electrically connected with the power supply line through the second opening.
7. The display panel according to any one of claims 1 to 6, characterized by further comprising:
the third shielding unit is positioned in the first display area and between the first grid and the first wire unit, and the orthographic projection of the third shielding unit on the substrate and the orthographic projection of the first shielding unit on the substrate are overlapped to cover the orthographic projection of the first grid on the substrate;
a fourth shielding unit located in the second display area and between the second gate and the second conducting wire unit, wherein an orthographic projection of the fourth shielding unit on the substrate and an orthographic projection of the second shielding unit on the substrate are overlapped to cover an orthographic projection of the second gate on the substrate;
preferably, the composition material of the first shielding unit comprises a transparent conductive material, and the composition material of the second shielding unit comprises a conductive material;
preferably, the first shielding unit and the second shielding unit are made of indium tin oxide;
preferably, the first shielding unit and the second shielding unit are connected to one of an anode power supply line and a cathode power supply line.
8. A preparation method of a display panel is characterized in that the display panel is provided with a first display area and a second display area, the pixel density of the first display area is smaller than that of the second display area, and the preparation method of the display panel comprises the following steps:
forming a first driving transistor and a second driving transistor on a substrate, wherein the first driving transistor is positioned in the first display area and comprises a first grid electrode, and the second driving transistor is positioned in the second display area and comprises a second grid electrode;
forming a first lead unit on one side of the first grid electrode, which is far away from the substrate, and forming a second lead unit on one side of the second grid electrode, which is far away from the substrate;
forming a first shielding unit on one side of the first lead unit, which is far away from the substrate, wherein the orthographic projection of the first shielding unit on the substrate covers the orthographic projection of the first lead unit on the substrate;
forming a second shielding unit on a side of the second wire unit facing away from the substrate, an orthographic projection of the second shielding unit on the substrate covering an orthographic projection of the second wire unit on the substrate,
wherein the first shielding unit and the second shielding unit are both connected to a fixed potential.
9. The method according to claim 8, wherein after the forming of the first wire unit on a side of the first gate electrode facing away from the substrate and the forming of the second wire unit on a side of the second gate electrode facing away from the substrate, the method further comprises:
forming a first planarization layer on one side of the first lead unit and the second lead unit, which faces away from the substrate;
preferably, after the forming of the first shielding unit at a side of the first wire unit facing away from the substrate and the forming of the second shielding unit at a side of the second wire unit facing away from the substrate, the method for manufacturing a display panel further includes:
forming a second planarization layer on the first shielding unit and the second shielding unit at the side away from the substrate;
preferably, the first shielding unit and the second shielding unit are both connected to a fixed potential includes the first shielding unit and the second shielding unit being connected to one of an anode supply line or a cathode supply line.
10. A display device comprising the display panel according to any one of claims 1 to 7, or the display panel produced by the production method for a display panel according to any one of claims 8 to 9.
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