CN113451231A

CN113451231A - WLCSP with transparent substrate and method of manufacturing the same

Info

Publication number: CN113451231A
Application number: CN202110329854.4A
Authority: CN
Inventors: D·加尼; R·阔
Original assignee: STMicroelectronics SA
Current assignee: STMicroelectronics SA; STMicroelectronics SRL
Priority date: 2020-03-27
Filing date: 2021-03-26
Publication date: 2021-09-28
Also published as: CN215644456U

Abstract

Embodiments of the present disclosure relate to WLCSP having a transparent substrate and methods of manufacturing the same. The present disclosure relates to a package, such as a Wafer Level Chip Scale Package (WLCSP), having a die coupled to a central portion of a transparent substrate. The transparent substrate includes a central portion and a peripheral portion surrounding the central portion. The package includes a conductive layer coupled to contacts of the die within the package, the contacts extending from the transparent substrate to an active surface of the package. The active surface is used to mount the package in an electronic device or to a Printed Circuit Board (PCB), respectively. The package includes a first insulating layer separating the die from the conductive layer and a second insulating layer on the conductive layer.

Description

WLCSP with transparent substrate and method of manufacturing the same

Technical Field

The present disclosure relates to a package body such as a Wafer Level Chip Scale Package (WLCSP) and a method of manufacturing the same.

Background

In general, a semiconductor device package, such as a chip scale package or a Wafer Level Chip Scale Package (WLCSP), contains a die, such as a sensor configured to detect any amount or quality of an external environment external to the semiconductor device package. For example, the semiconductor device package may detect light, temperature, sound, pressure, or any other quantity or quality of the external environment as desired.

Balancing all of the above preferences presents a significant challenge as the need increases to provide more semiconductor device packages in an electronic device to perform increasingly complex functions while reducing manufacturing costs, increasing resistance to external stresses to reduce the likelihood of failure, and improving the effectiveness of the semiconductor device. Examples of electronic devices include laptop computers, displays, televisions, smart phones, tablet computers, foldable electronics, or any other electronic device.

Disclosure of Invention

Embodiments of the present disclosure overcome significant challenges associated with packages, such as Wafer Level Chip Scale Packages (WLCSP), such as improving the effectiveness and robustness of light sensors within the WLCSP.

One significant challenge is to reduce the amount of light escaping from the transparent substrate when the WLCSP is configured as a light sensor. For example, depending on the configuration of the layers and components of the light sensor (e.g., a glass lens aligned with the light sensor), light emitted by an external light source entering the WLCSP or package from the external environment may be able to escape from the WLCSP or package before completely reaching the light sensor.

In the present disclosure, an embodiment of a WLCSP configured to detect light includes a transparent substrate, a die, a light sensor in the die, a first insulating layer on the die, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and a molding compound layer on a sidewall of the transparent substrate. The molding compound layer is formed of an opaque material on the sidewalls of the transparent substrate. This reduces the amount of light escaping from the sidewalls of the transparent substrate and increases the amount of light reaching the photo sensor of the die. Therefore, it is desirable for a layer of opaque molding compound to be on the sidewalls of the transparent substrate to increase the light reaching the photo sensors of the die.

Another significant challenge is to manufacture WLCSP with a minimum number of highly specialized machines and a minimum amount of scrap, to reduce the cost of manufacturing WLCSP, and to increase the yield of available WLCSP with transparent substrates.

In an embodiment of the method of manufacturing WLCSP, a 12-inch semiconductor wafer is converted to an 8-inch wafer. The transparent wafer is coupled to a 12 inch semiconductor wafer, which may include active and passive components. The transparent wafer and the 12-inch semiconductor wafer are divided to form a plurality of substrate assemblies each including a semiconductor substrate and a transparent substrate secured to each other. A plurality of substrate components are coupled to a carrier substrate (e.g., glass, silicon, etc.). The molding compound is then formed on the plurality of substrate assemblies to form 8-inch wafers, which are then further processed by highly specialized machines to form a plurality of WLCSP. Thus, by converting a 12 inch wafer to an 8 inch wafer through the above process, a machine utilizing only 8 inch wafers can be utilized, and by converting a 12 inch wafer to an 8 inch wafer, it is not necessary to utilize any highly specialized machine replicas when manufacturing WLCSP.

In this embodiment of the method of manufacturing WLCSP, a preferably opaque molding compound is formed on and covers the sidewalls of the substrate assembly on the carrier support. The molding compound fills the spaces or channels between the substrate components that are coupled to the carrier substrate. A plurality of trenches is formed in the molding compound and the plurality of semiconductor dies. Various layers of materials (e.g., insulating layers, passivation layers, transparent substrates, conductive layers, and other various material layers) are formed in the plurality of trenches and on the plurality of substrate assemblies. After forming the various layers, the 8-inch wafer is diced to form WLCSP. The wafer is singulated at locations between the plurality of transparent substrates where the molding compound is present. By dicing the wafer at these locations, the likelihood of cracking or breaking the transparent substrate is significantly reduced since the transparent substrate is not diced multiple times. Additionally, by retaining some of the molding compound during this singulation step, a layer of molding compound on the sidewalls of the transparent substrate is formed in the completed package. Thus, this embodiment of the method of manufacturing the WLCSPs reduces the manufacturing cost as the yield of available WLCSPs increases.

Yet another significant challenge is to reduce the thickness of the WLCSP while maintaining its functionality. For example, as electronic devices become thinner, more hingeable (e.g., foldable displays or devices, flexible displays or devices, etc.), and interactive (e.g., touch screens, haptic feedback, etc.), the space to provide a semiconductor die within the electronic device is significantly reduced. It is desirable to make the WLCSP thin so that the WLCSP can be incorporated into the small space available within an electronic device to provide information to the electronic device to function as needed.

In this embodiment of the method of manufacturing a WLCSP, a 12-inch semiconductor wafer including active and passive components is coupled to a transparent wafer. The transparent wafer may be coupled to the 12 inch semiconductor wafer using a transparent die attach film, transparent glue, or alternative transparent die attach material that allows light to pass through. By coupling the 12-inch semiconductor wafer to the transparent wafer at the beginning of the process, there is no need to apply a cover or lens to the WLCSP to allow light to reach the light sensor, thereby reducing the overall thickness of the complete WLCSP. Thus, this embodiment of the method of manufacturing the WLCSPs reduces the overall thickness of the complete WLCSP.

Drawings

In the drawings, like reference numerals identify similar elements or acts unless context dictates otherwise. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale.

FIG. 1A is a top view of one embodiment of a Wafer Level Chip Scale Package (WLCSP) including a die having a light sensor and a transparent substrate aligned with the light sensor of the die;

FIG. 1B is a cross-sectional view of one embodiment of a WLCSP taken along line 1B-1B in FIG. 1A;

FIG. 1C is a bottom plan view of one embodiment of the WLCSP of FIGS. 1A and 1B;

FIG. 2 is a cross-sectional view of an alternative embodiment of a WLCSP taken along a line similar to line 1B-1B in FIG. 1A;

FIG. 3 is a cross-sectional view of an alternative embodiment of a WLCSP taken along a line similar to line 1B-1B in FIG. 1A;

fig. 4A is a flow diagram of a method of manufacturing an embodiment of WLCSP, such as the WLCSP shown in fig. 1A-1C, in accordance with one or more embodiments; and

fig. 4B-4Q are cross-sectional views of a method of manufacturing embodiments of WLCSPs, such as the WLCSP shown in fig. 1A-1C, as indicated in the flowchart in fig. 4A and in accordance with one or more embodiments.

Detailed Description

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electrical component and semiconductor fabrication techniques have not been described in detail to avoid unnecessarily obscuring descriptions of the embodiments of the disclosure.

Unless the context requires otherwise, throughout the following description and claims, the word "comprise" and variations such as "comprises" and "comprising" should be interpreted in an open inclusive sense, i.e., as "including but not limited to.

The use of ordinals such as first, second and third does not necessarily imply a sense of rank after ordering, but may merely distinguish between multiple instances of an action or structure.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As described below, the terms "left," "right," "top," and "bottom" are used for discussion purposes only based on the orientation of the components in the discussion of the figures in this disclosure. These terms are not limited to the possible locations explicitly disclosed, implicitly disclosed, or inherently disclosed in this disclosure.

The term "substantially" is used to clarify that there may be subtle differences when manufacturing WLCSP in the real world, as it is not possible to make anything exactly equal or exactly the same. The term is not limiting as it is merely intended to clarify the real world manufacturing manner of WLCSP. In other words, basically means that in actual practice there may be some slight variations, since it is not possible to make anything perfect, but within acceptable tolerances.

As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise.

The present disclosure relates to various embodiments of semiconductor device packages, such as Wafer Level Chip Scale Packages (WLCSP), each including a semiconductor die and a transparent substrate. The transparent substrate is aligned with the sensor of the die and is configured to expose the sensor of the die to light from an external light source. In some other embodiments, the die may include an LED or light source aligned with the transparent substrate to emit light through the transparent substrate.

In some embodiments, the transparent substrate includes a central portion having a first height and a peripheral portion surrounding the central portion having a second height. The first height of the central portion is greater than the second height of the peripheral portion surrounding the central portion. The peripheral portion has a sidewall covered by a molding compound layer. The molding compound layer surrounds the transparent substrate and forms a boundary around the transparent substrate. The molding compound is an opaque material configured to increase the amount of light reaching the sensor of the die by reducing the amount of light escaping from the sidewalls of the transparent substrate as the light passes through the transparent substrate to the sensor. The molding compound also protects the transparent substrate of the package during the singulation process during the manufacturing process because the molding compound is cut instead of the transparent substrate. The die is on a central portion of the transparent substrate and the sensor is aligned with the central portion of the transparent substrate.

While various embodiments are shown and described with respect to WLCSP, it will be readily understood that embodiments of the present disclosure are not so limited. In various embodiments, the structures, devices, methods, etc. described herein may be implemented or otherwise utilized with any suitable type or form of semiconductor package or WLCSP, and may be fabricated using any suitable semiconductor packaging technology as desired.

Fig. 1A is a top view of an embodiment of a package 100, such as WLCSP. The package 100 includes an insulating layer 101 having a first surface 102 and a plurality of conductive contacts 104 exposed through openings 106 in the first surface 102. The insulating layer may be a passivation layer, a molding compound layer, an epoxy layer, or some other insulating material. The first surface 102 may be referred to as an active or mounting surface of the package 100 because the plurality of conductive contacts 104 are configured to be mounted to a Printed Circuit Board (PCB) or within an electronic device via a conductive material. The contacts 104 are coupled to active and passive components within the package 100, which will be discussed in more detail below with respect to fig. 1B.

Fig. 1B is a cross-sectional side view of the package 100 taken along line 1B-1B in fig. 1A, and fig. 1C is a bottom plan view of the package 100 in fig. 1A and 1B. The line 1B-1B passes through three of the contacts 104 of the package 100.

The package body 100 includes a second surface 108 opposite the first surface 102. The second surface 108 may be referred to as a passive surface because the second surface 108 does not include any active or passive conductive components. In contrast, the second surface 108 includes a surface of the transparent substrate 110 and a surface of the molding compound layer 112. The transparent substrate 110 may be a glass material, an acrylic material, a plastic material, or any other transparent material or combination of transparent materials that allow light to pass through and have high transmittance. Alternatively, the transparent substrate 110 may be a stack of multiple layers of materials to increase the transmission of light through the multiple layers. The surface of the transparent substrate 110 and the surface of the molding compound layer 112 are substantially flush or coplanar.

The surface of the transparent substrate 110, which is a portion of the second surface 108 of the package 100, is uncovered. A layer of molding compound 112 is on the sidewalls 114 of the transparent substrate 110. The sidewalls 114 of the transparent substrate 110 have a first height h₁. The molding compound layer 112 has sidewalls 116 with a first height h₁. The molding compound layer 112 is preferably an opaque material, such as a molding compound comprising carbon black pigment, a plastic molding compound made of an opaque material, or some other opaque material or combination of opaque materials that do not allow light to pass through. The use of an opaque material enables the molding compound layer 112 to prevent light from escaping from the sidewalls 114 of the transparent substrate 110 after the light has entered through the uncovered surface of the transparent substrate 110, which will be discussed in more detail later within this disclosure.

The transparent substrate 110 includes a central portion 120 having a second height h₂The second height is greater than the first height h of the

sidewalls

114 and 116 of the transparent substrate 110 and the molding compound layer 112₁. The transparent substrate 110 also includes a peripheral portion 122 that surrounds the central portion 120 and forms a boundary or perimeter around the central portion 120. The peripheral portion 122 has a first height h of the sidewall 114 of the transparent substrate 110₁。

The transparent substrate 110 includes a connection portion 124 having an inclined surface 126 coupling the peripheral portion 122 to the central portion 120. The central portion 120, the peripheral portion 122 and the connecting portion 124 are made of a continuous material of the transparent substrate 110. The slope of the sloped surface 126 is defined by a first height h at the peripheral portion 122₁Second height h from the central part₂The height difference therebetween. In some other embodiments, the first height isDegree h₁May be greater than the second height h₂Or a first height h₁May be at a second height h₂Are substantially the same.

Semiconductor die 128 is coupled to central portion 120 of transparent substrate 110. The die is coupled to the central portion 120 of the transparent substrate 110 by an adhesive (not shown). The adhesive may be glue, Die Attach Film (DAF), or some other adhesive material or combination of adhesive materials. The semiconductor die 128 is opposite the second surface 108 of the package 100. Semiconductor die 128 includes active and passive components to perform a desired function. For example, the semiconductor die 128 may include any other quality or quantity of components configured to detect light, pressure, sound, temperature, humidity, or an external environment.

Semiconductor die 128 includes an active surface 130 and a passive surface 132 opposite active surface 130. The active surface 130 is on the central portion 120 of the transparent substrate 110 and faces the transparent substrate 110. The passive surface 132 is opposite the active surface 130 and faces away from the transparent substrate 110 and the active surface 130 of the semiconductor die 128. Passive surface 132 does not include any active or passive components, while active surface 130 includes active and conductive components. Sloped surface 133 of semiconductor die 128 extends between active surface 130 and passive surface 132 of semiconductor die 128.

Semiconductor die 128 includes a sensor 134 at active surface 130 of semiconductor die 128. The sensor 134 may be a photosensor such as an image sensor, a Single Photon Avalanche Diode (SPAD), or some other type of photosensor or combination of photosensors as desired. The sensor 134 may be configured to detect infrared light, ultraviolet light, visible light, or light of any wavelength, as desired. Light sensor 134 may be a sensor array or a plurality of sensors positioned on active surface 130 of semiconductor die 128. In some other alternative embodiments, sensor 134 may be another type of sensor, such as a sensor configured to detect pressure, sound, temperature, humidity, or any other quality or quantity of the external environment. Light sensor 134 may be positioned at the center of active surface 130 of semiconductor die 128.

Electrical connections 136 have a first end coupled to light sensor 134 and a second end coupled to contacts 138 on the surface of semiconductor die 128. The electrical connections 136 may be configured to communicate signals from the light sensor 134 to the contacts 138 or from the contacts 138 to the light sensor 134 as desired. Electrical connections 136 may include a conductive material, such as copper or a doped semiconductor, extending across or on the surface of semiconductor die 128. Electrical connections 136 may also include various circuit devices such as transistors, diodes, or other conductive elements.

The contacts 138 are conductive materials such as copper materials, gold materials, aluminum materials, alloy materials, or any other conductive material or combination of conductive materials as desired. Contacts 138 extend outwardly from an edge of semiconductor die 128 and extend away from light sensor 134 of semiconductor die 128. The contacts 138 extend across the central portion 120 of the transparent substrate 110 to the edge of the transparent substrate 110 where the central portion 120 meets the connecting portion 124.

Another insulating layer 140 is on the passive surface 132 and the sloped surface 133 of the die. An insulating layer 140 is also on the contacts 138. The insulating layer 140 may be any electrically insulating material, such as an epoxy material, a plastic material, a passivation material, a re-passivation material, a dielectric material, or some other insulating material or combination of insulating materials, as desired. Insulating layer 140 is configured to separate semiconductor die 128 from conductive layer 142 to avoid conductive layer 142 from contacting semiconductor die 128.

A conductive layer 142 is on the insulating layer 140, the contacts 138 of the semiconductor die 128, and the peripheral portion 122 and the connection portion 124 of the transparent substrate 110. Conductive layer 142 contacts sidewalls of contacts 138 of semiconductor die 128. Conductive layer 142 allows signals to communicate from an external device to contacts 138 of the die and from contacts 138 of the die to an external device. For example, the external device may be a controller, an electronic device, a memory, or some other component of an electronic device that is configured to control or utilize the package 100 to perform a desired function. The conductive layer 142 includes a first end 144 on the peripheral portion 122 of the transparent substrate 110. In this embodiment, the first end 144 is positioned between the sidewall 114 of the transparent substrate 110 and the connecting portion 124 of the transparent substrate 110. However, in other alternative embodiments, the first end 144 may be positioned on the connecting portion 124 or may extend to the sidewall 114 of the transparent substrate 110. Conductive layer 142 may be referred to as an electrical connector, a redistribution layer (RDL), or some other conductive connector or combination of conductive connectors, as desired. In alternative embodiments, the conductive layer may be a conductive via.

The insulating layer 101 is on the conductive layer 142, the molding compound layer 112, the insulating layer 140, and the peripheral portion 122 and the connection portion 124 of the transparent substrate 110. Insulating layer 101 is configured to protect conductive layer 142 from external conductive materials, thereby avoiding short circuits, or undesired electrical connections, between conductive layer 142 and external electrical components on the PCB or within the electronic device. Insulating layer 101 covers first end 144 of conductive layer 142. Insulating layer 101 includes sidewalls 148. The sidewalls 148 of the insulating layer 101 are substantially flush or coplanar with the sidewalls 116 of the molding compound layer 112. The insulating layer 101 includes openings 106 that expose the contacts 104. The contact 104 is the portion of the conductive layer 142 exposed by the opening 106 in the insulating layer 101. The opening 106 is shown as having a square shape, however, in alternative embodiments, the opening may have a circular shape, a rectangular shape, or any other shape as desired. The insulating layer 101 may be any insulating material, such as an epoxy material, a plastic material, a passivation material, a re-passivation material, a dielectric material, or some other insulating material or combination of insulating materials. The insulating layer 101 may be referred to as a protective layer.

In this embodiment, the dimensions of the package 100 are as follows. The transparent substrate 110 has a thickness of about 100-500 microns, the die has a thickness of 50-200 microns, the conductive layer 142 has a thickness of 3-5 microns, and the insulating layer 140 has a thickness of 10-30 microns. Although these are thicknesses of various components of the package 100 in this embodiment, for purposes of clarity, these components are not drawn to scale exactly in fig. 1B. Although in this embodiment the above dimensions may be as listed above, in some other alternative embodiments of the WLCSP, the WLCSP may have dimensions that are entirely different from those set forth above.

Fig. 1C is a top plan view of an embodiment of the package 100 as seen in fig. 1A and 1B. As previously described, the package 100 includes the transparent substrate 110. The transparent substrate 110 includes a central portion 120, a peripheral portion 122, and a connection portion 124. The connecting portion 124 extends between the central portion 120 and the peripheral portion 122 and couples the central portion 120 to the peripheral portion 122. In addition, as previously discussed with respect to fig. 1B, the peripheral portion 122 surrounds both the central portion 120 and the connecting portion 124 and forms a perimeter or boundary around both the central portion 120 and the connecting portion 124. Similarly, the connecting portion 124 surrounds the central portion 120 and forms a perimeter or boundary around the central portion 120. The relationship of these various portions of the transparent substrate 110 can be clearly seen in FIG. 1C. Additionally, as previously discussed with respect to fig. 1B, the semiconductor die 128 is on the central portion 120 of the transparent substrate 110 and the sensor 134 is aligned with the central portion 120 of the transparent substrate 110, as can be clearly seen in fig. 1C.

Fig. 2 is a cross-sectional view of an alternative embodiment of a package 200 a. The package 200a may be a WLCSP or a semiconductor package. This cross-sectional view of package 200a is taken along a line similar to 1B-1B in fig. 1A of package 100. The package 200a has similar features as the embodiment in the package 100 illustrated in fig. 1B, which features are denoted by the same reference numerals as in fig. 1B.

However, in this alternative embodiment, package 200a includes cavity 202. The cavity 202 is aligned with the central portion 120 of the transparent substrate 110. Cavity 202 is adjacent to and aligned with light sensor 134 of semiconductor die 128. The cavity 202 spaces the central portion 120 of the transparent substrate 110 from the light sensor 134. A cavity is formed in material layer 208a between semiconductor die 128 and transparent substrate 110. In this alternative embodiment, material layer 208a couples semiconductor die 128 to transparent substrate 110. Material layer 208a may be an insulating material, a non-conductive material, an adhesive material, or any combination of insulating or insulating materials, as desired. Alternatively, in some other embodiments of the package, the cavity 202 may be formed from a multi-layer material rather than a materialA layer 208a is formed. In other alternative embodiments, the cavity 202 may be within the central portion 120 of the transparent substrate 110, or extend into the central portion 120 of the transparent substrate 110. The second height h if the cavity 202 is within the central portion 120 of the transparent substrate 110₂May be smaller than the first height h₁Or a second height h₂May be at the first height h₁Are substantially the same. For example, if the cavity 202 extends far enough within the transparent substrate 110 toward the surface 108, the central portion 120 of the transparent substrate 110 will have a second height h₂The second height is smaller than the first height h of the peripheral portion 122₁。

The thickness of the cavity 202 in the package body 200a is substantially equal to the thickness of the material layer 208 a. In some other embodiments, the cavity may have a thickness that is greater than the thickness of material layer 208a or less than the thickness of material layer 208 a. In other words, the cavity 202 may have any size as desired.

In some embodiments of the package, the light sensor 134 may extend into the cavity 202. The cavity may be wide enough and deep enough to allow the sensor to fully fit within the cavity or to allow the sensor to partially fit within the cavity.

Fig. 3 is a cross-sectional view of an alternative embodiment of a package 200b, which is similar to package 200a in fig. 2. The package 200B has similar features as the embodiments in the

packages

100, 200a in fig. 1B and 2, which features are denoted by the same reference numerals as in fig. 1B and 2.

However, in this alternative embodiment, package 200b includes multiple layers of material 208b between semiconductor die 128 and transparent substrate 110. The multilayer material 208b can be multiple layers of insulating material, non-conductive material, multiple layers of adhesive material, or multiple layers of any insulating material, as desired. In this alternative embodiment, the multilayer material 208b couples the semiconductor die to the transparent substrate 110. Unlike the package 200a in fig. 2, the package 200b includes a portion of the multilayer material 208b between the transparent substrate 110 and the conductive layer 142, and an end portion 209 of the multilayer material 208b has a surface covered by the molding compound layer 112. A portion of the multilayer material 208b separates the conductive layer 142 from the transparent substrate 110. Unlike the package 200a, the package 200b has the transparent substrate 110, however, the transparent substrate 110 has substantially the same height as along the length of the transparent substrate 100 extending between the sidewalls 114 of the transparent substrate 110.

Alternatively, in some other embodiments of the package, the cavity 202 may be formed of a single layer of material rather than the multilayer material 208b, and the end 209 may be covered by the insulating layer 101. In other alternative embodiments, the cavity 202 may be within the central portion 120 of the transparent substrate or extend into the central portion 120 of the transparent substrate.

The thickness of the cavity 202 in the package 200b is substantially equal to the thickness of the multilayer material 208 b. In some other embodiments, the cavity can have a thickness that is greater than the thickness of the multilayer material 208b or less than the thickness of the multilayer material 208 b. In other words, the cavity 202 may have any size as desired.

Package 200b includes an insulating layer 204 formed on insulating layer 101 and under an Under Bump Metallurgy (UBM)206 in insulating

layers

101, 204. The insulating layer 204 may be an epoxy material, a plastic material, a passivation material, a re-passivation material, or some other insulating material or combination of insulating materials. As shown in fig. 2, UBMs 206 each include a recess extending toward semiconductor die 128 to enable better contact with solder bumps (discussed below) used to electrically connect package 200a to a PCB or other device.

In some other alternative embodiments of WLCSP, UBM206 may have a different shape or configuration. For example, UBM206 may extend outward from insulating layer 204, or UBM206 may be on insulating layer 204. Accordingly, UBM206 may have any shape or configuration as desired.

Fig. 4A is a flow chart of an embodiment of a method 300 of manufacturing the package 100 and an alternative embodiment of the WLCSP as disclosed in this disclosure. These steps will be discussed in detail with respect to the structures illustrated in fig. 4B-4Q. This embodiment of the manufacturing method 300 involves manufacturing the package 100 shown in fig. 1A-1C. However, other alternative embodiments, such as the packages 200a, 200b in fig. 2 and 3, may be fabricated by adding additional steps to the method 300.

The method 300 includes a wafer preparation process 301 that processes and singulates a 12-inch wafer into individual dies using

steps

302, 304, 306, and a reconstitution and molding process 303 that processes the singulated individual dies using

steps

308, 310, 312 to form an 8-inch wafer. The remaining

steps

314, 316, 318, 320, 322, 324, 326, 328 of the method 300 are further process steps for forming the package 100.

Step 302 of wafer preparation process 301 of method 300 is a wafer bonding step 302 in which a semiconductor wafer 330 is coupled to a transparent wafer 332, as shown in fig. 4B. Prior to the wafer bonding step 302, the semiconductor wafer 330 will have been processed to form an electronic circuit device including the sensor 134. The active surface 333 of the semiconductor wafer 330 is coupled to the transparent wafer 332, which can be seen in fig. 4C. Fig. 4C is a cross-sectional view taken along line 3C-3C in fig. 4A. The semiconductor wafer 330 may be a 12 inch wafer, or have other diameters. The transparent wafer 332 may be any transparent material discussed above with respect to the transparent substrate 110, which will be formed from the transparent wafer 332 as discussed below. Semiconductor wafer 330 may be bonded to transparent wafer 332 using any of the adhesive materials discussed above with respect to coupling semiconductor die 128 to transparent substrate 110.

Step 304 of the wafer preparation process 301 is an optional back grinding step 304, in which the passive surface 338 of the semiconductor wafer 330 facing away from the transparent wafer 332 and the active surface 333 of the semiconductor wafer 330 are ground to reduce the thickness of the semiconductor wafer 330. In step 306, as shown in fig. 4C and 4D, the semiconductor wafer 330 and the transparent wafer 332 are singulated into substrate assemblies 339. Fig. 4C illustrates the cutting tool 334 cut along a dashed line 336 that indicates where the semiconductor wafer 330 and the transparent wafer 332 were separated by the cutting tool 334. Fig. 4D illustrates a substrate assembly 339 that includes the transparent substrate 110 and the semiconductor die 128 shown in fig. 1B. The cutting tool 334 may be a laser, a saw, or some other mechanical cutting device or cutting technique as desired.

After step 306, in which the semiconductor and transparent wafers 332 are singulated into substrate assemblies 339, in step 308, the plurality of transparent substrates 110 are coupled to a carrier support 340, which can be seen in fig. 4E. Fig. 4F to 4H are cross-sectional views taken along line 3F-3F in fig. 4E.

In one embodiment, carrier support 340 is an 8 inch carrier support, but other sizes may be employed. The carrier support 340 may be a silicon (e.g., glass) carrier substrate, a support wafer, a dummy wafer, or some other support material or carrier support configured to support a plurality of substrate components 339 during further processing. The transparent substrate 110 is coupled to the carrier support 340 by a temporary adhesive material (not shown). The temporary bonding material may be a thermally decomposed bonding material, a water decomposed bonding material, a photosensitive decomposed material, or some other bonding material that can be decomposed or removed without leaving a residue on the transparent substrate 110. For simplicity of discussion, the temporary adhesive will be a temporary heat-decomposable adhesive material.

A plurality of substrate assemblies 339 may be positioned on carrier support 340 by a pick and place machine. The substrate assembly 339 has a pass width d₁Are spaced apart from each other as shown in fig. 4F.

After step 308 of coupling the plurality of substrate assemblies 339 to the support 340, a molding compound 343 is formed on the plurality of substrate assemblies 339 and the support 340 in step 310, which can be seen in fig. 4G. The channels 342 between the plurality of dies 128 and the plurality of transparent substrates 110 are filled with a molding compound 343. The molding compound 343 is an opaque material. For example, the opaque material of the molding compound 343 may be a molding compound doped with carbon black pigment, may be a plastic molding compound doped with carbon black pigment, or may be some other opaque material or combination of opaque materials. The opaque material of the molding compound 343 does not allow light to pass through. Once the molding compound 343 is placed in the channels 342, on the plurality of dies 128, on the plurality of transparent substrates 110, and on the carrier support 340, the molding compound 343 is allowed to cure and harden.

After the mold compound 343 is formed, the carrier support 340 is removed or separated from the mold compound 343 and the transparent substrate 110 in step 312, which can be seen in fig. 4H. The carrier support 340 is removed by exposing the carrier support 340 and the temporary thermally decomposable adhesive material coupling the carrier support to the transparent substrate 110 to heat to decompose the temporary thermally decomposable adhesive material. Removal of the carrier support 340 leaves a wafer 346 that includes a base assembly 339 and a mold compound 343, which can be seen in the bottom plan view of fig. 4I. In some other embodiments, support 340 may itself be a thermally decomposable material, a photo-decomposable material, a laser decomposable material, a water decomposable material, or some other type of decomposable material that is decomposed for removal as desired.

After step 312, in which carrier support 340 is removed to form wafer 346, wafer 346 is ground to remove molding compound 343 covering semiconductor die 128 in step 314. The grinding of wafer 346 may also remove portions from passive surface 132 of die 128, thereby reducing the thickness of die 128. However, in some alternative embodiments, die 128 may not be ground. Grinding the molding compound 343 exposes the top of the die 128 while leaving the molding compound 343 in the channels 342 between the base assemblies 339.

This grinding step 314 may be referred to as a planarization step because the molding compound 343 and the passive surface 132 of the die 128 are made substantially flush and coplanar with each other, as can be seen in fig. 4J. The polishing step 314 may be accomplished by a chemical mechanical polishing tool, a mechanical polishing tool, or some other polishing tool or planarization tool or technique to form a substantially planar surface of the wafer.

After step 314, where wafer 346 is ground or planarized, a plurality of trenches 350 are formed in step 316 that extend into wafer 346, as can be seen in FIG. 4K. The plurality of trenches 350 are formed by removing portions of the molding compound 343 between the die 128 and portions of the die 128.

The plurality of trenches 350 may be formed by dry etching, wet etching, sawing, dicing, laser, or some other removal technique. For example, a photolithography process may be used to define die 128 and portions of molding compound 343, and then a dry etching technique (e.g., plasma etching) is performed to remove die 128 and portions of molding compound 343.

The dry etching process forms the sloped surface 133 of each semiconductor die 128 and exposes the surfaces 352 of the contacts 138. These surfaces 352 of the contacts 138 face away from the transparent substrate 110. The first end 144 of the contact 138 remains covered by the portion 354 of the die 128 left after the trench 350 is formed. Each of these portions 354 of each semiconductor die 128 extends from each first end 144 of each contact 138 to a sidewall 114 of the transparent substrate 110. The molding compound 343 remains positioned between the first ends 144 of the contacts 138 and the portions 354 of adjacent semiconductor dies 128 in the 8-inch wafer 346. The molding compound 343 extends between the sidewalls 114 of the transparent substrate 110.

Each trench 350 extends a first distance d from the inactive surface of the semiconductor die 128 to the molding compound 343 or the surface 352 of each contact 138 exposed by the trench 350₂。

After forming the trench 350, in step 318, an insulating layer 140 is formed, which can be seen in fig. 4L. The insulating layer 140 is formed on the passive surface 132 and the inclined surface 133 of the die 128, on the surface 352 of the contact 138, and on the molding compound 343 between the transparent substrate 110. The insulating layer 140 partially fills the plurality of trenches 350. The insulating layer 140 may be formed using chemical vapor deposition, physical vapor deposition, sputtering, or some other deposition technique or combination of deposition techniques.

After the insulating layer 140 is formed, in step 320, a plurality of trenches 350 are extended further into the wafer 346, which can be seen in fig. 4M. Step 320 may use a saw tool or other device to remove portions of transparent substrate 110, portions of molding compound 343, portions of contacts 138, die portions 354, and portions of insulating layer 140. Step 320 increases the distance d that the plurality of grooves 350 extend into the semiconductor die 128₂. In some alternative embodiments, the distance d is achieved by not removing portions of the transparent substrate 110 and the die portion 354₂May remain the same.

The extended trench forms the sloped surface 358 of each contact 138 of each semiconductor die 128 and the sloped surface 126 of the connection portion 124 of the transparent substrate 110 in step 320. The

inclined surfaces

126, 358 may be substantially flush or coplanar with one another.

After step 320, step 322 forms conductive layer 142 directly on insulating layer 140, inclined surfaces 358 of contacts 138, transparent substrate 110, and molding compound 343. Conductive layer 142 may be deposited by utilizing a vapor deposition technique, an electrochemical deposition technique, a sputtering technique, or some other deposition technique or combination of deposition techniques.

After conductive layer 142 has been deposited, conductive layer 142 is patterned to form openings 362 through conductive layer 142 on insulating layer 140 and openings 364 through conductive layer 142 within plurality of trenches 350, as shown in fig. 4N. Conductive layer 142 may be patterned using a sawing technique, a cutting technique, a dry etching technique, a wet etching technique, or some other patterning technique or combination of patterning techniques to remove portions of conductive layer 142. Openings 362, 364 separate portions of conductive layer 142. The openings 362 in the conductive layer 142 expose portions of the insulating layer 140 and the openings 364 in the plurality of trenches 350 expose the molding compound 343. After step 322, where conductive layer 142 is formed, insulating layer 101 is formed in a plurality of trenches 350 in step 324, which can be seen in fig. 4O. An insulating layer 101 is formed over the conductive layer 142 that has been patterned, in the openings 362, 364 in the conductive layer 142, over the transparent substrate 110, over the insulating layer 140, and over the molding compound 343. The insulating layer 101 may be deposited using a vapor deposition technique, a chemical deposition technique, a sputter deposition technique, or some other deposition technique or combination of deposition techniques. As discussed above, the insulating layer 101 may be patterned to form the openings 106 and expose the plurality of conductive contacts 104.

After the insulating layer 101 is formed, solder balls 366 are formed in the openings 106 and on the plurality of conductive contacts 104 in step 326, as can be seen in fig. 4P. The solder balls 366 may be formed by a reflow technique, by an injection technique, or by some other solder ball forming technique or combination of solder ball forming techniques. The solder balls 366 are configured to allow the complete package 100 to be mounted to a PCB or electronic device. In some other embodiments, solder balls 366 may be formed on package 100 after singulation.

After the solder balls 366 are formed, the wafer 346 after the above processing steps 314-326 is singulated into individual and complete packages 100 in step 328, as can be seen in fig. 4P and 4Q. The singulation step 328 uses a cutting tool 370 to cut through the stack of layers of material at the locations indicated by dashed lines 368. The cutting tool 370 may be a saw, a laser, or some other cutting or separating tool, as desired. The molding compound 343 between the transparent substrates 110 acts as a buffer by protecting the transparent substrates 110 from the cutting tool 370 during singulation.

The above method may be modified to form the package 200a in fig. 2 by depositing the material layer 208a on a 12-inch transparent wafer 332, and coupling the 12-inch wafer 330 to the 12-inch transparent substrate 332. This layer of material 208a allows the cavity 202 to be formed between the die 128 and the transparent substrate 110 of the package 200 a. The material layer 208a may be patterned to form the cavity 202.

The above method may be modified by depositing multiple layers of material 208b on a 12 inch transparent wafer 332 and coupling a 12 inch wafer 330 to the multiple layers 20b on the 12 inch transparent wafer 332 to form the package 200b in fig. 3. The multilayer material 208b allows the cavity 202 to be formed between the die 128 and the transparent substrate 110 of the package 200 b. When forming the package 200b, the multilayer material 208b may be patterned to form the cavity 202, or may be deposited in selected areas to form the cavity 202.

Additionally, the above method may be modified after step 324 and before step 326 by depositing insulating layer 204 on insulating layer 101, opening 106, and on contact 104 to form package 200 b. After the insulating layer 204 is deposited, the insulating layer 204 is patterned to re-expose the contacts 104. The insulating layer 204 may be patterned using an etching technique, a saw technique, a laser technique, or some other patterning technique or combination of patterning techniques. After the insulating layer 204 is patterned, a second conductive layer is deposited on the insulating layer 204 and covers the contacts 104. After the second conductive layer is deposited, the second conductive layer is patterned to form UBM 206.

The methods described herein may provide a number of advantages over prior art methods. For example, coupling the semiconductor die 128 directly to the transparent substrate 110 makes the packages 100, 200 thinner than prior art packages that utilize a lid and lens arrangement. Many prior art devices employ such a cover to cover and protect the die and sensor. This increases the overall thickness and lateral size of the package. Thus, by directly coupling the semiconductor die 128 to the transparent substrate 110, the overall size of the packages 100, 200 may be made smaller than conventional packages.

The method 300 may generate less waste than conventional methods by using the remaining substrate assembly 339 formed by separating the 12 inch wafer 330 and the 12 inch transparent wafer 332 that were not used to form the first 8 inch wafer 346 when forming the additional second 8 inch wafer.

When the wafer 346 is singulated into packages 100 in step 328, the method 300 may improve the yield of available packages 100 because the molding compound 343 protects the transparent substrate 110. The molding compound acting as a buffer reduces the likelihood of chipping or cracking in the transparent substrate 110 because the transparent substrate 110 is not cut directly by the cutting tool 370 during the singulation step 328. This reduction in the likelihood of cracking or breaking on the transparent substrate increases the yield of the number of packages 100 available.

Furthermore, the method 300 may also reduce the overall cost of manufacturing the package 100 by not requiring new highly specialized machines. Method 300 may use existing highly specialized machines that are only capable of using 8 inch wafers because substrate assembly 339 may be formed from 12 inch wafers and placed on 8 inch carrier 340. In some other embodiments of the method, a 12 inch wafer may be converted to another 12 inch wafer, an 8 inch wafer may be converted to a 12 inch wafer, an 8 inch wafer may be converted to another 8 inch wafer, or any size wafer may be converted to another size wafer as desired.

The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications and publications to provide yet further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.

Claims

1. A device, comprising:

a transparent substrate comprising a first surface, a second surface opposite the first surface, and sidewalls transverse to the first and second surfaces;

a molding compound on the sidewalls of the transparent substrate;

a die on the second surface of the transparent substrate, the die comprising:

a sensor aligned with the transparent substrate;

a contact extending outwardly from an edge of the die and extending away from the sensor; and

an electrical connection having a first end coupled to the sensor and a second end coupled to the contact.

2. The device of claim 1, further comprising:

a first insulating layer on the die and on the contacts of the die;

a conductive layer on the first insulating layer and coupled to the contacts of the die;

a second insulating layer on the first insulating layer, the conductive layer, and the molding compound; and

an opening in the second insulating layer, the opening exposing a portion of the conductive layer.

3. The device of claim 2, wherein the molding compound has a surface that is substantially flush with a surface of the second insulating layer.

4. The device of claim 1, further comprising:

a cavity between the die and the transparent substrate, the cavity adjacent to the sensor of the die; and

a non-conductive layer on the transparent substrate and between the contacts of the die and the transparent substrate.

5. The device of claim 4, wherein a surface of an end of the non-conductive layer is substantially flush with a surface of the molding compound.

6. The device of claim 1, wherein the molding compound is an opaque material.

7. The device of claim 1, wherein:

a central portion of the transparent substrate has a first height;

the sidewalls have a second height that is less than the first height of the central portion of the transparent substrate; and

the die is on the central portion of the transparent substrate.

8. A device, comprising:

a transparent substrate comprising a first surface, a second surface opposite the first surface, and a sidewall transverse to the first surface and the second surface, the sidewall having a first height;

a molding compound on the sidewalls of the transparent substrate, the molding compound having the first height; and

a semiconductor die on the transparent substrate, the semiconductor die including conductive contacts on the transparent substrate, the conductive contacts extending outward from an edge of the semiconductor die.

9. The device of claim 8, wherein the transparent substrate further comprises:

a central portion at a center of the transparent substrate, the central portion having a second height;

a peripheral portion surrounding the central portion, the peripheral portion including the sidewall of the transparent substrate and having the first height, the first height being less than the second height;

a connecting portion surrounding the central portion, the connecting portion connecting the central portion to the peripheral portion.

10. The device of claim 8, wherein the first surface of the transparent substrate further comprises: a surface of the central portion; a surface of the peripheral portion surrounding a surface of the central portion; and a surface of the connecting portion connecting a surface of the peripheral portion to a surface of the central portion.

11. The device of claim 10, wherein a surface of the connection portion of the first surface of the transparent substrate portion is an inclined surface.

12. A method, comprising:

coupling a semiconductor wafer to a transparent wafer;

separating the semiconductor wafer and the transparent wafer to form a plurality of substrate assemblies, each substrate assembly comprising a transparent substrate and a semiconductor die coupled to each other;

coupling the plurality of base assemblies to a carrier support;

forming a molding compound on the plurality of substrate assemblies and the carrier support;

decoupling the carrier support from the plurality of base components and the molding compound; and

forming a plurality of packages by dividing the plurality of substrate assemblies and the molding compound.

13. The method of claim 12, further comprising:

forming a plurality of trenches in the plurality of substrate components and the molding compound;

forming a first insulating layer on the plurality of substrate components, on the molding compound, and in the plurality of trenches;

further extending the plurality of trenches into the plurality of substrate components and into the molding compound, and into the first insulating layer;

forming a conductive layer on the first insulating layer, on the contacts of each of the plurality of substrate assemblies, and in the plurality of trenches; and

a second insulating layer is formed in the trench and on the conductive layer.

14. The method of claim 13, wherein extending the plurality of trenches further comprises: removing portions of electrical contacts of each of the semiconductor dies of the plurality of substrate assemblies.

15. The method of claim 12, wherein the semiconductor wafer and the transparent wafer are 12-inch wafers and the carrier support is an 8-inch glass carrier substrate.

16. The method of claim 15, further comprising forming an 8 inch wafer by forming the mold compound and decoupling the carrier support from the mold compound and the plurality of base assemblies.

17. The method of claim 12, wherein forming the plurality of packages by singulating the plurality of substrate assemblies and the molding compound further comprises: forming a layer of the molding compound on sidewalls of each of the transparent substrates in the plurality of substrate assemblies.

18. The method of claim 12, further extending the plurality of trenches into the plurality of substrate assemblies and into the molding compound further comprising: forming an elevated portion of each of the transparent substrates in the plurality of substrate assemblies.

19. The method of claim 12, further comprising planarizing the mold compound and the plurality of substrate assemblies to form a surface of the mold compound that is flush with a surface of each of the semiconductor dies of the plurality of substrate assemblies.

20. The method of claim 12, wherein:

coupling the plurality of base assemblies to the carrier support further comprises spacing each of the base assemblies apart from each other; and

forming the molding compound includes forming the molding compound between the substrate components.