CN113451151A - Method for manufacturing integrated semiconductor device and integrated semiconductor device - Google Patents
Method for manufacturing integrated semiconductor device and integrated semiconductor device Download PDFInfo
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- CN113451151A CN113451151A CN202110675282.5A CN202110675282A CN113451151A CN 113451151 A CN113451151 A CN 113451151A CN 202110675282 A CN202110675282 A CN 202110675282A CN 113451151 A CN113451151 A CN 113451151A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
Abstract
The invention discloses a preparation method of an integrated semiconductor device and the integrated semiconductor device, comprising the following steps: providing a first substrate, and forming a first non-metal bonding material layer on the surface of the first substrate; providing a second substrate, and forming a device material layer on the surface of the second substrate; forming a second non-metal bonding material layer on the surface of the device material layer; bonding the second non-metal bonding material layer and the first non-metal bonding material layer to form a non-metal bonding layer; removing the second substrate; and carrying out patterned etching on the device material layer to obtain a device layer containing at least one semiconductor device. The invention avoids the problems of electric leakage caused by metal overflow of graphical etching after metal bonding and residual of cleaned metal particles by a nonmetal bonding mode, forms effective etching high selection ratio by the nonmetal bonding mode, increases a process window and improves feasibility.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing an integrated semiconductor device and an integrated semiconductor device.
Background
With the development of miniaturization of LEDs (Light-Emitting diodes), concepts such as Mini and Micro have been proposed. Currently, the light emitting diode with the long side below 400 microns is generally considered to be a Mini LED (submillimeter light emitting diode), and the light emitting diode with the long side below 100 microns and without a substrate is considered to be a Micro-LED (micrometer light emitting diode). The Micro-LED is an LED Micro-and matrixing technique, and the LED backlight is thinned, miniaturized, and arrayed, so that the size of the LED unit can be smaller than 100 micrometers, and each pixel can be addressed independently and driven to emit Light (self-luminescence) independently as in an OLED (Organic Light-Emitting Diode).
The traditional LED chip and the display preparation scheme can be compatible with the Mini LED at present, but the size and the thickness of an LED device in the Micro-LED are both in the micron order, the difference of the LED order of hundreds of microns is larger than that of the traditional LED, and the number of chips involved in use is large, so that the traditional LED preparation method is difficult to use. Taking a mobile phone screen as an example, a mobile phone screen with 1080P resolution has more than 200 thousands (1920 × 1080) of pixels, and each pixel is composed of three subpixels of red, green and blue, that is, a mobile phone screen with 1080P resolution needs more than 600 thousands of LED devices, as for a conventional LED device, one device is transferred every second, so that the time of one year is required for completing the screen, and the cost is extremely high.
Currently, for Micro-LED chips, the mainstream solution includes bulk transfer and monolithic integration. The Mass transfer (Mass transfer) uses Pick-and-place means (Pick and place) similar to the traditional scheme, but is different from one or more means for picking up at one time in the traditional LED preparation scheme, and the Mass transfer picks up a large number of LED chips at one time for transfer; monolithic Integration (Monolithic Integration) refers to a scheme of aligning and bonding metal contacts to a driver after forming a densely arranged LED matrix region or an LED array of a whole wafer, and has higher Integration density.
The two schemes of mass transfer and monolithic integration are respectively aimed at different application scenes. Bulk transfer is mainly aimed at low Pixel density (Pixel Per inc, PPI) and large screen applications, etc., and monolithic integration is mainly aimed at high Pixel density applications, such as Virtual Reality (VR), Augmented Reality (AR), etc.
At present, the schemes for realizing monolithic integration mainly include patterned metal alignment bonding and full-surface metal bonding.
(1) The metal alignment bonding scheme is patterned. The method comprises the steps of carrying out graphical metal coating on the surface of a driving back plate and the whole surface of a wafer used by a photoelectric device, wherein the metal can be a simple substance or an alloy and comprises bonding metals such as gold, gold and tin, welding metal contacts of a driving wafer and a photoelectric wafer by an alignment bonding technology to complete integration of the driving wafer and the photoelectric wafer, and carrying out device processing on the photoelectric wafer side after integration to form a light emitting matrix with N poles. See the literature: wing Cheung Chong, Fang Ou, Qunchao Xu, et al, Low Optical crossbar Micro-LED Micro-Display with Semi-Sphere Micro-Sphere-Lens for Light Collision [ J ].
(2) A full-area metal bonding scheme. The method comprises the steps of carrying out metal film coating on the whole surface of a driving back plate surface and a wafer used by a photoelectric device, wherein the metal can be a simple substance and can be an alloy including bonding metals such as gold, gold and tin, carrying out integration of the driving and the photoelectric wafer through a wafer-level bonding technology, and carrying out device processing on the photoelectric wafer surface after the integration to form a light-emitting matrix with a common N pole. See the literature: lei Zhang, Fan Ou, Wing Cheung Chong, et al. wave Scale Hybrid Monolithic Integration of Si-based IC and III-V envelopes-a Mass Manual applicable Approach for Active Matrix micro-LED Displays [ J ].
In addition, patent documents CN110462850A and TW201724442A also disclose full-area metal bonding and patterned metal alignment bonding schemes.
However, both patterned metal alignment bonding and full-area metal bonding schemes suffer from the following drawbacks.
The disadvantages of the patterned metal alignment bonding scheme are mainly based on the extremely high requirement on the alignment precision, so that the equipment and manufacturing cost is high, the minimum size limit of each alignment module is large due to the problems of metal flowing or alignment deviation and the like in the bonding process, the operation of a single device in the order of tens of microns can be generally carried out, and the high requirement on the density of integrated devices is met.
The whole-surface metal bonding scheme has the main defects that in the patterning work of the bonded bonding metal, the bonding metal relates to various materials, and then a plurality of complex different crystal phases can be formed in the bonding process, which brings great challenges to the patterning, common dry etching equipment cannot meet the etching requirements, and then an electron beam etching scheme is adopted, but the problems of device electric leakage caused by scattered metal particles and incomplete removal easily occur in the metal etching process, and the over-etching is easily caused because the electron beam etching cannot form a good barrier layer and cannot achieve selective etching, and further the over-etching causes damage to drive related devices.
In addition, because both the patterned metal bonding and the entire-surface metal bonding face the etching problem of the bonding metal, a relatively wide etching channel space needs to be reserved to ensure that the metal etching can be performed, which brings adverse effects to the density of the highly integrated device. Taking patent TW201724442A as an example, the device needs to satisfy an aspect ratio close to 1:1 during metal etching due to the thickness of the bonding metal, so that 50% of the width of each pixel needs to be reserved to satisfy the metal etching, and finally, only 50% of the space remains in the real active region.
In addition, the metal bonding process of the graphical metal bonding and the whole-surface metal bonding needs to be performed in a high-temperature environment, and objective factors of differences of thermal expansion coefficients of different material systems cause the problem that the bonded wafer is warped, and the problems of manufacturing difficulty and the like caused by cracking of an effective structure, faults and overlarge warping are easily caused.
Therefore, how to avoid the above disadvantages of patterned metal bonding and full-surface metal bonding becomes a problem to be solved.
Disclosure of Invention
In view of the above, the present invention provides a method for manufacturing an integrated semiconductor device and an integrated semiconductor device, which use a non-metal bonding method to solve the problems of high cost and limited integration density of a patterned metal alignment bonding scheme, leakage and device damage of a full-surface metal bonding scheme, and wafer warpage, structural cracking and fault caused by metal bonding.
The technical scheme of the invention is realized as follows:
a method of fabricating an integrated semiconductor device, comprising:
providing a first substrate, and forming a first non-metal bonding material layer on the surface of the first substrate;
providing a second substrate, and forming a device material layer on the surface of the second substrate;
forming a second non-metal bonding material layer on the surface of the device material layer;
bonding the second non-metal bonding material layer and the first non-metal bonding material layer to form a non-metal bonding layer;
removing the second substrate;
and carrying out patterned etching on the device material layer to obtain a device layer containing at least one semiconductor device.
Further, the semiconductor device is a micron light emitting diode Micro-LED, and the device material layer is made of a Micro-LED material;
the first substrate contains drive integrated circuits therein, and the first substrate surface is formed on a surface of the first substrate that includes metal contacts of the drive integrated circuits.
Further, the method further comprises:
bridging the device layer with the first substrate.
Further, the bridging the device layer and the first substrate includes:
bridging the first poles of all the Micro-LEDs in the device layer with metal contacts in the first substrate.
Further, after bridging the device layer with the first substrate, the method further comprises:
and preparing a common electrode layer on the device layer, wherein the common electrode layer is simultaneously connected with the second poles of all the Micro-LEDs in the device layer.
Further, the method further comprises:
and preparing an optical structure layer on the surface of the substrate containing the device layer.
Further, the optical structure layer comprises a micro lens and/or a micro reflecting cup.
Further, the method further comprises:
and filling a color conversion material in the micro reflecting cup and sealing.
Further, the method further comprises:
and cutting the base body including the first substrate and the device layer to obtain an integrated semiconductor device including a set number of the semiconductor devices.
An integrated semiconductor device comprising:
a first substrate;
the non-metal bonding layer is positioned on the surface of the first substrate;
a device layer on the non-metallic bonding layer, the device layer containing at least one semiconductor device;
wherein:
the nonmetal bonding layer is formed by bonding a first nonmetal bonding material layer formed on the surface of the first substrate and a second nonmetal bonding material layer formed on a device material layer, and the device layer is formed by performing graphical etching on the device material layer.
According to the scheme, the preparation method of the integrated semiconductor device and the integrated semiconductor device avoid the problems of electric leakage caused by metal overflow of patterned etching metal and residual cleaning metal particles after metal bonding in a non-metal bonding mode, form an effective etching high selection ratio in the non-metal bonding mode, increase a process window and improve feasibility.
In addition, the invention reduces the space between devices by a through hole mode, has small size of the through hole, and can realize larger active area or higher integration level under the same size because the nonmetal bonding layer is not required to be completely isolated.
In the invention, through a non-metal bonding mode, the integrated photoelectric representation (such as light transmittance) of a plurality of target wafers is not influenced by bonding metal any more, a plurality of devices which are vertically integrated and distributed can be prepared, and the integration density and the yield of finished products of a larger single device size or a larger device with the same size can be realized in the same area.
In the invention, the contact mode can be freely defined, common-pole or non-common-pole bridging can be freely adopted, and the serial-parallel scheme between devices is more convenient.
In addition, compared with the condition that the metal bonding needs high temperature, the nonmetal bonding in the invention can realize low-temperature bonding to optimize thermal mismatch, and avoid yield and reliability damage caused by the thermal mismatch.
Drawings
FIG. 1 is a flow chart of the steps of a method for fabricating an integrated semiconductor device according to an embodiment of the present invention;
fig. 2A to 2N are schematic views of device structure evolution process structures of the method for manufacturing an integrated semiconductor device according to the embodiment of the present invention;
fig. 3A to fig. 3D are schematic structural diagrams of several bridge connection modes in the embodiment of the present invention.
In the drawings, the names of the components represented by the respective reference numerals are as follows:
101. driving back plate
102. A first non-metallic bonding material layer
103. Metal contact
201. Wafer substrate
202. Micro-LED material layer
2021. Buffer layer
2022. N-type gallium nitride layer
2023. Quantum well layer
2024. P-type gallium nitride layer
2025. Ohmic contact layer
203. Second non-metallic bonding material layer
204. Micro-LED structure
301. Non-metallic bonding layer
401. Bridging layer
402. Common electrode layer
501. Passivation layer
601. Large-luminous-angle structure
602. Small light-emitting angle structure
603. Butterfly-shaped luminous angle structure
604. Micro reflection cup
701. Color conversion material
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and examples.
As shown in fig. 1, an embodiment of the present invention provides a method for manufacturing an integrated semiconductor device, which mainly includes the following steps:
step 1, providing a first substrate, and forming a first nonmetal bonding material layer on the surface of the first substrate;
step 2, providing a second substrate, and forming a device material layer on the surface of the second substrate;
step 3, forming a second non-metal bonding material layer on the surface of the device material layer;
step 4, bonding the second non-metal bonding material layer and the first non-metal bonding material layer to form a non-metal bonding layer;
step 5, removing the second substrate;
and 6, carrying out patterned etching on the device material layer to obtain a device layer containing at least one semiconductor device.
In alternative embodiments, the material of the first substrate may be a first generation semiconductor material (e.g., silicon, germanium, etc.), a second generation semiconductor material (e.g., gallium arsenide, indium phosphide, etc.), a third generation semiconductor material (e.g., gallium nitride, silicon carbide, zinc oxide, diamond, etc.), or a semi-finished product and a finished device, etc.
In alternative embodiments, the material of the first non-metallic bonding material layer may be a single layer or a stacked layer of semiconductor material composed of at least one of silicon oxide, silicon nitride, titanium in oxide state, magnesium oxide, aluminum oxide, gallium nitride, gallium arsenide, and the like.
In alternative embodiments, forming the first non-metallic bonding material layer on the first substrate surface may be performed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering (Sputter), evaporation, or the like.
In an alternative embodiment, the first non-metal bonding material layer may have functions of reflection, heat dissipation, and the like in addition to the bonding function.
In an alternative embodiment, the first non-metallic bonding material layer is formed over an entire surface of the first substrate surface.
In an alternative embodiment, the first non-metallic bonding material layer is patterned.
In alternative embodiments, the material of the second substrate may be a first-generation semiconductor material, a second-generation semiconductor material, a third-generation semiconductor material, or a semi-finished product and a finished device, etc.
In an alternative embodiment, the material of the device material layer comprises a material system from deep ultraviolet to far infrared wavelengths.
In alternative embodiments, the material of the second non-metallic bonding material layer may be a thin film material such as silicon oxide, aluminum oxide, silicon nitride, etc.
In an alternative embodiment, the second non-metallic bonding material layer is formed over the entire surface of the device material layer surface.
In an alternative embodiment, the second non-metallic bonding material layer is patterned.
In an alternative embodiment, the bonding the second non-metal bonding material layer and the first non-metal bonding material layer to form the non-metal bonding layer includes:
and directly bonding the first full-surface formed non-metal bonding material layer and the second full-surface formed non-metal bonding material layer.
In an alternative embodiment, the bonding the second non-metal bonding material layer and the first non-metal bonding material layer to form the non-metal bonding layer includes:
and carrying out alignment bonding on the patterned first non-metal bonding material layer and the patterned second non-metal bonding material layer.
In alternative embodiments, the second substrate may be removed by laser lift-off, chemical liquid removal, or mechanical grinding.
In an alternative embodiment, the device material layer is patterned and etched to obtain a device layer including at least one semiconductor device, which may be implemented by a photolithography and etching method. Wherein, the etching can adopt a dry etching method or a wet etching method.
In alternative embodiments, the semiconductor devices in the device layer may have a cylindrical, trapezoidal, triangular, or other structural shape, and the semiconductor devices in the device layer may be distributed in an orderly manner or in a crossed manner.
In an alternative embodiment, the semiconductor device is a Micro-LED, and the device material layer is made of a Micro-LED material; the first substrate contains a driving integrated circuit therein, and the surface of the first substrate is formed on the surface of the first substrate containing the metal contact of the driving integrated circuit.
In alternative embodiments, the patterned first non-metallic bonding material layer may cover the metal contact of the driving integrated circuit, or may expose the metal contact of the driving integrated circuit without covering the metal contact of the driving integrated circuit.
In an alternative embodiment, the device material layer (Micro-LED material) includes a buffer layer, an N-type layer, a quantum well layer, a P-type layer, and an ohmic contact layer sequentially stacked on the second substrate.
In an alternative embodiment, the N-type layer is N-type gan and the P-type layer is P-type gan.
In alternative embodiments, the buffer layer material may be gallium nitride, aluminum gallium nitride, indium gallium nitride, and other materials and alloys thereof.
In alternative embodiments, the material of the ohmic contact layer may be a metal or a metal oxide. Specifically, the material of the ohmic contact layer includes a metal material such as silver, nickel, gold, aluminum, and the like, and may also include a metal oxide material such as indium tin oxide, zinc oxide, and the like, and the ohmic contact layer may have a single-layer or multi-layer structure.
In alternative embodiments, a reflective material or structure, such as a bragg reflector, may also be disposed between the ohmic contact layer and the second non-metallic bonding material layer.
In alternative embodiments, the ohmic contact layer may be full-surface or patterned.
The preparation of the device material layer can be realized by the prior art, and is not described in detail here.
In alternative embodiments, the driver integrated circuit comprises a TFT thin film transistor and/or LTPS low temperature polysilicon and/or CMOS integrated circuit.
In an alternative embodiment, the method for manufacturing an integrated semiconductor device according to an embodiment of the present invention may further include: and 7, bridging the device layer and the first substrate.
Specifically, in an alternative embodiment, step 7 comprises:
step 71, bridging the first poles of all Micro-LEDs in the device layer with the metal contacts in the first substrate.
In an alternative embodiment, the first electrode of the Micro-LED is a P-pole. In an alternative embodiment, P is a P-type gallium nitride layer in a Micro-LED.
Besides, in other alternative embodiments, step 7 may further include:
step 71', the second poles of all Micro-LEDs in the device layer are bridged with metal contacts in the first substrate.
Wherein the second electrode of the Micro-LED is an N pole. In an alternative embodiment, the N pole is an N-type gallium nitride layer in the Micro-LED.
In alternative embodiments, one or both of steps 71 and 71' may be performed selectively. The following embodiment is performed on the basis of performing step 71 and not performing step 71'.
In an alternative embodiment, after the step 7 of bridging the device layer and the first substrate is completed, the method for manufacturing an integrated semiconductor device according to an embodiment of the present invention further includes:
and 8, preparing a common electrode layer on the device layer, wherein the common electrode layer is simultaneously connected with the second poles of all the Micro-LEDs in the device layer.
Wherein the second electrode of the Micro-LED is an N pole. In an alternative embodiment, the N pole is an N-type gallium nitride layer in the Micro-LED.
After step 8, a common N-pole Micro-LED light emitting matrix is formed.
In an alternative embodiment, after step 8 is completed, the method for manufacturing an integrated semiconductor device according to an embodiment of the present invention further includes:
and 9, preparing an optical structure layer on the surface of the substrate containing the device layer.
In alternative embodiments, the optical structure layer includes microlenses and/or micro-reflective cups.
In alternative embodiments, the material of the microlenses and the micro-reflector cups can be a transparent insulating inorganic or organic material, such as silicon oxide, aluminum oxide, SU8 (a photosensitive silicone type material), polyimide, or the like. The inorganic material can be prepared by a graphical etching process after film coating by adopting a CVD (chemical vapor deposition) method or a Sputter method and the like, and can be prepared by exposure and high-temperature baking.
In an alternative embodiment, if the step 9 is to prepare the micro-reflective cups, after the step 9 is completed, the method for preparing the integrated semiconductor device according to the embodiment of the present invention further includes:
and 10, filling a color conversion material in the micro reflecting cup and sealing.
In alternative embodiments, the color conversion material is a phosphor, quantum dot, or the like.
In an alternative embodiment, after step 10 is completed, the method for manufacturing an integrated semiconductor device according to an embodiment of the present invention further includes:
step 11, cutting the base body including the first substrate and the device layer to obtain an integrated semiconductor device including a set number of semiconductor devices.
The method for manufacturing an integrated semiconductor device according to an embodiment of the present invention is further described below with reference to specific examples of the process for manufacturing a Micro-LED.
Step a1, as shown in fig. 2A, provides a driving back plate (first substrate) 101, and forms a first non-metallic bonding material layer 102 on the surface of the driving back plate 101.
The driving back plate 101 includes a TFT thin film transistor driving circuit, an LTPS low temperature polysilicon driving circuit, or a CMOS integrated circuit driving circuit. A first layer of non-metallic bonding material 102 is formed on one side of the metallic contacts 103 of the driving backplane 101.
The material of the first non-metal bonding material layer 102 may be a single-layer or stacked-layer semiconductor material such as silicon oxide, silicon nitride, titanium oxide, magnesium oxide, aluminum oxide, gallium nitride, gallium arsenide, or the like. The first non-metal bonding material layer 102 may be prepared by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering (Sputter), evaporation, or the like, and besides the bonding function, the first non-metal bonding material layer 102 may also have the capability of reflection, heat dissipation, or the like.
The first non-metal bonding material layer 102 may be the entire surface as shown in fig. 2A, or may be patterned, and if the first non-metal bonding material layer 102 is patterned, the patterned first non-metal bonding material layer 102 may cover the metal contact 103, or may expose the metal contact 103.
Step a2, as shown in fig. 2B, provides a wafer substrate (second substrate) 201, and forms a Micro-LED material layer 202 on the surface of the wafer substrate 201.
Wherein the material of the wafer substrate 201 is, for example, sapphire or silicon carbide.
The Micro-LED material layer 202 includes a buffer layer 2021, an N-type gallium nitride layer 2022, a quantum well layer 2023, a P-type gallium nitride layer 2024, and an ohmic contact layer 2025 sequentially stacked on the wafer substrate 201.
Step a3, as shown in FIG. 2C, a second non-metallic bonding material layer 203 is formed on the surface of the Micro-LED material layer 202.
The second nonmetal bonding material layer 203 may be a thin film material such as silicon oxide, aluminum oxide, or silicon nitride. The material of the second non-metallic bonding material layer 203 corresponds to the material of the first non-metallic bonding material layer 102.
There may be a reflective material or structure, such as a bragg reflector, between the ohmic contact layer 2025 and the second non-metallic bonding material layer 203.
The second non-metal bonding material layer 203 may be a whole surface as shown in fig. 2C, or may be patterned.
Step a4, bonding the second non-metal bonding material layer 203 and the first non-metal bonding material layer 102 to form a non-metal bonding layer 301, as shown in fig. 2D.
Wherein, the first non-metal bonding material layer 102 and/or the second non-metal bonding material layer 203 are formed on the whole surface, and the second non-metal bonding material layer 203 and the first non-metal bonding material layer 102 are directly bonded; for both the first non-metallic bonding material layer 102 and the second non-metallic bonding material layer 203 to be patterned, an alignment bonding is required to ensure that the metal contact 103 falls within a desired range.
Step a5, the wafer substrate 201 is removed, as shown in fig. 2E.
This step employs a corresponding process depending on the wafer substrate 201 material. For example, the sapphire material can be removed by laser lift-off, and if the sapphire material is a silicon substrate, a silicon carbide substrate, a gallium nitride substrate or a gallium arsenide substrate, the sapphire material can be removed by chemical liquid or grinding.
The mode of the embodiment of the invention can also realize the overlapping bonding of the multilayer Micro-LED material layers 202. For example, after the wafer substrate 201 is removed, a first non-metal bonding material layer is prepared on the Micro-LED material layer 202, another Micro-LED material layer and a second non-metal bonding material layer are prepared on the surface of another wafer substrate 201, and the second non-metal bonding material layer is bonded with the first non-metal bonding material layer, so that stacking of two Micro-LED material layers is realized, and the stacking and bonding of multiple Micro-LED material layers can be realized by repeatedly adopting the method.
Step a6, device structure preparation is carried out, as shown in fig. 2F.
In this step, the Micro-LED material layer 202 is patterned etched to obtain a device layer containing at least one Micro-LED structure 204.
In this step, the buffer layer 2021 and other sacrificial layer structures are removed by dry etching or wet etching to expose the ohmic contact layer 2025 and the N-type gallium nitride layer 2022, and the Micro-LED structure 204 may be in the shape of a cylinder, a trapezoid, a triangle, or other common structures, and may be distributed in order or in a cross arrangement.
Step a7, bridging the P-type gallium nitride layer 2024 of all Micro-LED structures 204 in the device layer with the metal contact 103 in the first substrate 101, as shown in fig. 2G.
In this step, the bridging manner is determined according to the requirement, and fig. 2G illustrates a bridging manner between the Micro-LED structure 204 and the metal contact 103. Fig. 3A, 3B, and 3C respectively show another bridging method, in which fig. 3A illustrates a method of bridging the N-type gallium nitride layer 2022 and the metal contact 103, fig. 3B illustrates a method of bridging one side of the G-type gallium nitride layer 2024 and the metal contact 103, and fig. 3C illustrates a method of bridging the G-type gallium nitride layer 2024 and the N-type gallium nitride layer 2022 with different metal contacts 103. Additionally, as shown in FIG. 3D, the metal contact 103 may also be on one side of the semiconductor device (e.g., Micro-LED structure 204).
Before bridging, insulation protection can be carried out, and the insulation protection can fill the space of the Micro-LED structure 204 or only wrap the surface of the Micro-LED structure 204. Optionally, during the bridging process, the non-metal bonding layer 301 is etched in the shape of the Micro-LED structure 204 itself, or a hole is dug in the non-metal bonding layer 301 to the metal contact 103 below, the position, size, number, and shape of the dug through hole depend on the space of the Micro-LED structure 204, the bridging scheme may be a single electrode (as shown in fig. 2G, 3A, and 3B) or a multiple electrode (as shown in fig. 3C), the bridging position may be any available through hole region, the material of the bridging layer 401 may be a metal, such as one or a stack of aluminum, titanium nitride, chromium, platinum, gold, or a metal oxide, such as indium tin oxide, zinc oxide, or a conductive material.
Step a8, preparing the common electrode layer 402, as shown in fig. 2H, fig. 2I, fig. 2J.
This step can be skipped for the structure with both P and N poles bridged (shown in FIG. 3C). In this step, a passivation layer 501 may be covered and planarized (fig. 2H) or a passivation layer 501 may be covered (fig. 2I and 2J), and the passivation layer 501 may be an inorganic material such as silicon oxide, silicon nitride, or aluminum oxide, or an organic material such as polyimide or SU 8. After the passivation layer 501 is insulated, the common electrode layer 402 is prepared, and the common electrode layer 402 may be a single-layer structure or a stacked structure of a metal or a metal oxide, such as nickel, gold, zinc, chromium, aluminum, titanium, or a single or multiple metal capable of forming an ohmic contact, or a transparent conductive film of indium tin oxide, zinc oxide, or a mixture of metal and metal oxide.
Step a9, preparing an optical structure layer as shown in fig. 2K, fig. 2L and fig. 2M.
The optical structure layer includes a micro lens, the micro lens includes a large light-emitting angle structure 601, a small light-emitting angle structure 602, a butterfly light-emitting angle structure 603, and the optical structure layer further includes a micro reflector cup 604.
The material of the micro lens and the micro reflector can be inorganic material, such as transparent insulating material of silicon oxide, aluminum oxide and the like, and can be prepared by patterned etching after being coated by CVD or Sputter and the like, or organic material, such as transparent insulating material of SU8, polyimide and the like, and can be prepared by exposure and high-temperature baking.
Step a10, colorizing and preparing the device by separation.
In this case, as shown in fig. 2N, the coloring process is to fill the micro-reflective cup 604 with a color conversion material 701. In an alternative embodiment, after the three neighboring Micro-LED structures 204 are filled with the red, green, and blue color conversion materials 701, the three neighboring Micro-LED structures 204 may form a pixel together. The color conversion material 701 is, for example, a phosphor, a quantum dot, or the like. After the color conversion material 701 is filled, a thin film deposition sealing or a micro lens sealing is performed. For different applications, cutting selection can be performed to prepare discrete devices with single or multiple pixels or display screens with certain resolution.
The colorization scheme can also be formed by bonding Micro-LED material wafers of different colors for multiple times, and the related processes from step a1 to step a5 are repeated after step a5 is completed, so that the multi-layer material wafers (such as red-green-blue three-color gallium arsenide system Micro-LED wafer, green-green gallium nitride system Micro-LED wafer, and blue-light gallium nitride system Micro-LED wafer) forming the Micro-LEDs are integrated, and the bonding film selected by each bonding can be selected according to the wafer material system to be bonded, for example, the material of the sapphire substrate can be aluminum oxide-aluminum oxide or silicon oxide-silicon oxide bonding, the material of the gallium arsenide substrate can be gallium arsenide-bonding, and the bonding material and the wafer can include an ohmic contact layer and a required optical reflection or filtering layer, the bonding sequence is operated according to actual requirements, such as photoelectric type devices, the forbidden band widths of the semiconductor materials are reduced from top to bottom in sequence, and optimal light extraction can be realized. After integration, the operation is started from step a6, the patterning is performed one by one, after the completion, bridging is performed according to the scheme of step a7, whether the common polarity and the common polarity are selected freely can be selected, the final integration scheme is completed, the integration bridging can occur between a driver and a wafer device and between the wafer device and the device, and a proper serial-parallel connection scheme and a proper through hole scheme can be selected.
The embodiments of the method for manufacturing an integrated semiconductor device according to the embodiments of the present invention can also be used for the integration of other types of semiconductor devices.
The embodiment of the invention also provides an integrated semiconductor device which comprises a first substrate, a non-metal bonding layer and a device layer. Wherein, the non-metal bonding layer is positioned on the surface of the first substrate. The device layer is located on the non-metallic bonding layer, and the device layer contains at least one semiconductor device. The nonmetal bonding layer is formed by bonding a first nonmetal bonding material layer formed on the surface of the first substrate and a second nonmetal bonding material layer formed on a device material layer, and the device layer is formed by patterning and etching the device material layer.
According to the preparation method of the integrated semiconductor device and the integrated semiconductor device, disclosed by the embodiment of the invention, the problems of metal overflow caused by graphical etching after metal bonding and electric leakage caused by cleaning of metal particle residues are solved through a non-metal bonding mode, an effective etching high selection ratio is formed through the non-metal bonding mode, a process window is increased, and the feasibility is improved. In addition, in the embodiment of the invention, the device space is reduced by a through hole mode, the size of the through hole is small, and simultaneously, as the nonmetal bonding layer is not required to be completely isolated, the larger active area or the higher integration level under the same size can be realized.
In the embodiment of the invention, through a non-metal bonding mode, the integrated photoelectric performance (such as light transmittance) of a plurality of target wafers is not influenced by bonding metal any more, a plurality of devices which are vertically integrated and distributed can be prepared, and the integration density and the yield of finished products of more devices with larger single device size or the same size can be realized in the same area.
In the embodiment of the invention, the contact mode can be freely defined, common-pole or non-common-pole bridging can be freely adopted, and the serial-parallel scheme between devices is more convenient.
In addition, compared with the condition that the metal bonding needs high temperature, the nonmetal bonding in the embodiment of the invention can realize low-temperature bonding to optimize thermal mismatch, and avoid yield and reliability damage caused by the thermal mismatch.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of fabricating an integrated semiconductor device, comprising:
providing a first substrate, and forming a first non-metal bonding material layer on the surface of the first substrate;
providing a second substrate, and forming a device material layer on the surface of the second substrate;
forming a second non-metal bonding material layer on the surface of the device material layer;
bonding the second non-metal bonding material layer and the first non-metal bonding material layer to form a non-metal bonding layer;
removing the second substrate;
and carrying out patterned etching on the device material layer to obtain a device layer containing at least one semiconductor device.
2. The method of manufacturing an integrated semiconductor device according to claim 1, wherein:
the semiconductor device is a micron light emitting diode Micro-LED, and the device material layer is made of a Micro-LED material;
the first substrate contains drive integrated circuits therein, and the first substrate surface is formed on a surface of the first substrate that includes metal contacts of the drive integrated circuits.
3. The method of manufacturing an integrated semiconductor device according to claim 2, further comprising:
bridging the device layer with the first substrate.
4. The method of claim 3, wherein bridging the device layer to the first substrate comprises:
bridging the first poles of all the Micro-LEDs in the device layer with metal contacts in the first substrate.
5. The method of claim 4, wherein after bridging the device layer with the first substrate, the method further comprises:
and preparing a common electrode layer on the device layer, wherein the common electrode layer is simultaneously connected with the second poles of all the Micro-LEDs in the device layer.
6. The method of manufacturing an integrated semiconductor device according to claim 5, further comprising:
and preparing an optical structure layer on the surface of the substrate containing the device layer.
7. The method of manufacturing an integrated semiconductor device according to claim 6, wherein:
the optical structure layer comprises a micro lens and/or a micro reflecting cup.
8. The method of manufacturing an integrated semiconductor device according to claim 7, further comprising:
and filling a color conversion material in the micro reflecting cup and sealing.
9. The method for manufacturing an integrated semiconductor device according to any one of claims 1 to 8, further comprising:
and cutting the base body including the first substrate and the device layer to obtain an integrated semiconductor device including a set number of the semiconductor devices.
10. An integrated semiconductor device, comprising:
a first substrate;
the non-metal bonding layer is positioned on the surface of the first substrate;
a device layer on the non-metallic bonding layer, the device layer containing at least one semiconductor device;
wherein:
the nonmetal bonding layer is formed by bonding a first nonmetal bonding material layer formed on the surface of the first substrate and a second nonmetal bonding material layer formed on a device material layer, and the device layer is formed by performing graphical etching on the device material layer.
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| CN202110675282.5A CN113451151A (en) | 2021-06-18 | 2021-06-18 | Method for manufacturing integrated semiconductor device and integrated semiconductor device |
| CN202111519890.3A CN114171394A (en) | 2021-06-18 | 2021-12-13 | Method for manufacturing semiconductor device and semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114628432A (en) * | 2022-02-28 | 2022-06-14 | 诺视科技(苏州)有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN114725149A (en) * | 2022-03-02 | 2022-07-08 | 湖南大学 | micro-LED display matrix preparation method and micro-LED display matrix |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114628432A (en) * | 2022-02-28 | 2022-06-14 | 诺视科技(苏州)有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN114628432B (en) * | 2022-02-28 | 2023-03-10 | 诺视科技(苏州)有限公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN114725149A (en) * | 2022-03-02 | 2022-07-08 | 湖南大学 | micro-LED display matrix preparation method and micro-LED display matrix |
| CN114725149B (en) * | 2022-03-02 | 2023-10-27 | 湖南大学 | micro-LED display matrix preparation method and micro-LED display matrix |
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