CN113451137A - Transistor manufacturing method, device, computer-readable storage medium, and program product - Google Patents
Transistor manufacturing method, device, computer-readable storage medium, and program product Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Abstract
The invention discloses a transistor manufacturing method, which comprises the following steps: after a field oxide layer is thermally grown on an epitaxial wafer, conducting doping impurity injection is carried out for multiple times to form a pressure-bearing ring PN junction, a source region PN junction and a stop region PN junction, wherein the source region PN junction is partially overlapped with the pressure-bearing ring PN junction; depositing a doped oxide layer PSG on the surface of the field oxide layer, and forming a source region contact hole and a stop region contact hole in the doped oxide layer PSG; and depositing metal layers on the doped oxide layer PSG, the source region contact hole and the stop region contact hole, and removing the invalid metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole. The invention also discloses a transistor manufacturing apparatus, a computer-readable storage medium, and a program product. According to the invention, conductive doping impurities are injected for multiple times, a pressure ring PN junction, a source region PN junction and a cut-off region PN junction with good conductivity are formed on the epitaxial wafer, and the pressure ring PN junction is partially overlapped with the source region PN junction, so that the high-temperature characteristic of the transistor is stable, and the high-temperature electric leakage is small.
Description
Technical Field
The present invention relates to the field of transistor technology, and more particularly, to a method for manufacturing a transistor, a device computer readable storage medium, and a program product.
Background
With the development of science and technology, the application of electronic technology almost permeates the aspects of production and life of people. Transistor transistors (abbreviated as transistors) are a most basic common device in electronic technology, and their applications are very wide, for example, an amplifier is a basic application of a transistor.
In practical applications, the structure of the transistor is very important, and a good transistor structure is the first design guarantee and is the basic requirement of all conventional parameters. However, the termination structure of any transistor is very complicated in design, such as a field plate structure, which requires multiple steps (multiple steps are used to keep the electric field under the field plate uniformly distributed), and also requires length (too long or too short field plate length affects the back pressure); the structure of the pressure dividing ring requires the limitation on parameters such as ring width, ring spacing (reasonable and effective ring spacing has decisive influence on back pressure) and the like, and the back pressure is very sensitive to design dimensions such as the ring spacing and the like; the junction terminal expansion structure requires specific requirements on the injection dosage and the junction depth of the terminal ring, and once the junction depth or the injection dosage fluctuates, serious influences such as back pressure reduction or back pressure leakage and the like can occur; the VLD terminal variable doping terminal structure has strict limiting requirements on parameters such as variable doping injection window size, terminal junction and main junction spacing, injection dosage and the like, and adverse effects such as back pressure reduction or back pressure electric leakage and the like can occur when the design or process data are changed as in a junction terminal expansion terminal; the above several types of terminals have strict limits on design size or process parameters and have smaller fluctuation range requirements, but all the design size or process fluctuation can cause serious reduction of the back pressure parameters or extremely increased back pressure leakage formation indexes to cause product failure.
Therefore, how to manufacture a transistor with a reasonable design size is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The main objective of the present invention is to provide a method, an apparatus, a computer readable storage medium and a program product for manufacturing a transistor, which are capable of manufacturing a transistor with a reasonable structure to ensure the qualification of the transistor product.
In order to achieve the above object, the present invention provides a transistor manufacturing method, including the steps of:
after a field oxide layer is thermally grown on an epitaxial wafer, determining a first position of a doping window for injecting a pressure-bearing ring in the field oxide layer, and injecting first conductive doping impurities based on the first position to form a pressure-bearing ring PN junction;
determining a second position of a source region injection window and a third position of a stop region injection window in the field oxide layer, and injecting first conductive doping impurities and second conductive doping impurities based on the second position and the third position to form a source region PN junction and a stop region PN junction, wherein the source region PN junction is partially overlapped with the pressure-bearing ring PN junction;
depositing a doped oxide layer PSG on the surface of the field oxide layer, determining a fourth position of a source region contact hole and a fifth position of a stop region contact hole in the doped oxide layer PSG, and forming a source region contact hole and a stop region contact hole based on the fourth position and the fifth position;
and depositing metal layers on the doped oxide layer PSG, the source region contact hole and the stop region contact hole, and removing the invalid metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole.
Preferably, after the field oxide layer is thermally grown on the epitaxial wafer, the field oxide layer determines a first position where the bearing ring is implanted into the doping window, and based on the first position, the step of implanting a first conductive doping impurity to form a bearing ring PN junction includes:
after a field oxide layer is thermally grown on an epitaxial wafer, photoresist with a preset thickness is coated on the field oxide layer, and exposure and development are carried out based on a first preset mask so as to determine a first position of a doping window injected into a pressure-bearing ring;
etching the oxide layer corresponding to the injection doping window of the pressure-bearing ring based on the first position, and removing the photoresist;
and injecting first conductive doping impurities into the pressure-bearing ring injection doping window to form a pressure-bearing ring PN junction.
Preferably, the step of implanting a first conductive dopant impurity into the bearing ring implantation doping window to form a bearing ring PN junction includes:
injecting a first conductive doping impurity into the doping window of the pressure-bearing ring, and performing high-temperature diffusion on the first conductive doping impurity based on a preset temperature and a preset time;
and thermally growing a first shielding oxide layer with a preset thickness on the injection window of the pressure-bearing ring to form a PN junction of the pressure-bearing ring.
Preferably, the step of determining the second position of the source region injection window and the third position of the stop region injection window in the field oxide layer, and implanting the first conductive doping impurity and the second conductive doping impurity based on the second position and the third position to form a source region PN junction and a stop region PN junction, wherein the source region PN junction and the bearing ring PN junction partially overlap includes:
coating photoresist with a preset thickness on the field oxide layer, and carrying out exposure and development based on a second preset mask to determine a second position of the source region injection window and a third position of the stop region injection window;
based on the second position and the third position, corroding an oxide layer corresponding to the source region injection window and an oxide layer corresponding to the stop region injection window, and thermally growing a second shielding oxide layer and a third shielding oxide layer with preset thicknesses on the source region injection window and the stop region injection window respectively;
and removing the photoresist, and respectively injecting a first conductive doping impurity and a second conductive doping impurity into the source region injection window and the cut-off region injection window to form a source region PN junction and a cut-off region PN junction.
Preferably, the step of implanting the first conductive dopant impurity and the second conductive dopant impurity into the source region implantation window and the stop region implantation window, respectively, to form a source region PN junction and a stop region PN junction includes:
respectively injecting second conductive doping impurities into the source region injection window and the stop region injection window, and diffusing the second conductive doping impurities to a preset doping peak depth based on a preset temperature and a preset time;
and respectively injecting first conductive doping impurities into the source region injection window and the cut-off region injection window, and performing high-temperature diffusion on the first conductive doping impurities based on preset temperature and preset time to form a source region PN junction and a cut-off region PN junction.
Preferably, the step of depositing a doped oxide layer PSG on the surface of the field oxide layer, determining a fourth position of a source region contact hole and a fifth position of a stop region contact hole in the doped oxide layer PSG, and opening the source region contact hole and the stop region contact hole based on the fourth position and the fifth position includes:
depositing a doped oxide layer PSG on the surface of the field oxide layer, and carrying out densification treatment on the doped oxide layer PSG in an oxygen atmosphere based on a preset temperature and preset time;
coating photoresist with a preset thickness on the doped oxide layer PSG, and carrying out exposure and development based on a third preset mask to determine a fourth position of a source region contact hole and a fifth position of a stop region contact hole;
and respectively etching to form a source region contact hole and a stop region contact hole based on the fourth position and the fifth position, and removing the photoresist.
Preferably, the step of depositing a metal layer on the doped oxide layer PSG, the source region contact hole and the stop region contact hole, and removing an invalid metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole includes:
depositing a metal layer on the doped oxide layer PSG, the source region contact hole and the cut-off region contact hole, and coating photoresist with a preset thickness on the metal layer;
exposing and developing based on a fourth preset mask to determine an invalid region between a source electrode corresponding to the source region contact hole and a field plate corresponding to the cut-off region contact hole;
and corroding the invalid metal layer corresponding to the invalid region, and removing the photoresist.
Further, to achieve the above object, the present invention also provides a transistor manufacturing apparatus including: a memory for storing executable instructions, a processor, and a transistor manufacturing program stored on the memory and executable on the processor, the transistor manufacturing program, when executed by the processor, implementing the steps of the transistor manufacturing method as described above.
Further, to achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a transistor manufacturing program which, when executed by a processor, realizes the steps of the transistor manufacturing method as described above.
Furthermore, to achieve the above object, the present invention also provides a computer program product comprising a computer program which, when being executed by a processor, realizes the steps of the transistor manufacturing method as described above.
The manufacturing method of the transistor comprises the steps that after a field oxide layer is thermally grown on an epitaxial wafer, a first position of a doping window of a pressure-bearing ring is determined on the field oxide layer, and first conductive doping impurities are injected on the basis of the first position to form a pressure-bearing ring PN junction; determining a second position of a source region injection window and a third position of a stop region injection window in the field oxide layer, and injecting first conductive doping impurities and second conductive doping impurities based on the second position and the third position to form a source region PN junction and a stop region PN junction, wherein the source region PN junction is partially overlapped with the pressure-bearing ring PN junction; depositing a doped oxide layer PSG on the surface of the field oxide layer, determining a fourth position of a source region contact hole and a fifth position of a stop region contact hole in the doped oxide layer PSG, and forming a source region contact hole and a stop region contact hole based on the fourth position and the fifth position; and depositing metal layers on the doped oxide layer PSG, the source region contact hole and the stop region contact hole, and removing the invalid metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole. Compared with the prior art, the transistor manufactured by the method has simple and clear structural design, larger size range and contribution to wide popularization, and meanwhile, as the PN junction of the source region is partially overlapped with the PN junction of the pressure-bearing ring, the high-temperature characteristic of the transistor terminal structure is more stable than that of other terminal structures, the high-temperature leakage is smaller, and the high-temperature application reliability and safety are better.
Drawings
FIG. 1 is a schematic diagram of an apparatus architecture of a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart illustrating a method of fabricating a transistor according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an embodiment of a method for fabricating a transistor according to the present invention with an opened implantation window and implantation doping;
FIG. 4 is a schematic diagram of an embodiment of a method for manufacturing a transistor according to the present invention, in which a doped impurity is injected into an injection window of a pressure ring and then is subjected to high temperature diffusion oxidation and then is coated with a photoresist;
FIG. 5 is a schematic diagram of a JFET with dopant diffusion implanted therein according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a transistor with a P-body junction formed according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a transistor formed according to an embodiment of the method for manufacturing a transistor of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, fig. 1 is a schematic device structure diagram of a hardware operating environment according to an embodiment of the present invention.
The equipment of the embodiment of the invention can be PC or server equipment and is used for controlling the process equipment of each station on a production line.
As shown in fig. 1, the apparatus may include: a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, a communication bus 1002. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a DisplAy screen (DisplAy), an input unit such as a KeyboArd (KeyboArd), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface). The memory 1005 may be a high-speed RAM memory or a non-volAtile attached memory (non-volAtile memory), such as a disk memory. The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the configuration of the apparatus shown in fig. 1 is not intended to be limiting of the apparatus and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 1, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and a transistor manufacturing program.
The operating system is a program for managing and controlling the transistor manufacturing equipment and software resources, and supports the running of a network communication module, a user interface module, a transistor manufacturing program and other programs or software; the network communication module is used for managing and controlling the network interface 1002; the user interface module is used to manage and control the user interface 1003.
In the transistor manufacturing apparatus shown in fig. 1, the transistor manufacturing apparatus calls a transistor manufacturing program stored in a memory 1005 by a processor 1001 and performs operations in various embodiments of a transistor manufacturing method described below.
Based on the above hardware structure, embodiments of the transistor manufacturing method of the present invention are provided.
Referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of a method for manufacturing a transistor according to the present invention, the method comprising:
step S10, after a field oxide layer is thermally grown on an epitaxial wafer, determining a first position of a doping window for injecting a bearing ring in the field oxide layer, and injecting a first conductive doping impurity based on the first position to form a bearing ring PN junction;
step S20, determining a second position of a source region injection window and a third position of a stop region injection window in the field oxide layer, and performing injection of a first conductive doping impurity and a second conductive doping impurity based on the second position and the third position to form a source region PN junction and a stop region PN junction, where the source region PN junction and the pressure ring PN junction are partially overlapped;
step S30, depositing a doped oxide layer PSG on the surface of the field oxide layer, determining a fourth position of a source region contact hole and a fifth position of a stop region contact hole in the doped oxide layer PSG, and forming a source region contact hole and a stop region contact hole based on the fourth position and the fifth position;
step S40, depositing a metal layer on the doped oxide layer PSG, the source region contact hole and the stop region contact hole, and removing an invalid metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole.
It should be explained that the transistor manufacturing method of the present embodiment can be selectively applied to the process flow of the semi-automatic production line, and can also be applied to the process flow of the full-automatic production line.
The transistor can be the novel transistor of high-pressure MOSFET, and is specific, the novel transistor of MOSFET includes an N + + substrate and sets up the N-epitaxial layer at the internal surface of N + + substrate, and wherein, still be provided with P-junction region between P-junction region and N + junction region, and the by-spacing of P-junction region and N + junction region sets up 35um-40um, and the size of P-junction region sets up 68um-70um, and the junction depth of P-junction region sets up 7um-8 um.
This embodiment is directed to the fabrication of the above-described MOSFET novel transistor.
The respective steps will be described in detail below:
step S10, after a field oxide layer is thermally grown on the epitaxial wafer, determining a first position of a doping window of the bearing ring in the field oxide layer, and injecting a first conductive doping impurity based on the first position to form a PN junction of the bearing ring.
In this embodiment, first, thermal growth is performed on an epitaxial wafer
I.e., field oxide layer, wherein the epitaxial wafer includes a semiconductor substrate, e.g., a N + + Sub substrate, and a conductive epitaxial layer, e.g., a N-Epi epitaxial layer.
After a field oxide layer is thermally grown on an epitaxial wafer, a first position of a doping window for injecting a pressure-bearing ring is determined on the field oxide layer, and first conductive doping impurities are injected through the first position, namely the first conductive doping impurities are injected into the injection window of the pressure-bearing ring, so that a pressure-bearing ring PN junction is formed on the epitaxial wafer.
Specifically, step S10 includes:
step a, after a field oxide layer is thermally grown on an epitaxial wafer, photoresist with a preset thickness is coated on the thermal oxide layer, and exposure and development are carried out based on a first preset mask so as to determine a first position of a doping window injected by a pressure-bearing ring;
in one embodiment, after thermally growing a field oxide layer on an epitaxial wafer, a photoresist with a predetermined thickness is coated on the field oxide layer, wherein the predetermined thickness is selected as
The photoresist is also called a barrier photoresist and can be selected as a positive photoresist.
And then, carrying out exposure and development through a first preset mask so as to determine a first position of the pressure-bearing ring for injecting the doping window.
B, corroding the oxide layer corresponding to the injection doping window of the pressure-bearing ring based on the first position, and removing the photoresist;
next, the corresponding oxide layer is etched clean by wet etching, as shown in fig. 3, and then the photoresist is removed.
And c, injecting first conductive doping impurities into the pressure-bearing ring injection doping window to form a pressure-bearing ring PN junction.
And then, injecting first conductive doping impurities into the pressure-bearing ring injection window through special semiconductor injection doping equipment to form a pressure-bearing ring PN junction with negative electricity, namely injecting P-doped PN junction into the terminal pressure-bearing ring.
In one embodiment, step c comprises:
step c1, injecting a first conductive doping impurity into the injection doping window of the pressure-bearing ring, and performing high-temperature diffusion on the first conductive doping impurity based on a preset temperature and a preset time;
in one embodiment, the first conductive doping impurities are injected into the injection doping window of the pressure-bearing ring, and the first conductive doping impurities on the epitaxial wafer are diffused at a preset temperature and a preset time at a high temperature through the special diffusion furnace tube, wherein the preset temperature is 1100-.
And c2, thermally growing a first shielding oxide layer with a preset thickness on the injection window of the pressure-bearing ring to form a PN junction of the pressure-bearing ring.
Then thermally growing the thickness of the injection window in the pressure bearing ring to be
The shielding oxide layer is used for improving the groove wall of the injection window of the pressure-bearing ring and preventing continuous diffusion, so that a PN junction of the pressure-bearing ring is formed, and the depth of the PN junction of the pressure-bearing ring is 7-8 um in specific implementation.
Step S20, determining a second position of the source region injection window and a third position of the stop region injection window in the field oxide layer, and based on the second position and the third position, performing injection of the first conductive doping impurity and the second conductive doping impurity to form a source region PN junction and a stop region PN junction, wherein the source region PN junction overlaps with the pressure ring PN junction.
In this embodiment, the third position of the source region implantation window and the third position of the stop region implantation window are continuously determined on the field oxide layer, and the implantation of the conductive doping impurities is performed at the second position and the third position, specifically, the first conductive doping impurities and the second conductive doping impurities are implanted, so as to form a source region PN junction and a stop region PN junction, wherein the source region PN junction and the pressure ring PN junction are partially overlapped.
Specifically, step S20 includes:
step d, coating photoresist with a preset thickness on the field oxide layer, and carrying out exposure and development based on a second preset mask to determine a second position of the source region injection window and a third position of the stop region injection window;
in one embodiment, the first layer is coated on top of the field oxide layer
And exposing and developing the positive photoresist through a second preset mask to determine respective positions of the source region injection window and the stop region injection window, as shown in fig. 4.
E, based on the second position and the third position, corroding an oxide layer corresponding to the source region injection window and an oxide layer corresponding to the stop region injection window, and thermally growing a second shielding oxide layer and a third shielding oxide layer with preset thicknesses on the source region injection window and the stop region injection window respectively;
and then, completely etching the oxide layers of the source region injection window and the stop region injection window by wet etching, and respectively thermally growing a second shielding oxide layer and a third fatigue oxide layer with preset thicknesses on the source region injection window and the stop region injection window at preset temperature and preset time by a special diffusion furnace tube, wherein the preset thicknesses are
F, removing the photoresist, and respectively injecting a first conductive doping impurity and a second conductive doping impurity into the source region injection window and the stop region injection window to form a source region PN junction and a stop region PN junction, wherein the source region PN junction is partially overlapped with the pressure-bearing ring PN junction;
and then, photoresist is made clear, and first conductive doping impurities and second conductive doping impurities are injected into the source region injection window and the stop region injection window through semiconductor special injection doping equipment, so that a source region PN junction and a stop region PN junction are formed, wherein the source region PN junction is partially overlapped with the pressure-bearing ring PN junction.
In one embodiment, step f comprises:
step f1, injecting second conductive doping impurities into the source region injection window and the cut-off region injection window respectively, and diffusing the second conductive doping impurities to a preset doping peak depth based on a preset temperature and a preset time;
in an embodiment, a second conductive doping impurity is implanted into the source region implantation window and the stop region implantation window respectively through a semiconductor special implantation doping device to form a JFET implantation layer for improving the on-resistance of the source region and an N-stop ring of the stop region, and then the second conductive doping impurity is diffused to a preset doping peak depth through a diffusion special furnace tube at a preset temperature and a preset time, wherein the preset temperature is 1100-.
And f2, respectively injecting first conductive doping impurities into the source region injection window and the stop region injection window, and performing high-temperature diffusion on the first conductive doping impurities based on preset temperature and preset time to form a source region PN junction and a stop region PN junction.
And then respectively injecting first conductive doping impurities into the source region injection window and the stop region injection window, and performing high-temperature diffusion at a preset temperature and a preset time through a special diffusion furnace tube to form a source region PN junction and a stop region PN junction, wherein the preset temperature is 1100-.
Step S30, depositing a doped oxide layer PSG on the surface of the field oxide layer, determining a fourth position of a source region contact hole and a fifth position of a stop region contact hole in the doped oxide layer PSG, and opening a source region contact hole and a stop region contact hole based on the fourth position and the fifth position.
In this embodiment, a doped oxide layer PSGS is deposited on the surface of the field oxide layer by a semiconductor-dedicated device for depositing a doped oxide layer, and the opening positions of the source region contact hole and the stop region contact hole, that is, the fourth position and the fifth position, are determined on the doped oxide layer PSGS, so as to open the source region contact hole and the stop region contact hole.
Specifically, step S30 includes:
step g, depositing a doped oxide layer PSG on the surface of the field oxide layer, and carrying out densification treatment on the doped oxide layer PSG in an oxygen atmosphere based on a preset temperature and preset time;
in one embodiment, a doped oxide layer PSG is deposited on the surface of an oxide layer through a semiconductor special doped oxide layer deposition device, and the PSG is densified in an oxygen atmosphere at a preset temperature for a preset time;
h, coating photoresist with a preset thickness on the doped oxide layer PSG, and carrying out exposure and development based on a third preset mask to determine a fourth position of a contact hole of the source region and a fifth position of a contact hole of the cut-off region;
then, coating the doped oxide layer PSG
And exposing and developing the fourth position and the fifth position of the contact holes of the source region and the cut-off region based on a third preset mask.
I, respectively corroding and forming a source region contact hole and a stop region contact hole based on the fourth position and the fifth position, and removing the photoresist
Then, a metal contact hole is formed by wet etching and dry etching, and the positive photoresist is removed.
Step S40, depositing a metal layer on the doped oxide layer PSG, the source region contact hole and the stop region contact hole, and removing an invalid metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole.
In this embodiment, a metal layer with a preset thickness is deposited on the epitaxial layer by using a metal deposition device special for a semiconductor, the oxide layer PSG is doped on the epitaxial layer, and the source region contact hole and the stop region contact hole are deposited, and the invalid metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole is removed, so that the qualified transistor is obtained.
Specifically, step S40 includes:
j, depositing a metal layer on the doped oxide layer PSG, the source region contact hole and the cut-off region contact hole, and coating photoresist with a preset thickness on the metal layer;
in one embodiment, a metal layer, preferably a metal aluminum layer,the thickness is 24-30um, and then coating is carried out on the metal layer
The positive photoresist of (1).
Step k, exposure and development are carried out based on a fourth preset mask, so that an invalid region between a source electrode corresponding to the source region contact hole and a field plate corresponding to the cut-off region contact hole is determined;
and then, exposing and developing the source electrode corresponding to the source electrode contact hole or the invalid metal window area between the field plate corresponding to the anode and the stop area contact hole, namely the invalid area through a fourth preset mask.
And step l, corroding the invalid metal layer corresponding to the invalid region, and removing the photoresist.
And then, corroding an invalid metal layer corresponding to the invalid region by using a wet etching method, and finally removing the photoresist to obtain a qualified transistor, wherein as shown in fig. 7, the N + + Sub substrate is used as a cathode or a drain electrode, the upper left part is an anode or a source electrode, and the upper right part is a metal field plate.
It should be added that the width of the injection window of the pressure-bearing ring is preferably 40-100um, and the depth of the PN junction of the pressure-bearing ring is 4-8um after the process is completed;
the cut-off distance between the pressure-bearing ring and the JFET injection diffusion layer is 35-40um, and the final peak concentration depth of the JFET injection diffusion layer is larger than the P-body junction depth by 2-4 um;
cut-off field plate length: the dimension from the left side of the JFET implant window to the top of the off-spacing is about 24-30 um.
The invention also provides a transistor manufacturing apparatus, a computer-readable storage medium, and a program product.
The transistor manufacturing apparatus, the computer readable storage medium of the present invention has stored thereon a transistor manufacturing program product which, when executed by a processor, implements the steps of the transistor manufacturing method as described above.
The method implemented when the transistor manufacturing program run on the processor is executed may refer to various embodiments of the transistor manufacturing method of the present invention, and details thereof are not described herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A method of manufacturing a transistor, the method comprising:
after a field oxide layer is thermally grown on an epitaxial wafer, determining a first position of a doping window for injecting a pressure-bearing ring in the field oxide layer, and injecting first conductive doping impurities based on the first position to form a pressure-bearing ring PN junction;
determining a second position of a source region injection window and a third position of a stop region injection window in the field oxide layer, and injecting first conductive doping impurities and second conductive doping impurities based on the second position and the third position to form a source region PN junction and a stop region PN junction, wherein the source region PN junction is partially overlapped with the pressure-bearing ring PN junction;
depositing a doped oxide layer PSG on the surface of the field oxide layer, determining a fourth position of a source region contact hole and a fifth position of a stop region contact hole in the doped oxide layer PSG, and forming a source region contact hole and a stop region contact hole based on the fourth position and the fifth position;
and depositing metal layers on the doped oxide layer PSG, the source region contact hole and the stop region contact hole, and removing the invalid metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole.
2. The method of claim 1, wherein the step of determining a first location of a halo implant doping window in the field oxide layer after thermally growing a field oxide layer on the epitaxial wafer, and performing a first conductive dopant impurity implant based on the first location to form a halo PN junction comprises:
after a field oxide layer is thermally grown on an epitaxial wafer, photoresist with a preset thickness is coated on the field oxide layer, and exposure and development are carried out based on a first preset mask so as to determine a first position of a doping window injected into a pressure-bearing ring;
etching the oxide layer corresponding to the injection doping window of the pressure-bearing ring based on the first position, and removing the photoresist;
and injecting first conductive doping impurities into the pressure-bearing ring injection doping window to form a pressure-bearing ring PN junction.
3. The method for fabricating a transistor according to claim 2, wherein the step of implanting the first conductive dopant impurity into the halo implant window to form a halo PN junction comprises:
injecting a first conductive doping impurity into the doping window of the pressure-bearing ring, and performing high-temperature diffusion on the first conductive doping impurity based on a preset temperature and a preset time;
and thermally growing a first shielding oxide layer with a preset thickness on the injection window of the pressure-bearing ring to form a PN junction of the pressure-bearing ring.
4. The method of manufacturing a transistor according to claim 1, wherein the step of determining a second position of a source region implantation window and a third position of a stop region implantation window in the field oxide layer and performing implantation of a first conductive doping impurity and a second conductive doping impurity based on the second position and the third position to form a source region PN junction and a stop region PN junction, the source region PN junction partially overlapping the confinement ring PN junction comprises:
coating photoresist with a preset thickness on the field oxide layer, and carrying out exposure and development based on a second preset mask to determine a second position of the source region injection window and a third position of the stop region injection window;
based on the second position and the third position, corroding an oxide layer corresponding to the source region injection window and an oxide layer corresponding to the stop region injection window, and thermally growing a second shielding oxide layer and a third shielding oxide layer with preset thicknesses on the source region injection window and the stop region injection window respectively;
and removing the photoresist, and respectively injecting a first conductive doping impurity and a second conductive doping impurity into the source region injection window and the cut-off region injection window to form a source region PN junction and a cut-off region PN junction.
5. The method for manufacturing a transistor according to claim 4, wherein the step of implanting the first conductive dopant impurity and the second conductive dopant impurity into the source region implantation window and the stop region implantation window, respectively, to form the source region PN junction and the stop region PN junction comprises:
respectively injecting second conductive doping impurities into the source region injection window and the stop region injection window, and diffusing the second conductive doping impurities to a preset doping peak depth based on a preset temperature and a preset time;
and respectively injecting first conductive doping impurities into the source region injection window and the cut-off region injection window, and performing high-temperature diffusion on the first conductive doping impurities based on preset temperature and preset time to form a source region PN junction and a cut-off region PN junction.
6. The method for manufacturing a transistor according to claim 1, wherein the step of depositing a doped oxide layer PSG on the surface of the field oxide layer, determining a fourth position of a source region contact hole and a fifth position of a stop region contact hole in the doped oxide layer PSG, and opening the source region contact hole and the stop region contact hole based on the fourth position and the fifth position comprises:
depositing a doped oxide layer PSG on the surface of the field oxide layer, and carrying out densification treatment on the doped oxide layer PSG in an oxygen atmosphere based on a preset temperature and preset time;
coating photoresist with a preset thickness on the doped oxide layer PSG, and carrying out exposure and development based on a third preset mask to determine a fourth position of a source region contact hole and a fifth position of a stop region contact hole;
and respectively etching to form a source region contact hole and a stop region contact hole based on the fourth position and the fifth position, and removing the photoresist.
7. The method for manufacturing a transistor according to any one of claims 1 to 6, wherein the step of depositing a metal layer on the doped oxide layer PSG, the source region contact hole and the stop region contact hole, and removing an inactive metal layer between the source electrode corresponding to the source region contact hole and the field plate corresponding to the stop region contact hole comprises:
depositing a metal layer on the doped oxide layer PSG, the source region contact hole and the cut-off region contact hole, and coating photoresist with a preset thickness on the metal layer;
exposing and developing based on a fourth preset mask to determine an invalid region between a source electrode corresponding to the source region contact hole and a field plate corresponding to the cut-off region contact hole;
and corroding the invalid metal layer corresponding to the invalid region, and removing the photoresist.
8. A transistor manufacturing apparatus, characterized by comprising:
a memory for storing executable instructions;
a processor for implementing the steps of the transistor fabrication method of any one of claims 1 to 7 when executing executable instructions stored in the memory.
9. A computer-readable storage medium, having stored thereon a transistor manufacturing program which, when executed by a processor, implements the steps of the transistor manufacturing method according to any one of claims 1 to 7.
10. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, realizes the steps of the transistor manufacturing method according to any one of claims 1 to 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116741821A (en) * | 2023-08-09 | 2023-09-12 | 深圳腾睿微电子科技有限公司 | IGBT device structure and corresponding manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102280493A (en) * | 2010-05-26 | 2011-12-14 | 三菱电机株式会社 | Semiconductor device |
| CN102468337A (en) * | 2010-11-09 | 2012-05-23 | 富士电机株式会社 | Semiconductor device |
| CN103066125A (en) * | 2011-10-21 | 2013-04-24 | 富士电机株式会社 | Superjunction semiconductor device |
| KR20160065326A (en) * | 2014-11-28 | 2016-06-09 | 매그나칩 반도체 유한회사 | Power semiconductor device and method of fabricating the same |
| CN111755503A (en) * | 2020-07-10 | 2020-10-09 | 嘉兴斯达半导体股份有限公司 | Variable transverse doping terminal structure and manufacturing method thereof |
-
2021
- 2021-06-29 CN CN202110723708.XA patent/CN113451137A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102280493A (en) * | 2010-05-26 | 2011-12-14 | 三菱电机株式会社 | Semiconductor device |
| CN102468337A (en) * | 2010-11-09 | 2012-05-23 | 富士电机株式会社 | Semiconductor device |
| CN103066125A (en) * | 2011-10-21 | 2013-04-24 | 富士电机株式会社 | Superjunction semiconductor device |
| KR20160065326A (en) * | 2014-11-28 | 2016-06-09 | 매그나칩 반도체 유한회사 | Power semiconductor device and method of fabricating the same |
| CN111755503A (en) * | 2020-07-10 | 2020-10-09 | 嘉兴斯达半导体股份有限公司 | Variable transverse doping terminal structure and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116741821A (en) * | 2023-08-09 | 2023-09-12 | 深圳腾睿微电子科技有限公司 | IGBT device structure and corresponding manufacturing method |
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