CN113451131A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
CN113451131A
CN113451131A CN202010211643.6A CN202010211643A CN113451131A CN 113451131 A CN113451131 A CN 113451131A CN 202010211643 A CN202010211643 A CN 202010211643A CN 113451131 A CN113451131 A CN 113451131A
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China
Prior art keywords
layer
opening
forming
mask layer
mask
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岳华聪
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010211643.6A priority Critical patent/CN113451131A/en
Publication of CN113451131A publication Critical patent/CN113451131A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method for forming a semiconductor device includes forming a first cutting layer in a first opening of a first mask layer and forming a second cutting layer in a second opening of the first mask layer. Meanwhile, when the second cutting layer is formed, the size of the second cutting layer in the first direction can be adjusted according to actual needs, the distance from the second opening head to the head after the second cutting layer is cut can be adjusted, and diversified process requirements are met.

Description

Method for forming semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor device.
Background
The conventional planar fet has poor control capability of channel current, and accordingly, a new cmos-Fin Field Effect Transistor (FinFET) is developed.
In a Back End Of Line (BEOL) self-aligned double patterning (SADP) process Of a finfet, a first mask layer on a semiconductor substrate needs to be patterned.
However, the conventional method for patterning the first mask layer has the problem of complicated operation, which reduces the work efficiency.
Disclosure of Invention
The technical problem to be solved by the invention is how to simplify the patterning operation of the first mask layer and improve the working efficiency.
In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, where the method includes:
providing a layer to be etched;
forming a first mask layer on the layer to be etched;
forming a plurality of first openings extending along a first direction in the first mask layer;
forming a side wall layer on the side wall of the first opening;
after the side wall layers are formed, second openings extending along the first direction are formed in the first mask layer between the adjacent first openings;
forming a first cutting layer in the first opening to cut the first opening in a second direction, and in the process of forming the first cutting layer, forming a second cutting layer in the second opening to cut the second opening in the second direction; the second direction is perpendicular to the first direction.
Optionally, before forming the first mask layer on the layer to be etched, the method further includes: forming a second mask layer on the layer to be etched; the first mask layer is positioned above the second mask layer; after the first cutting layer and the second cutting layer are formed, etching the second mask layer by taking the first mask layer, the side wall layer, the first cutting layer and the second cutting layer as masks, forming a third opening in the second mask layer at the bottom of the first opening, and forming a fourth opening in the second mask layer at the bottom of the second opening; and after a third opening and a fourth opening are formed in the second mask layer, removing the first mask layer, the side wall layer, the first cutting layer and the second cutting layer.
Optionally, the step of forming the first opening includes: forming a patterned third mask layer on the first mask layer; etching the first mask layer by taking the patterned third mask layer as a mask to form the first opening; and removing the third mask layer after the first opening is formed.
Optionally, before forming the patterned third mask layer, the method further includes: sequentially forming a first SOC layer and a first Si-ARC layer on the first mask layer; and in the process of forming the first opening, sequentially etching the first Si-ARC layer, the first SOC layer and the first mask layer by taking the patterned third mask layer as a mask.
Optionally, a process of etching the first mask layer by using the patterned third mask layer as a mask is a first plasma dry etching process, and an etching angle of the first plasma dry etching process is 90 degrees.
Optionally, in the process of forming the first opening, an etching selection ratio of the first mask layer to the second mask layer is greater than or equal to 100.
Optionally, the step of forming the sidewall layer includes: depositing a side wall material layer on the top surface of the first mask layer, the side wall and the bottom of the first opening; and etching back the side wall material layer, removing the top surface of the first mask layer and the side wall material layer at the bottom of the first opening, and forming a side wall layer positioned on the side wall of the first opening.
Optionally, the material of the sidewall layer comprises titanium oxide.
Optionally, the forming process of the side wall material layer includes an atomic layer deposition process.
Optionally, the thickness of the sidewall layer is 100 to 150 angstroms.
Optionally, the step of forming the second opening comprises: forming a patterned fourth mask layer on the first mask layer; etching the first mask layer between the adjacent first openings by taking the patterned fourth mask layer as a mask to form the second openings, wherein the side walls of the second openings are exposed out of the side wall layer; and removing the fourth mask layer after the second opening is formed.
Optionally, before forming the patterned fourth mask layer, the method further includes: sequentially forming a second SOC layer and a second Si-ARC layer on the first mask layer; and in the process of forming the second opening, sequentially etching the second Si-ARC layer, the second SOC layer and the first mask layer by taking the patterned fourth mask layer as a mask.
Optionally, the process of etching the first mask layer between the adjacent first openings by using the patterned fourth mask layer as a mask is a second plasma dry etching process, and an etching angle of the second plasma dry etching process is 90 degrees.
Optionally, in the process of forming the second opening, an etching selection ratio of the first mask layer to the second mask layer is greater than or equal to 100, and an etching selection ratio of the first mask layer to the sidewall layer is greater than or equal to 20.
Optionally, the step of forming the first and second cut layers comprises: forming a sacrificial material layer covering the first mask layer, the first opening, the sidewall layer and the second opening; planarizing the sacrificial material layer until the top surface of the first mask layer and the top surface of the side wall are exposed, and forming a sacrificial layer filled in the first opening and the second opening; forming a first cutting groove positioned in the first opening and a second cutting groove positioned in the second opening in the sacrificial layer; forming a cutting material layer which covers the first mask layer, the side wall layer and the sacrificial layer and fills the first cutting groove and the second cutting groove; removing the cutting material layer on the top surface of the first mask layer, the top surface of the sacrificial layer and part of the top surface of the side wall layer to form a first cutting layer and a second cutting layer; and removing the sacrificial layer.
Optionally, the process of forming the first cutting layer and the second cutting layer is a third plasma dry etching process.
Optionally, the material of the cutting material layer comprises a low temperature oxide.
Alternatively, for the adjacent first and second openings, the first cut layer located in the first opening and the second cut layer located in the second opening are separated from each other in the first direction.
Optionally, the size of the first cutting layer in the first direction is 20 nm to 30 nm; the second cutting layer has a size of 20 to 30 nm in the first direction.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the scheme, the first cutting layer is formed in the first opening in the first mask layer, and the second cutting layer is formed in the second opening at the same time. In addition, when forming the second cutting layer, can adjust the size of second cutting layer in first direction according to actual needs, and then can adjust the second opening Head after the cutting to first (Head to Head) distance, satisfy diversified technology demand.
Drawings
Fig. 1 is a schematic flow chart of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 2 to 9 are schematic intermediate structures corresponding to steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As a background art, in a conventional self-aligned double patterning (SADP) process Of a Back End Of Line (BEOL) Of a finfet, two processes are required to separate a first opening and a second opening Of a first mask layer, which causes a problem Of complicated operation and reduces work efficiency.
According to the technical scheme, the first cutting layer is formed in the first opening in the first mask layer, and the second cutting layer is formed in the second opening at the same time. In addition, when forming the second cutting layer, can adjust the size of second cutting layer in the first direction according to actual needs, and then can adjust the second opening head after the cutting to the first distance, satisfy diversified technology demand.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention. Referring to fig. 1, a method for forming a semiconductor device in an embodiment of the present invention may specifically include the following steps:
step S101: providing a layer to be etched;
step S102: forming a first mask layer on the layer to be etched;
step S103: forming a plurality of first openings extending along a first direction in the first mask layer;
step S104: forming a side wall layer on the side wall of the first opening;
step S105: after the side wall layers are formed, second openings extending along the first direction are formed in the first mask layer between the adjacent first openings;
step S106: forming a first cutting layer in the first opening to cut the first opening in a second direction, and in the process of forming the first cutting layer, forming a second cutting layer in the second opening to cut the second opening in the second direction; the second direction is perpendicular to the first direction.
A method of forming a semiconductor device in an embodiment of the present invention will be described in further detail below with reference to fig. 2 to 9.
Referring to fig. 2, a substrate is provided on which a layer to be etched 100 is formed.
In a specific implementation, the substrate provides a process platform for the subsequent formation of the FinFET. The fin field effect transistor can be one of an NMOS transistor or a PMOS transistor.
In a specific implementation, the base can be a silicon substrate or a germanium substrate or the like. In addition, other devices such as a PMOS transistor, an NMOS transistor, etc. may be formed in the substrate; an isolation structure may also be formed in the substrate, and the isolation structure is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. Similarly, a conductive member may be formed in the substrate, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like.
In the embodiment of the present invention, the layer to be etched 100 is a multi-layer structure, and includes a first etching stop layer, an interlayer dielectric layer located on the first etching stop layer, a second etching stop layer located on the interlayer dielectric layer, and a bottom hard mask layer located on the second etching stop layer. In this embodiment, the first etch stop layer is made of aluminum nitride (aln), the interlayer dielectric layer is made of Black Diamond (BD) or low-K dielectric material, the second etch stop layer is made of silicon oxycarbide (SiOC), and the bottom hard mask layer is made of titanium nitride (TiN).
Referring to fig. 3, a second mask layer 110 and a first mask layer 120 on the second mask layer 110 are sequentially formed on the layer to be etched 100.
In this embodiment, the second mask layer 110 is located on the bottom hard mask layer.
The second mask layer 110 is used for forming a third opening and a fourth opening therein by etching in the following.
The first mask layer 120 serves as an etch mask for subsequent etching of the second mask layer 110.
The material of the first mask layer 120 includes: amorphous silicon.
The material of the second mask layer 110 includes: silicon oxide or SiOC. The second mask layer 110 can also increase adhesion between the underlying hard mask layer and the first mask layer 120.
The second etch stop layer also increases adhesion between the underlying hard mask layer and the interlevel dielectric layer.
Referring to fig. 4, the first mask layer 120 is etched, and a plurality of first openings 121 extending along a first direction are formed in the first mask layer 120, wherein the bottom of the first openings 121 expose the material of the second mask layer 110.
In a specific implementation, the first opening 121 is used to define the position and the width of a third opening to be formed in the first mask layer.
In a specific implementation, the step of forming the first opening may include: sequentially forming a first SOC layer, a first Si-ARC layer and a third mask layer on the first mask layer; performing a photolithography process on the third mask layer by using a mask to form a patterned third mask layer, wherein the patterned third mask layer has a pattern defining a plurality of openings extending along a first direction; sequentially etching the first Si-ARC, the first SOC layer and the first mask layer 120 by using the patterned third mask layer as a mask until the top surface of the second mask layer 110 is exposed, and forming a plurality of first openings 121 extending along the first direction in the first mask layer 120; and then removing the first SOC layer, the first Si-ARC layer and the third mask layer. In this embodiment, the process of etching the first mask layer by using the patterned third mask layer as a mask is a first plasma dry etching process, and an etching angle of the first plasma dry etching process is 90 degrees.
In order to retain the second mask layer 110 in the step of forming the first opening 121, the etch selectivity rate for the second mask layer 110 should be smaller than the etch selectivity rate for the first mask layer 120. In the embodiment of the present invention, in the process of etching the first mask layer 120 to form the first opening 121, an etching selection ratio of the first mask layer to the second mask layer is greater than or equal to 100, such as 150, 200, and the like.
In this embodiment, the third mask layer is made of photoresist.
Referring to fig. 5, a sidewall layer 130 is formed on sidewalls of the first opening 121.
The sidewall layer 130 is used to define a spacing distance between the first opening and a subsequently formed second opening in a second direction; the second direction is perpendicular to the first direction. The sidewall layer 130 separates the first opening from the second opening.
In a specific implementation, the sidewall layer may be selected to have a higher etch selectivity rate relative to the second hard mask layer. In an embodiment of the invention, the material of the sidewall layer comprises titanium oxide. In other embodiments, the material of the sidewall layer may also be formed of AlO, AlN, AlON, TaN, SiO, or SiN, or other materials such as nitride, oxide, oxynitride, carbide, boride, and combinations thereof.
The step of forming the sidewall layer may include: depositing a side wall material layer on the top surface of the second mask layer and the side wall and the bottom of the first opening; and etching back the side wall material layer, removing the side wall material layer on the top surface of the first mask layer and the bottom surface of the first opening, and forming a side wall layer positioned on the side wall of the first opening.
The process for forming the side wall material layer is a deposition process, such as an atomic layer deposition process.
In a specific implementation, the dimension of the sidewall layer in the second direction may be determined according to a distance between a subsequently formed first opening and a subsequently formed second opening in the second direction, that is, according to a distance between a first metal line and a second metal line in an interlayer dielectric layer of the layer to be etched 100, which are subsequently formed in the second direction. In the embodiment of the invention, the thickness of the side wall layer is 100-150 angstroms.
Referring to fig. 6, after the formation of the sidewall layer 130, second openings 122 extending along the first direction are formed in the first mask layer 120 between adjacent first openings 121.
In this embodiment, the material of the second mask layer 110 is exposed at the bottom of the second opening 122.
The second opening is used for defining the position of a fourth opening formed in the second mask layer subsequently.
The step of forming the second opening may include: forming a second SOC layer, a second Si-ARC layer and a patterned fourth mask layer on the first hard mask layer; sequentially etching the second Si-ARC layer, the second SOC layer and the first mask layer between the adjacent first openings with the patterned fourth mask layer as a mask, and forming second openings 122 extending along the first direction in the first mask layer between the adjacent first openings 121; after the second opening 122 is formed, the second SOC layer, the second Si-ARC layer and the patterned fourth mask layer are removed. In this embodiment, a process of sequentially etching the second Si-ARC layer, the second SOC layer, and the first mask layer with the patterned fourth mask layer as a mask is a second plasma dry etching process, and an etching angle of the second plasma dry etching process is 90 degrees.
In specific implementation, the positions and the number of the sizes of the first opening 121 and the second opening 122 can be determined according to actual process requirements. In the present embodiment, the number of the first openings 121 and the second openings 122 is 3 and 2, respectively.
In order to retain the second mask layer 110 and the sidewall spacers 130 in the step of forming the second opening 122, the etching rate for the first mask layer 120 should be greater than the etching rates for the second mask layer 110 and the sidewall spacers 130, respectively. In the embodiment of the present invention, in the process of etching the first mask layer to form the second opening 122, an etching selection ratio of the first mask layer to the second mask layer is greater than or equal to 100, such as 150, 200, and the like, and an etching selection ratio of the first mask layer to the sidewall layer is greater than or equal to 20, such as 50, 100, and the like.
Referring to fig. 7, a first cutting layer 141 cutting the first opening 121 along a second direction is formed in the first opening 121, and a second cutting layer 142 cutting the second opening 122 along the second direction is formed in the second opening 122 in the process of forming the first cutting layer 141; the second direction is perpendicular to the first direction.
The first cutting layer 141 located in the first opening 121 and the second cutting layer 142 located in the second opening 122 are separated from each other in the first direction with respect to the adjacent first opening 121 and second opening 122.
The first cutting layer 141 is used for defining the cutting position and the size of a third opening formed in the second mask layer 110 later; the second cutting layer 142 is used to define the dividing position and size of the fourth opening to be formed in the second mask layer 110.
In this embodiment, the material of the first cutting layer 141 and the second cutting layer 142 is a Low Temperature Oxide (LTO).
The step of forming the first and second cutting layers 141 and 142 may include: forming a sacrificial material layer covering the first mask layer 120, the first opening 121, the sidewall layer 130 and the second opening 122; planarizing the sacrificial material layer until the top surface of the first mask layer 120 and the top surface of the sidewall layer 130 are exposed, forming a sacrificial layer filled in the first opening 121 and the second opening 122; forming a first cutting groove in the first opening 121 and a second cutting groove in the second opening 122 in the sacrificial layer 122, wherein the first cutting groove and the second cutting groove in the adjacent sacrificial layers are mutually separated in the first direction; a first cutting layer 141 is formed in the first cutting groove, and a second cutting layer 142 is formed in the second cutting groove.
The sacrificial material layer provides a process base for subsequently forming a first cutting groove in the first opening and a second cutting groove in the second opening.
The process for forming the sacrificial material layer comprises adopting chemical vapor deposition, physical vapor deposition and atomic layer deposition processes.
The first cutting groove is used for defining a process position of a first cutting layer 141 formed in the first opening 121; the second cutting groove is used to define a processing position of a second cutting layer 142 subsequently formed in the second opening 122.
The step of forming the first and second cutting grooves 141 and 142 may include: forming a third SOC layer, a third Si-ARC layer and a patterned fifth mask layer on the upper surfaces of the first mask layer 120, the sidewall layer 130 and the sacrificial layer in sequence; the patterned fifth mask layer is provided with patterns for defining a first cutting groove and a second cutting groove; sequentially etching the third SOC layer, the third Si-ARC layer and the sacrificial layer by taking the patterned fifth mask layer as a mask until the top surface of the first mask layer is exposed, and forming a first cutting groove in the first opening 121 and a second cutting groove in the second opening 122 in the sacrificial layer; and after the first cutting groove and the second cutting groove are formed, removing the patterned third mask layer, the third SOC layer and the third Si-ARC layer.
The subsequent steps further include a step of removing a sacrificial layer, and in order to retain the first mask layer 120, the sidewall layer 130, and the first and second cutting layers 141 and 142 in the step of removing the sacrificial layer, the etching rate of the sacrificial layer should be greater than the etching rate of the first mask layer 120, the sidewall layer 130, and the first and second cutting layers 141 and 142, respectively.
The method of forming the first and second cutting layers 141 and 142 may include: forming a cutting material layer covering the first mask layer 120, the sidewall layer 130, the sacrificial layer and filling the first cutting groove and the second cutting groove; and etching back the cutting material layer, removing the top surface of the first mask layer 120, the top surface of the sacrificial layer and part of the cutting material layer on the top surface of the sidewall layer to form the first cutting layer 141 and the second cutting layer 142, wherein the first cutting layer 141 further extends to the positions on the sidewall layers on the two sides of the first cutting groove along the second direction, and the second cutting layer 142 further extends to the positions on the sidewall layers on the two sides of the second cutting groove along the second direction.
In this embodiment, the first cutting layer 141 extends to the sidewall layers on both sides of the first cutting groove along the second direction, but the first cutting layer 141 does not extend to the adjacent second opening, and the first cutting layer 141 does not cut the second opening.
In this embodiment, the second cutting layer 142 further extends to the sidewall layers on two sides of the second cutting groove along the second direction, but the second cutting layer 142 does not extend to the adjacent first opening, and the second cutting layer 142 does not cut the first opening.
Since the first cut layer 141 extends over the sidewall layers on both sides of the first cut groove along the second direction, the size of the first cut layer 141 in the second direction increases, so that the restriction on the size of the first cut layer 141 in the second direction is reduced while restricting the first cut layer 141 in the first direction to have a smaller size. Therefore, difficulty in forming the first cutting layer 141 is reduced.
Since the second cutting layer 142 also extends above the sidewall layer at both sides of the second cutting groove along the second direction, the size of the second cutting layer 142 in the second direction increases, so that the restriction on the size of the second cutting layer 142 in the second direction decreases while the size of the second cutting layer 142 in the first direction is restricted from having a smaller size. Therefore, the difficulty of forming the second cutting layer 142 is reduced.
In one embodiment, the first cutting layer 141 has a dimension in the first direction of 20 nm to 30 nm, such as 26 nm.
In one embodiment, the second cutting layer 142 has a dimension in the first direction of 20 nm to 30 nm, such as 26 nm.
The size of the first cutting layer 141 in the first direction is the same as or different from the size of the second cutting layer 142 in the first direction.
The process of forming the cutting material layer includes a deposition process such as a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, or an atomic layer deposition process.
In the embodiment of the present invention, after the first cutting layer and the second cutting layer are formed, a step of removing the sacrificial layer is further included. In this embodiment, the sacrificial layer in the first opening and the sacrificial layer in the second opening are removed by etching through a third plasma dry etching process.
Referring to fig. 8, the second mask layer 110 is etched by using the first mask layer 120, the sidewall layer 130, the first cut layer 141, and the second cut layer 142 as masks, a third opening 111 is formed in the second mask layer 110 at the bottom of the first opening, and a fourth opening 112 is formed in the second mask layer at the bottom of the second opening.
Due to the existence of the first and second cutting layers 141 and 142, the second mask layer 110 under the first and second cutting layers 141 and 142 is remained, so that the third and fourth openings 111 and 112 are separated by the second mask layer 110 remained under the first and second cutting layers, respectively.
Referring to fig. 9, after forming the third opening 111 and the fourth opening 112, the first and second cut layers 141 and 142, the sidewall layer 130, and the first mask layer 120 are removed.
In a specific implementation, the processes of removing the first and second cutting layers 141 and 142, the sidewall layer 130, and the first mask layer 120 include a dry etching process and a wet etching process.
In order to remain the layer to be etched 100, during the process of removing the first and second cut layers 141 and 142, the sidewall layer 130, and the first mask layer 120, the etching rate of the layer to be etched 100 should be smaller than the etching rates of the first and second cut layers 141 and 142, the sidewall layer 130, and the first mask layer 120, respectively. The material of the layer to be etched 100 should be selected to have an etching selection rate respectively smaller than the etching selection rates of the first cutting layer 141 and the second cutting layer 142, the sidewall 130 and the first mask layer 120.
In the embodiment of the present invention, the first cutting layer 141 and the second cutting layer 142, the sidewall layer 130, and the first mask layer 120 are removed, so that the third opening and the fourth opening patterns formed in the second mask layer are continuously transferred downward to the interlayer dielectric layer in the layer to be etched 100, a corresponding opening is formed in the interlayer dielectric layer, and a corresponding opening is formed in the interlayer dielectric layer and filled with a metal material, so as to form a plurality of corresponding conductive layers.
Specifically, in this embodiment, the layer to be etched 100 at the bottom of the third opening and the fourth opening is etched by using the second mask layer as a mask, a first middle opening is formed in the bottom hard mask layer at the bottom of the third opening, and a second middle opening is formed in the bottom hard mask layer at the bottom of the fourth opening; then, removing the second mask layer; then, etching the second etching stop layer and the interlayer dielectric layer at the bottoms of the first middle opening and the second middle opening by taking the bottom hard mask layer as a mask, forming a first interconnection opening in the interlayer dielectric layer at the bottom of the first middle opening, and forming a second interconnection opening in the interlayer dielectric layer at the bottom of the second middle opening; forming a first conductive layer in the first interconnect opening; a second conductive layer is formed in the second interconnect opening.
In one embodiment, the second conductive layer is formed during the formation of the first conductive layer, simplifying the process.
By adopting the scheme in the implementation of the invention, the first cutting layer is formed in the first opening in the first mask layer, and the second cutting layer is formed in the second opening at the same time, so that compared with the prior art that the first cutting layer and the second cutting layer are respectively formed by adopting two processes, the process operation steps can be simplified, and the working efficiency is improved. In addition, when forming the second cutting layer, can adjust the size of second cutting layer in the first direction according to actual needs, and then can adjust the second opening head after the cutting to the first distance, satisfy diversified technology demand.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor device, comprising:
providing a layer to be etched;
forming a first mask layer on the layer to be etched;
forming a plurality of first openings extending along a first direction in the first mask layer;
forming a side wall layer on the side wall of the first opening;
after the side wall layers are formed, second openings extending along the first direction are formed in the first mask layer between the adjacent first openings;
forming a first cutting layer in the first opening to cut the first opening in a second direction, and in the process of forming the first cutting layer, forming a second cutting layer in the second opening to cut the second opening in the second direction; the second direction is perpendicular to the first direction.
2. The method for forming a semiconductor device according to claim 1, further comprising, before forming the first mask layer over the layer to be etched: forming a second mask layer on the layer to be etched; the first mask layer is positioned above the second mask layer; after the first cutting layer and the second cutting layer are formed, etching the second mask layer by taking the first mask layer, the side wall layer, the first cutting layer and the second cutting layer as masks, forming a third opening in the second mask layer at the bottom of the first opening, and forming a fourth opening in the second mask layer at the bottom of the second opening; and after a third opening and a fourth opening are formed in the second mask layer, removing the first mask layer, the side wall layer, the first cutting layer and the second cutting layer.
3. The method according to claim 1, wherein the step of forming the first opening comprises:
forming a patterned third mask layer on the first mask layer;
etching the first mask layer by taking the patterned third mask layer as a mask to form the first opening;
and removing the third mask layer after the first opening is formed.
4. The method of claim 3, further comprising, prior to forming the patterned third mask layer: sequentially forming a first SOC layer and a first Si-ARC layer on the first mask layer; and in the process of forming the first opening, sequentially etching the first Si-ARC layer, the first SOC layer and the first mask layer by taking the patterned third mask layer as a mask.
5. The method for forming a semiconductor device according to claim 3, wherein the process of etching the first mask layer by using the patterned third mask layer as a mask is a first plasma dry etching process, and an etching angle of the first plasma dry etching process is 90 degrees.
6. The method of claim 2, wherein an etching selectivity ratio of the first mask layer to the second mask layer is greater than or equal to 100 during the forming of the first opening.
7. The method according to claim 1, wherein the step of forming the sidewall layer comprises:
depositing a side wall material layer on the top surface of the first mask layer, the side wall and the bottom of the first opening;
and etching back the side wall material layer, removing the top surface of the first mask layer and the side wall material layer at the bottom of the first opening, and forming a side wall layer positioned on the side wall of the first opening.
8. The method according to claim 1, wherein a material of the sidewall layer comprises titanium oxide.
9. The method for forming the semiconductor device according to claim 7, wherein the forming process of the side wall material layer comprises an atomic layer deposition process.
10. The method of claim 1, wherein the thickness of the sidewall layer is 100 to 150 angstroms.
11. The method according to claim 1, wherein the step of forming the second opening comprises:
forming a patterned fourth mask layer on the first mask layer;
etching the first mask layer between the adjacent first openings by taking the patterned fourth mask layer as a mask to form the second openings, wherein the side walls of the second openings are exposed out of the side wall layer;
and removing the fourth mask layer after the second opening is formed.
12. The method of claim 11, further comprising, prior to forming the patterned fourth mask layer: sequentially forming a second SOC layer and a second Si-ARC layer on the first mask layer; and in the process of forming the second opening, sequentially etching the second Si-ARC layer, the second SOC layer and the first mask layer by taking the patterned fourth mask layer as a mask.
13. The method for forming the semiconductor device according to claim 11, wherein a process of etching the first mask layer between the adjacent first openings with the patterned fourth mask layer as a mask is a second plasma dry etching process, and an etching angle of the second plasma dry etching process is 90 degrees.
14. The method of claim 2, wherein in the process of forming the second opening, an etching selection ratio of the first mask layer to the second mask layer is greater than or equal to 100, and an etching selection ratio of the first mask layer to the sidewall layer is greater than or equal to 20.
15. The method according to claim 1, wherein the step of forming the first cutting layer and the second cutting layer comprises:
forming a sacrificial material layer covering the first mask layer, the first opening, the sidewall layer and the second opening;
planarizing the sacrificial material layer until the top surface of the first mask layer and the top surface of the side wall are exposed, and forming a sacrificial layer filled in the first opening and the second opening;
forming a first cutting groove positioned in the first opening and a second cutting groove positioned in the second opening in the sacrificial layer;
forming a cutting material layer which covers the first mask layer, the side wall layer and the sacrificial layer and fills the first cutting groove and the second cutting groove;
removing the cutting material layer on the top surface of the first mask layer, the top surface of the sacrificial layer and part of the top surface of the side wall layer to form a first cutting layer and a second cutting layer;
and removing the sacrificial layer.
16. The method for forming a semiconductor device according to claim 15, wherein a process of forming the first cutting layer and the second cutting layer is a third plasma dry etching process.
17. The method of claim 15, wherein the material of the dicing material layer comprises a low temperature oxide.
18. The method for forming a semiconductor device according to claim 1, wherein a first cut layer located in the first opening and a second cut layer located in the second opening are separated from each other in the first direction for the adjacent first opening and second opening.
19. The method for forming a semiconductor device according to claim 1, wherein a size of the first cutting layer in the first direction is 20 to 30 nm; the second cutting layer has a size of 20 to 30 nm in the first direction.
CN202010211643.6A 2020-03-24 2020-03-24 Method for forming semiconductor device Pending CN113451131A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130244430A1 (en) * 2012-03-15 2013-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Double Patterning Method for Semiconductor Devices
CN109427651A (en) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN111668093A (en) * 2019-03-07 2020-09-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130244430A1 (en) * 2012-03-15 2013-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Double Patterning Method for Semiconductor Devices
CN109427651A (en) * 2017-08-24 2019-03-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN111668093A (en) * 2019-03-07 2020-09-15 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same

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