CN113448783B - Hard reset type data testing method and device - Google Patents
Hard reset type data testing method and device Download PDFInfo
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- CN113448783B CN113448783B CN202110554261.8A CN202110554261A CN113448783B CN 113448783 B CN113448783 B CN 113448783B CN 202110554261 A CN202110554261 A CN 202110554261A CN 113448783 B CN113448783 B CN 113448783B
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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Abstract
The invention discloses a method and a device for testing hard reset data, wherein the method comprises the following steps: a hardware switch is used for sending a test enabling instruction to a test control chip, so that the test control chip controls a storage chip to enable an automatic data collection function and an upper electrical basic input and output system; responding to the basic input and output system being powered on or powered on again to print the system log, and continuously acquiring and storing the system log from the basic input and output system by using the storage chip; responding to a hard reset type data ending keyword printed by a basic input and output system in a system log and sending a reset instruction to a power supply control chip; and powering off the basic input and output system in response to the power supply control chip receiving the reset instruction, and powering on the basic input and output system again after a preset delay. The invention can automatically execute RMT, liberate manpower, improve efficiency and analyze the performance of the memory in real time.
Description
Technical Field
The present invention relates to the field of testing, and more particularly, to a method and an apparatus for testing hard reset data.
Background
With the rapid development of the information era, technologies such as the internet, artificial intelligence and the like cover all fields of society, and higher requirements are made on the data processing capacity of a server and the transmission capacity of network data. The memory bank is used as a bridge to perform data exchange and processing tasks between hardware such as a hard disk, a mainboard and a video card and a processor in the server, and plays an important role in the performance of the server.
The RMT is a memory bit width margin test, and the test result directly reflects the performance of the memory on the server motherboard, while in the test process, a large amount of RMT data needs to be collected to analyze the performance, and in order to obtain effective RMT data, a serial port tool needs to be manually turned on and turned off once to obtain the effective RMT data, which wastes a large amount of manpower in the aspect of obtaining data, and cannot quickly obtain data and analyze the performance of the memory.
Aiming at the problems of labor consumption, low efficiency and slow data processing of RMT in the prior art, no effective solution is available at present.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method and an apparatus for testing hard reset data, which can automatically execute RMT, liberate labor, improve efficiency, and analyze memory performance in real time.
In view of the above object, a first aspect of the embodiments of the present invention provides a method for testing hard-reset data, including the following steps:
a hardware switch is used for sending a test enabling instruction to a test control chip, so that the test control chip controls a storage chip to enable an automatic data collection function and an upper electrical basic input and output system;
printing a system log in response to the basic input and output system being powered on or powered back on, and continuously acquiring and storing the system log from the basic input and output system by using a storage chip;
responding to a hard reset type data end keyword printed out in a system log by the basic input and output system and sending a reset instruction to the power supply control chip;
and powering off the basic input and output system in response to the power supply control chip receiving the reset instruction, and powering on the basic input and output system again after a preset delay.
In some embodiments, the hard reset data is memory bit width margin test data.
In some embodiments, the method further comprises: before a hardware switch is used for sending a test enabling instruction to a test control chip, a memory bit width margin tool and a serial port debugging mode of a basic input and output system are activated; the system log comprises memory bit width allowance test data.
In some embodiments, using the memory chip to continuously obtain and store the system log from the bios comprises: and outputting a system log comprising memory bit width allowance test data by the basic input and output system based on the memory bit width allowance tool, and acquiring and storing the system log by using a memory chip in a serial port debugging mode.
In some embodiments, the method further comprises: a hardware switch is used for sending a test stopping instruction to a test control chip, so that the test control chip controls a storage chip to stop a data automatic collection function to power off a basic input and output system;
and reading the system log from the storage chip, and intercepting the hard reset data from the system log by using the hard reset data start keyword and the hard reset data end keyword.
In some embodiments, the hardware switch is a flip cap; the hardware switch is used for sending a test enabling instruction to the test control chip, so that the test control chip controls the storage chip to enable the data automatic collection function to enable the electrical basic input and output system to comprise: sending a high level to a test control chip by using a jump cap, so that the test control chip sends the high level to a hard reset type data enabling end of a storage chip; the method for sending a test stopping instruction to a test control chip by using a hardware switch to enable the test control chip to control a storage chip to stop an automatic data collection function so as to power off a basic input and output system comprises the following steps: and sending a low level to the test control chip by using the jump cap, so that the test control chip sends the low level to the hard reset type data enabling end of the storage chip.
In some embodiments, the method further comprises: the hard reset data or the system log is output to the out-of-band manager in response to the memory chip obtaining a read instruction for the hard reset data from the out-of-band manager.
In some embodiments, the method further comprises: when the test control chip controls the storage chip to start the data automatic collection function and the power basic input and output system, the test control chip sends a false triggering insurance instruction to the power supply control chip; the power-down basic input output system in response to the power supply control chip receiving the reset instruction includes: and powering off the basic input and output system in response to the power supply control chip simultaneously receiving the reset instruction and the false triggering insurance instruction.
In some embodiments, the method further comprises: the memory chip is reset to clear all system logs stored in the memory chip in response to the test control chip detecting that the total size of the system logs stored in the memory chip has reached or exceeded a storage security threshold.
A second aspect of an embodiment of the present invention provides an apparatus, including:
a processor;
a controller storing program code executable by a processor, the processor executing the following steps when executing the program code:
a hardware switch is used for sending a test enabling instruction to a test control chip, so that the test control chip controls a storage chip to enable an automatic data collection function and an upper electrical basic input and output system;
responding to the basic input and output system being powered on or powered on again to print the system log, and continuously acquiring and storing the system log from the basic input and output system by using the storage chip;
responding to a hard reset type data ending keyword printed by a basic input and output system in a system log and sending a reset instruction to a power supply control chip;
and powering off the basic input and output system in response to the power supply control chip receiving the reset instruction, and powering on the basic input and output system again after a preset delay.
The invention has the following beneficial technical effects: according to the method and the device for testing the hard reset data, provided by the embodiment of the invention, the test enabling instruction is sent to the test control chip by using the hardware switch, so that the test control chip controls the storage chip to enable the automatic data collection function and the basic electrical input and output system; responding to the basic input and output system being powered on or powered on again to print the system log, and continuously acquiring and storing the system log from the basic input and output system by using the storage chip; responding to a hard reset type data ending keyword printed by a basic input and output system in a system log and sending a reset instruction to a power supply control chip; the technical scheme that the power supply control chip powers off the basic input and output system in response to the fact that the power supply control chip receives the reset instruction, and powers on the basic input and output system again after the preset time delay is achieved can automatically execute RMT, liberate manpower, improve efficiency and analyze memory performance in real time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flow chart of a hard-reset data testing method according to the present invention;
fig. 2 is a detailed flowchart of the method for testing hard-reset data according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the foregoing, a first aspect of the embodiments of the present invention provides an embodiment of a test method for automatically performing RMT, releasing manpower, improving efficiency, and analyzing memory performance in real time. Fig. 1 is a schematic flow chart illustrating a method for testing hard-reset data according to the present invention.
The method for testing hard-reset data, as shown in fig. 1, includes the following steps:
step S101, a hardware switch is used for sending a test enabling instruction to a test control chip, so that the test control chip controls a storage chip to enable an automatic data collection function to be used for powering up a basic input and output system;
step S103, responding to the basic input and output system being powered on or powered on again, printing the system log, and continuously acquiring and storing the system log from the basic input and output system by using the storage chip;
step S105, responding to the hard reset type data ending keyword printed in the system log by the basic input and output system and sending a reset instruction to the power supply control chip;
step S107, in response to the power supply control chip receiving the reset instruction, the bios is powered off, and the bios is powered on again after a preset delay.
The RMT data exists in the system log in the server and is a section of the log, not all of the log. Therefore, the embodiment of the invention can acquire the RMT data quickly by intercepting one section of log. The keywords for starting and ending RMT data in the system log are respectively 'START _ BSSA _ RMT' and 'STOP _ BSSA _ RMT', and the function of quickly acquiring multiple groups of RMT data can be achieved by utilizing the self-checking characteristic of the BIOS keywords and matching with the external hardware logic design.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by instructing relevant hardware by a computer program, and the program may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. Embodiments of the computer program may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.
In some embodiments, the hard reset data is memory bit width margin test data.
In some embodiments, the method further comprises: before a hardware switch is used for sending a test enabling instruction to a test control chip, a memory bit width margin tool and a serial port debugging mode of a basic input and output system are activated; the system log comprises memory bit width allowance test data.
In some embodiments, using the memory chip to continuously obtain and store the system log from the bios comprises: and outputting a system log comprising memory bit width allowance test data by the basic input and output system based on the memory bit width allowance tool, and acquiring and storing the system log by using a memory chip through a serial port debugging mode.
In some embodiments, the method further comprises: a hardware switch is used for sending a test stopping instruction to a test control chip, so that the test control chip controls a storage chip to stop a data automatic collection function to power off a basic input and output system;
and reading the system log from the storage chip, and intercepting the hard reset data from the system log by using the hard reset data start keyword and the hard reset data end keyword.
In some embodiments, the hardware switch is a flip cap; the hardware switch is used for sending a test enabling instruction to the test control chip, so that the test control chip controls the storage chip to enable the automatic data collection function and the power-on basic input and output system comprises: sending a high level to a test control chip by using a jump cap, so that the test control chip sends the high level to a hard reset type data enabling end of a storage chip; the method for sending a test stopping instruction to a test control chip by using a hardware switch to enable the test control chip to control a storage chip to stop an automatic data collection function so as to power off a basic input and output system comprises the following steps: and sending a low level to the test control chip by using the jump cap, so that the test control chip sends the low level to the hard reset type data enabling end of the storage chip.
In some embodiments, the method further comprises: the hard reset data or the system log is output to the out-of-band manager in response to the memory chip obtaining a read instruction for the hard reset data from the out-of-band manager.
In some embodiments, the method further comprises: when the test control chip controls the storage chip to start the data automatic collection function and the power basic input and output system, the test control chip sends a false triggering insurance instruction to the power supply control chip; the power-down basic input output system in response to the power supply control chip receiving the reset instruction includes: and powering off the basic input and output system in response to the power supply control chip simultaneously receiving the reset instruction and the false triggering insurance instruction.
In some embodiments, the method further comprises: resetting the memory chip to clear all system logs stored in the memory chip in response to the test control chip detecting that the total size of the system logs stored in the memory chip has reached or exceeded the storage security threshold.
The apparatuses and devices disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television, and the like, or may be a large terminal device, such as a server, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus and device. The client disclosed in the embodiment of the present invention may be applied to any one of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.
The following further illustrates embodiments of the invention in accordance with the specific example shown in fig. 2.
The current main ways to obtain RMT data are: a Rank Margin Tool and a Serial Debug mode are opened in a BIOS (basic input output system), the Serial Tool is manually opened to collect complete log information from Power On to Power Off once, effective RMT data is recorded once, and N sets of RMT data (target times) are repeatedly collected according to the method, which means that the Serial Tool needs to be manually switched On and Off for N times. When RMT data is obtained once, a serial port tool needs to be manually operated to carry out naming and storing work, and a tester needs to be kept beside a machine table.
The memory bit width margin test is a memory test scheme under normal temperature and voltage, and the whole test scheme is embedded into a specific BIOS. If the RMT option is enabled in BIOS, the platform will automatically enter RMT test mode. The test result is output through the serial port, and the allowance of the main board of the memory design part can be detected. RMT provides automatic memory bit width margin testing and is used to identify memory bit width margins at different levels. The test will be embedded in the memory reference code MRC and run after enablement. RMT is enabled in BIOS by the MRC and is executed during system boot. It automatically sets margins for memory reference voltage and duration parameters on the CPU and DIMM by applying a stress pattern and outputs the results to the serial port.
And embodiments of the present invention overcome this problem. Before testing, preparation is carried out, the server is powered on and started, and the Rank Margin Tool and the Serial Debug are opened in the BIOS so as to carry out RMT testing. In the embodiment of the invention, a jump cap is used as a hardware switch, a CPLD (complex logic programmable device) is used as a test control chip, a Flash memory is used as a storage chip, a VR (voltage regulator) is used as a power supply control chip, and a BMC (baseboard control manager) is used as an out-of-band manager.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
Referring to fig. 2, in the embodiment of the present invention, the RMT data automatic collection function is turned on and off by means of a cap jump: when the jump cap is placed at 1-2 bits, the signal 1.RMT_Mode is low level '0', the CPLD receives the signal and then sends a signal 3.RMT_Enable to the Flash chip to be also low level '0', at the moment, the Flash does not work, and the RMT data automatic collection function is closed; when the jump cap is placed at 2-3 positions, 3V3 electricity is pulled up from the outside, the signal 1 is high level 1, the CPLD also sends a high level signal 3 to the Flash chip, the Flash chip starts to work, and the RMT data automatic collection function is started.
After the server is started, the BIOS starts to print the system log, data is transmitted to the Flash chip for storage through a signal 5.RMT _DATA, and after the system log is printed to a keyword of STOP _ BSSA _ RMT, the BIOS triggers a signal 6.Data _detect. In order to avoid the situation that the system is shut down due to false triggering, a signal 3.RMT _Enableand a signal 6.Data _Detectenter an AND gate chip to perform logic judgment, so that a signal 7.Power Off is triggered to control VR, and the system is subjected to on-Off operation, and the judgment logic is as follows:
| 3.RMT_Enable(Input) | 6.Data_Detect(Input) | 7.Power Off(Output) |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 0 | 1 | 0 |
| 0 | 0 | 0 |
when the automatic function of RMT data is started, the signal 3 is high level "1", and after the system detects the keyword "STOP _ BSSA _ RMT", the signal 6 will also be high level "1", when both of these signals are high, the AND gate chip trigger signal 7.Power Off is also high level "1", after VR detects the signal 7 is high level, the system is powered Off and shut down, otherwise, the system is not shut down; after the internal delay (for example, 100 ms) of the CPLD, a signal 8.Power _Onis automatically triggered and sent to the VR, so that the system is powered on and started again, and the Flash chip collects RMT data again.
If the size of the stored system log file is about to exceed the storage size of the Flash chip, the CPLD sends a 4.reset signal to the Flash chip to Reset the Flash chip, and clears all system logs in the chip before, so that the system logs in the next test stage are normally stored. This is the Flash chip reset function.
In addition, the system log stored in the Flash is transmitted to the BMC through the I2C, and the log is downloaded and stored from the BMC Web interface inside the BMC. This is a log save function.
The computer-readable storage media (e.g., memory) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM may be available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
It can be seen from the foregoing embodiments that, in the hard reset data testing method provided in the embodiments of the present invention, a test enabling instruction is sent to the test control chip by using the hardware switch, so that the test control chip controls the memory chip to enable the data automatic collection function to enable the basic input/output system; printing a system log in response to the basic input and output system being powered on or powered back on, and continuously acquiring and storing the system log from the basic input and output system by using a storage chip; responding to a hard reset type data ending keyword printed by a basic input and output system in a system log and sending a reset instruction to a power supply control chip; the technical scheme that the power supply control chip powers off the basic input and output system in response to the fact that the power supply control chip receives the reset instruction, and powers on the basic input and output system again after the preset time delay is achieved can automatically execute RMT, liberate manpower, improve efficiency and analyze memory performance in real time.
It should be particularly noted that, the steps in the embodiments of the hard reset data testing method described above may be mutually intersected, replaced, added, or deleted, and therefore, these reasonably arranged and combined changes should also belong to the scope of the present invention, and should not limit the scope of the present invention to the described embodiments.
In view of the above, a second aspect of the embodiments of the present invention provides an embodiment of a test apparatus for performing RMT automatically, releasing manpower, improving efficiency, and analyzing hard reset data of memory performance in real time. The device comprises:
a processor;
a controller storing program code executable by a processor, the processor executing the following steps when executing the program code:
a hardware switch is used for sending a test enabling instruction to a test control chip, so that the test control chip controls a storage chip to enable an automatic data collection function and an upper electrical basic input and output system;
printing a system log in response to the basic input and output system being powered on or powered back on, and continuously acquiring and storing the system log from the basic input and output system by using a storage chip;
responding to a hard reset type data ending keyword printed by a basic input and output system in a system log and sending a reset instruction to a power supply control chip;
and powering off the basic input and output system in response to the power supply control chip receiving the reset instruction, and powering on the basic input and output system again after a preset delay.
In some embodiments, the hard reset data is memory bit width margin test data.
In some embodiments, the steps further comprise: before a hardware switch is used for sending a test enabling instruction to a test control chip, a memory bit width allowance tool and a serial port debugging mode of a basic input and output system are activated; the system log comprises memory bit width allowance test data.
In some embodiments, using the memory chip to continuously obtain and store the system log from the bios comprises: and outputting a system log comprising memory bit width allowance test data by the basic input and output system based on the memory bit width allowance tool, and acquiring and storing the system log by using a memory chip in a serial port debugging mode.
In some embodiments, the steps further comprise: a hardware switch is used for sending a test stopping instruction to a test control chip, so that the test control chip controls a storage chip to stop the automatic data collection function to power off a basic input and output system;
and reading the system log from the storage chip, and intercepting the hard reset data from the system log by using the hard reset data start keyword and the hard reset data end keyword.
In some embodiments, the hardware switch is a flip cap; the hardware switch is used for sending a test enabling instruction to the test control chip, so that the test control chip controls the storage chip to enable the data automatic collection function to enable the electrical basic input and output system to comprise: sending a high level to a test control chip by using a jump cap, so that the test control chip sends the high level to a hard reset type data enabling end of a storage chip; the method for sending a test stopping instruction to a test control chip by using a hardware switch to enable the test control chip to control a storage chip to stop the automatic data collection function so as to power off a basic input and output system comprises the following steps: and sending a low level to the test control chip by using the jump cap, so that the test control chip sends the low level to the hard reset type data enabling end of the storage chip.
In some embodiments, the steps further comprise: the hard reset data or the system log is output to the out-of-band manager in response to the memory chip obtaining a read instruction for the hard reset data from the out-of-band manager.
In some embodiments, the steps further comprise: when the test control chip controls the storage chip to start the data automatic collection function to power up the basic input and output system, the test control chip sends a false triggering insurance instruction to the power supply control chip; the power-down basic input output system in response to the power supply control chip receiving the reset instruction includes: and powering off the basic input and output system in response to the power supply control chip simultaneously receiving the reset instruction and the false triggering insurance instruction.
In some embodiments, the steps further comprise: the memory chip is reset to clear all system logs stored in the memory chip in response to the test control chip detecting that the total size of the system logs stored in the memory chip has reached or exceeded a storage security threshold.
It can be seen from the foregoing embodiments that, in the test apparatus for hard reset data provided in the embodiments of the present invention, a test enabling instruction is sent to a test control chip by using a hardware switch, so that the test control chip controls a storage chip to enable an automatic data collection function to implement an electrical basic input/output system; printing a system log in response to the basic input and output system being powered on or powered back on, and continuously acquiring and storing the system log from the basic input and output system by using a storage chip; responding to a hard reset type data ending keyword printed by a basic input and output system in a system log and sending a reset instruction to a power supply control chip; the technical scheme that the power supply control chip powers off the basic input and output system in response to the fact that the power supply control chip receives the reset instruction, and powers on the basic input and output system again after the preset time delay is achieved can automatically execute RMT, liberate manpower, improve efficiency and analyze memory performance in real time.
It should be particularly noted that the above-mentioned embodiment of the apparatus employs the embodiment of the hard-reset data testing method to specifically describe the working process of each module, and those skilled in the art can easily think that these modules are applied to other embodiments of the hard-reset data testing method. Of course, since the steps in the embodiment of the hard reset data test method can be mutually intersected, replaced, added, or deleted, these reasonable permutations and combinations should also fall within the scope of the present invention, and should not limit the scope of the present invention to the embodiment.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant only to be exemplary, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (9)
1. A method for testing hard reset data is characterized by comprising the following steps:
a hardware switch is used for sending a test enabling instruction to a test control chip, so that the test control chip controls a storage chip to enable an automatic data collection function and an upper power basic input and output system;
printing a system log in response to the basic input and output system being powered on or powered back on, and continuously acquiring and storing the system log from the basic input and output system by using the storage chip;
responding to the basic input and output system to print out a hard reset type data end keyword in the system log and sending a reset instruction to a power supply control chip;
powering off the basic input and output system in response to the power supply control chip receiving the reset instruction, and powering back on the basic input and output system after a preset delay;
and the hard reset data is memory bit width allowance test data.
2. The method of claim 1, further comprising: before a hardware switch is used for sending a test enabling instruction to a test control chip, a memory bit width margin tool and a serial port debugging mode of the basic input and output system are activated; the system log comprises memory bit width allowance test data.
3. The method of claim 2, wherein continuously obtaining and storing the system log from the bios using the memory chip comprises: and outputting a system log comprising the memory bit width allowance test data by the basic input and output system based on the memory bit width allowance tool, and acquiring and storing the system log by using the memory chip through the serial port debugging mode.
4. The method of claim 1, further comprising:
sending a test stopping instruction to the test control chip by using the hardware switch, so that the test control chip controls the storage chip to stop the automatic data collection function to power off the basic input and output system;
and reading the system log from the storage chip, and intercepting the hard reset data from the system log by using a hard reset data start keyword and a hard reset data end keyword.
5. The method of claim 4, wherein the hardware switch is a flip cap; the hardware switch is used for sending a test enabling instruction to the test control chip, so that the test control chip controls the memory chip to enable the automatic data collection function and the power-on basic input and output system, and the method comprises the following steps: sending a high level to the test control chip by using the jump cap, so that the test control chip sends the high level to a hard reset type data enabling end of a storage chip;
the step of sending a test disabling instruction to the test control chip by using the hardware switch, so that the test control chip controls the storage chip to disable the automatic data collection function to power off the basic input output system comprises the following steps: and sending a low level to the test control chip by using the jump cap, so that the test control chip sends the low level to a hard reset type data enabling end of the storage chip.
6. The method of claim 4, further comprising:
outputting the hard reset data or the system log to an out-of-band manager in response to the memory chip obtaining a read instruction for the hard reset data from the out-of-band manager.
7. The method of claim 1, further comprising: when the test control chip controls the storage chip to start the data automatic collection function to power up the basic input and output system, the test control chip sends a false triggering insurance instruction to the power supply control chip;
powering down the basic input output system in response to the power control chip receiving the reset instruction includes: powering down the BIOS in response to the power control chip receiving the reset command and the false trigger safing command simultaneously.
8. The method of claim 1, further comprising:
resetting the memory chip to clear all of the system logs stored in the memory chip in response to the test control chip detecting that the total size of the system logs stored in the memory chip has reached or exceeded a storage security threshold.
9. A hard reset data testing apparatus, comprising:
a processor;
a controller storing program code executable by the processor, the processor performing the following steps when executing the program code:
a hardware switch is used for sending a test enabling instruction to a test control chip, so that the test control chip controls a storage chip to enable an automatic data collection function and an upper power basic input and output system;
printing a system log in response to the basic input and output system being powered on or powered back on, and continuously acquiring and storing the system log from the basic input and output system by using the storage chip;
responding to a hard reset type data end keyword printed out in the system log by the basic input and output system, and sending a reset instruction to a power supply control chip;
powering off the basic input and output system in response to the power supply control chip receiving the reset instruction, and powering back on the basic input and output system after a preset delay;
and the hard reset data is memory bit width allowance test data.
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