CN113439338A

CN113439338A - Display substrate and preparation method thereof

Info

Publication number: CN113439338A
Application number: CN202080000249.6A
Authority: CN
Inventors: 黄炜赟; 邱远游; 肖星亮; 黄耀; 刘聪; 王彬艳
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2020-01-23
Filing date: 2020-01-23
Publication date: 2021-09-24
Also published as: WO2021147082A1

Abstract

A display substrate and a method for manufacturing the same are provided. The display substrate has a first side for displaying and a second side opposite to the first side, the display area of the display substrate comprises a first display area (10) and a second display area (20) at least partially surrounding the first display area (10); the display substrate further comprises at least one first connection trace (15), the first connection trace (15) comprises a first part (15A) located in the first display area (10) and a second part (15B) located in the second display area (20) which are electrically connected with each other, and the first part (15A) comprises a first light-transmitting trace layer; the first display area (10) comprises a plurality of first sub-pixels which are arranged in an array mode, each first sub-pixel comprises a first light-emitting device, and a first electrode sub-layer (111A) of a first electrode structure (111) of each first light-emitting device is arranged on the same layer as and electrically connected with the first light-transmitting wiring layer, so that the preparation process of the display substrate can be simplified.

Description

Display substrate and preparation method thereof

Technical Field

Embodiments of the present disclosure relate to a display substrate and a method of manufacturing the same.

Background

At present, display screens for electronic devices are being developed in large-screen and full-screen directions to provide users with better visual experience. Taking electronic products such as mobile phones and tablet computers as examples, the electronic devices need to combine components such as a camera and a light sensor, and these components usually occupy the display area of the display screen, so that it is difficult to realize a full screen design of the display screen.

Disclosure of Invention

At least one embodiment of the present disclosure provides a display substrate including a first side for displaying and a second side opposite to the first side, the display substrate including: a display area, wherein the display area comprises a first display area and a second display area at least partially surrounding the first display area, the first display area allowing at least partial transmission of light from the first side to the second side; the display substrate further comprises at least one first connecting wire in the first display area and the second display area, wherein the first connecting wire comprises a first part and a second part, the first part is electrically connected with the second part, the first part is located in the first display area, the second part is located in the second display area, and the first part comprises a first light-transmitting wire layer; the first display area comprises a plurality of first sub-pixels arranged in an array, each first sub-pixel comprises a first light-emitting device, each first light-emitting device comprises a first electrode structure, a second electrode structure and a first light-emitting layer arranged between the first electrode structure and the second electrode structure, each first electrode structure comprises a first electrode sublayer, and the first electrode sublayers and the first light-transmitting wiring layers are arranged on the same layer and electrically connected.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the at least one first connection trace includes a plurality of first connection traces; the second display area comprises a plurality of first pixel circuits which are electrically connected with the first electrode structures of the first light-emitting devices through the first connecting wires respectively so as to be used for driving the first light-emitting devices.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the second portion includes a second light-transmitting wiring layer, and the second light-transmitting wiring layer and the first light-transmitting wiring layer are disposed on the same layer and integrally connected.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the display substrate includes a substrate, the second light-transmitting wiring layer and the first electrode sub-layer are located on the substrate, the second portion further includes a first metal wiring layer located on a side of the second light-transmitting wiring layer away from the substrate, the first electrode structure further includes a second electrode sub-layer located on a side of the first electrode sub-layer away from the substrate, and the second electrode sub-layer and the first metal wiring layer are disposed on the same layer.

For example, in the display substrate provided in at least one embodiment of the present disclosure, the second portion further includes an anti-oxidation protection layer located on a side of the first metal routing layer away from the substrate, the first electrode structure further includes a third electrode sublayer located on a side of the second electrode sublayer away from the substrate, and the third electrode sublayer and the anti-oxidation protection layer are disposed on the same layer.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the first electrode structure is a first anode structure, and the second electrode structure is a first cathode structure; the material of the first electrode sub-layer comprises indium tin oxide, the material of the second electrode sub-layer comprises silver or a silver alloy, and the material of the third electrode sub-layer comprises indium tin oxide.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the second portion includes a second metal routing layer, and the second metal routing layer is disposed in a different layer from the first light-transmitting routing layer and is electrically connected to the first light-transmitting routing layer through a via hole.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the second display region further includes a plurality of second sub-pixels, each of the second sub-pixels includes a second light emitting device and a second pixel circuit electrically connected to the second light emitting device, the second pixel circuit is configured to drive the second light emitting device, and the plurality of second pixel circuits are arranged in a first array in the second display region.

For example, in the display substrate provided by at least one embodiment of the present disclosure, in the second display region, the plurality of first pixel circuits are dispersedly disposed in the first array, and are arranged with the plurality of second pixel circuits as a second array.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the second light emitting device includes a second anode structure, a second cathode structure, and a second light emitting layer between the second anode structure and the second cathode structure, and the second anode structure is electrically connected to the second pixel circuit through a via hole.

For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display region further includes a third display region at least partially surrounding the second display region, the third display region includes a plurality of third sub-pixels arranged in an array, each of the third sub-pixels includes a third light emitting device and a third pixel circuit electrically connected to the third light emitting device, the third pixel circuit is configured to drive the third light emitting device, the third light emitting device includes a third anode structure, a third cathode structure and a third light emitting layer between the third anode structure and the third cathode structure, and the third anode structure is electrically connected to the third pixel circuit through a via.

For example, in a display substrate provided by at least one embodiment of the present disclosure, the display substrate includes a substrate, the first display region further includes a transparent support layer on the substrate, and the first light emitting device is located on a side of the transparent support layer away from the substrate.

For example, in a display substrate provided in at least one embodiment of the present disclosure, the first pixel circuit includes a thin film transistor and a storage capacitor, where the thin film transistor includes an active layer, a gate electrode, and source and drain electrodes; the storage capacitor comprises a first capacitor polar plate and a second capacitor polar plate, the active layer is arranged on the substrate base plate, one side of the active layer, which is far away from the substrate base plate, is provided with a first grid insulating layer, the grid electrode and the first capacitor polar plate are arranged on the same layer of the first grid insulating layer, which is far away from the substrate base plate, one side of the grid electrode and the first capacitor polar plate, which is far away from the substrate base plate, is provided with a second grid insulating layer, the second capacitor polar plate is arranged on one side of the second grid insulating layer, which is far away from the substrate base plate, one side of the second capacitor polar plate, which is far away from the substrate base plate, is provided with an interlayer insulating layer, the source and drain electrodes are arranged on one side of the interlayer insulating layer, which is far away from the substrate base plate, and are electrically connected with the active layer through via holes in the first grid insulating layer, the second grid insulating layer and the interlayer insulating layer, a planarization layer is arranged on one side of the source and drain electrodes, which is far away from the substrate; the transparent support layer is disposed on the same layer as at least one of the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the planarization layer.

For example, at least one embodiment of the present disclosure provides a display substrate further comprising a sensor, wherein the sensor is disposed on the second side of the display substrate, and an orthographic projection of the sensor on the substrate at least partially overlaps the first display area, and is configured to receive light from the first side.

At least one embodiment of the present disclosure provides a method of manufacturing a display substrate having a first side for display and a second side opposite to the first side, the method including: forming a display area comprising a first display area and a second display area at least partially surrounding the first display area, the first display area allowing at least partial transmission of light from the first side to the second side; forming at least one first connecting wire in the first display area and the second display area, wherein the first connecting wire comprises a first part and a second part, the first part is electrically connected with the second part, the first part is located in the first display area, the second part is located in the second display area, and the first part comprises a first light-transmitting wire layer; and forming a plurality of first sub-pixels arranged in an array manner in the first display area, wherein each first sub-pixel comprises a first light-emitting device, the first light-emitting device comprises a first electrode structure, a second electrode structure and a first light-emitting layer between the first electrode structure and the second electrode structure, the first electrode structure comprises a first electrode sub-layer, and the first electrode sub-layer and the first light-transmitting wiring layer are formed on the same layer and are electrically connected.

For example, in the method for manufacturing a display substrate according to at least one embodiment of the present disclosure, the at least one first connection trace includes a plurality of first connection traces; the preparation method further comprises the following steps: and forming a plurality of first pixel circuits in the second display area, wherein the plurality of first pixel circuits are electrically connected with the first electrode structures of the plurality of first light-emitting devices through the plurality of first connecting wires respectively so as to drive the plurality of first light-emitting devices.

For example, in a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure, forming the second portion of the first connection trace includes: and forming a second light-transmitting wiring layer, wherein the second light-transmitting wiring layer and the first light-transmitting wiring layer are formed on the same layer and are integrally connected.

For example, the method for manufacturing a display substrate according to at least one embodiment of the present disclosure further includes: providing a substrate, wherein the second light-transmitting trace layer and the first electrode sub-layer are formed on the substrate, and the forming of the second portion of the first connection trace further comprises: and forming a first metal routing layer on one side of the second light-transmitting routing layer, which is far away from the substrate, and forming a second electrode sublayer on one side of the first electrode sublayer, which is far away from the substrate, wherein the second electrode sublayer and the first metal routing layer are formed on the same layer.

For example, in a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure, forming the second portion of the first connection trace further includes: and forming an anti-oxidation protective layer on one side of the first metal wiring layer, which is far away from the substrate, and forming a third electrode sublayer on one side of the second electrode sublayer, which is far away from the substrate, wherein the third electrode sublayer and the anti-oxidation protective layer are formed on the same layer.

For example, in a method for manufacturing a display substrate provided in at least one embodiment of the present disclosure, forming the first connection trace and the first electrode structure includes: sequentially depositing a first electrode material layer, a second electrode material layer and a third electrode material layer in the first display area and the second display area through a mask plate; etching away at least part of the third electrode material layer and part of the second electrode material layer in the first display region by using a first wet etching process; and etching away the remaining second electrode material layer in the portion of the first display region using a second wet etching process.

For example, in the method for manufacturing a display substrate provided in at least one embodiment of the present disclosure, forming the first pixel circuit includes forming a thin film transistor and a storage capacitor, where the thin film transistor includes an active layer, a gate electrode, and a source/drain electrode; the storage capacitor comprises a first capacitor polar plate and a second capacitor polar plate, wherein the active layer is formed on a substrate, a first grid insulating layer is formed on one side of the active layer, which is far away from the substrate, the grid electrode and the first capacitor polar plate are formed on the same layer on one side of the first grid insulating layer, which is far away from the substrate, a second grid insulating layer is formed on one side of the grid electrode and the first capacitor polar plate, which is far away from the substrate, the second capacitor polar plate is formed on one side of the second grid insulating layer, which is far away from the substrate, an interlayer insulating layer is formed on one side of the second capacitor polar plate, which is far away from the substrate, the source and drain electrodes are formed on one side of the interlayer insulating layer, which is far away from the substrate, and are electrically connected with the active layer through via holes in the first grid insulating layer, the second grid insulating layer and the interlayer insulating layer, forming a planarization layer on one side of the source and drain electrodes far away from the substrate; forming the first display region further comprises: forming a transparent support layer between the substrate base plate and the first light emitting device, wherein the transparent support layer is formed in the same layer as at least one of the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the planarization layer.

For example, the method for manufacturing a display substrate according to at least one embodiment of the present disclosure further includes: providing a sensor and bonding the sensor to a second side of the display substrate, wherein an orthographic projection of the sensor on the substrate at least partially overlaps the first display area and is configured to receive the light from the first side.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic plan view of a display substrate;

FIG. 1B is a partially enlarged view of a display substrate;

FIG. 2 is a schematic cross-sectional view of the display substrate of FIG. 1B along line A-A;

fig. 3 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure;

FIG. 4 is a schematic cross-sectional view of the display substrate of FIG. 3 taken along line B-B;

fig. 5 is a schematic plan view of a first display region and a second display region in a display substrate according to at least one embodiment of the disclosure;

FIG. 6 is another schematic cross-sectional view of the display substrate of FIG. 3 along line B-B;

FIG. 7 is another schematic cross-sectional view of the display substrate of FIG. 3 along line B-B;

fig. 8 is another schematic plan view of a first display region and a second display region in a display substrate according to at least one embodiment of the present disclosure;

fig. 9 is a schematic plan view of a sub-pixel arrangement in a display area of a display substrate according to at least one embodiment of the present disclosure;

fig. 10 is a schematic plan view illustrating routing layout in a display area of a display substrate according to at least one embodiment of the present disclosure;

fig. 11 is another schematic plan view illustrating routing layout in a display area of a display substrate according to at least one embodiment of the present disclosure;

fig. 12 is a further schematic plan view of a first display region and a second display region of a display substrate according to at least one embodiment of the disclosure;

fig. 13 is a schematic cross-sectional view of a second display region in a display substrate according to at least one embodiment of the present disclosure;

fig. 14 is a schematic cross-sectional view of a third display region in a display substrate according to at least one embodiment of the present disclosure;

fig. 15A-15B are schematic cross-sectional views illustrating a display substrate during a manufacturing process according to at least one embodiment of the present disclosure;

fig. 16 is a schematic cross-sectional view of another display substrate provided in at least one embodiment of the present disclosure during a manufacturing process; and

fig. 17 is a further schematic plan view of a first display region and a second display region in a display substrate according to at least one embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In order to realize a full screen design of the display screen, in some embodiments, a part of the display area for mounting components such as a sensor (e.g., an image sensor, an infrared sensor) may be designed as a light-transmitting display area, so that the light-transmitting display area may provide convenience for mounting components such as a sensor while realizing a display function.

For example, fig. 1A is a schematic plan view of a display substrate, fig. 1B is a schematic partial enlarged view of the display substrate shown in fig. 1A, and fig. 2 is a schematic sectional view of the display substrate shown in fig. 1B along a line a-a. As shown in fig. 1A, 1B and 2, the display region of the display substrate includes a light-transmissive display region 1, a peripheral display region 2 and a main body display region 3.

For example, the main display region 3 is a main display region having a high resolution (PPI, Pixel Per inc), that is, sub-pixels for display having a high density are arranged in the main display region 3. Each sub-pixel includes a light emitting device and a pixel circuit driving the light emitting device. The light-transmissive display region 1 may allow light incident from the display side of the display substrate to pass through the display substrate to the back side of the display substrate for normal operation of components such as sensors located on the back side of the display substrate. The light-transmissive display region 1 and the peripheral display region 2 also include a plurality of sub-pixels for display. However, since the pixel circuits of the sub-pixels are normally opaque, in order to ensure the light transmittance of the light-transmissive display region 1, the pixel circuits of the sub-pixels (e.g., as indicated by the square in the light-transmissive display region 1 in fig. 1B) in the light-transmissive display region 1 may be disposed in the peripheral display region 2, as indicated by the gray square in the peripheral display region 2, thereby occupying part of the space of the peripheral display region 2, while the remaining space of the peripheral display region 2 is used for disposing the sub-pixels of the peripheral display region 2, e.g., each white square in the peripheral display region 2 represents one sub-pixel. At this time, the sub-pixels (white boxes in fig. 1B) of the peripheral display region 2 and the pixel circuits (gray boxes in fig. 1B) of the sub-pixels in the light-transmissive display region 1 are arranged in an array in the peripheral display region 2. Thus, the resolution of the light-transmitting display region 1 and the peripheral display region 2 is lower than that of the main display region 3, that is, the density of the sub-pixels arranged for display in the light-transmitting display region 1 and the peripheral display region 2 is lower than that of the main display region 3.

As shown in fig. 2, the light emitting device 4 of one sub-pixel in the light-transmissive display region 1 includes an anode 4A, a cathode 4C, and a light emitting layer 4B between the anode 4A and the cathode 4C, and the anode 4A is connected to the pixel circuit 5 in the peripheral display region 2 by a conductive wiring.

In a specific embodiment, the conductive leads may be metal leads, for example, the conductive leads may be made of the same material as a source-drain electrode metal in a pixel circuit of the sub-pixel, or may be transparent traces (e.g., ITO traces) 6 electrically connected to the pixel circuits 5 in the peripheral display region 2, so that the pixel circuits 5 in the peripheral display region 2 may be used to drive the light emitting devices 4 in the light-transmitting display region 1. Since the transparent trace 6 has high light transmittance, the light-transmitting display region 1 can also have high light transmittance. Thus, components such as the sensor 7 provided on the back side of the display substrate can receive light transmitted from the display side of the display substrate through the light-transmitting display region 1 to perform normal operation.

In the above case, the transparent trace 6 needs to extend from the pixel circuit 5 of the peripheral display region 2 to the light emitting device 4 of the transmissive display region 1, so that at least a portion of the transparent trace 6 has a longer length, for example, the length thereof spans more than 2 sub-pixel regions, on the other hand, compared to the source/drain electrode material, such as Ti/Al/Ti, or any one of them, or a combination of both; or other electrode materials such as copper, molybdenum, magnesium, silver, or a combination of at least two materials, and the like. The material of the transparent wire 6 has a large resistance, and the manufacturing process thereof is prone to generate deviation, so that the overall resistance of the transparent wire 6 is large, and therefore, the speed of the pixel circuit 5 transmitting an electrical signal to the sub-pixels in the transparent display area 1 is low, which causes the sub-pixels in the transparent display area 1 to be driven asynchronously with the sub-pixels in the peripheral display area 2 and the main display area 3, and affects the display effect of the display area. In the manufacturing process, a transparent trace 6 is usually formed by a one-step patterning process, and then an insulating layer 6A on the transparent trace 6 is formed by the one-step patterning process, where a via hole is formed in the insulating layer 6A. Thereafter, an anode 4A is formed on the insulating layer 6A, and the anode 4A is electrically connected to the transparent trace 6 through the via hole in the insulating layer 6A. In the preparation process, a plurality of patterning processes are required to form the structures such as the transparent wiring 6 and the anode 4A, so that the preparation process becomes complicated.

At least one embodiment of the present disclosure provides a display substrate having a first side for displaying and a second side opposite the first side, the display substrate comprising a display area including a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side to be at least partially transmitted to the second side; the display substrate further comprises at least one first connecting wire in the first display area and the second display area, the first connecting wire comprises a first part and a second part, the first part and the second part are electrically connected, the first part is located in the first display area, the second part is located in the second display area, and the first part comprises a first light-transmitting wiring layer; the first display area comprises a plurality of first sub-pixels arranged in an array mode, each first sub-pixel comprises a first light-emitting device, each first light-emitting device comprises a first electrode structure, a second electrode structure and a first light-emitting layer between the first electrode structure and the second electrode structure, each first electrode structure comprises a first electrode sublayer, and the first electrode sublayers and the first light-transmitting wiring layers are arranged on the same layer and electrically connected. In the preparation process of the display substrate, the first electrode sub-layer and the first light-transmitting wiring layer can be formed by adopting the same material layer and through the same composition process, so that the preparation process of the display substrate is simplified.

At least one embodiment of the present disclosure provides a display substrate and a method of manufacturing the same, the display substrate having a first side for displaying and a second side opposite to the first side, the display substrate including a display area, the display area including a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side to be at least partially transmitted to the second side; the display substrate further comprises at least one first connecting wire in the first display area and the second display area, the first connecting wire comprises a first part and a second part, the first part and the second part are electrically connected with each other and are located in the first display area, the first part comprises a first light-transmitting wiring layer, and the second part comprises a metal wiring layer. The first connecting trace in the display substrate has a lower resistance.

The display substrate and the method for manufacturing the same according to some embodiments of the present disclosure are described below with reference to several specific examples.

At least one embodiment of the present disclosure provides a display substrate, fig. 3 illustrates a schematic plan view of the display substrate, fig. 4 illustrates a schematic cross-sectional view of the display substrate in fig. 3 along a line B-B, and fig. 5 illustrates a schematic plan view of a first display region 10 and a second display region 20.

As shown in fig. 3 and 4, the display substrate has a first side for display (shown in fig. 4 as the upper side of the display substrate, i.e., the display side of the display substrate) and a second side opposite to the first side (shown in fig. 4 as the lower side of the display substrate). The display substrate comprises a display area comprising a first display area 10 and a second display area 20 at least partially surrounding the first display area 10, the first display area 10 allowing light from a first side to be at least partially transmitted to a second side, i.e. the first display area 10 is at least partially light transmissive for facilitating mounting of components like image sensors, infrared sensors, etc.

As shown in fig. 4, the display substrate further includes at least one first connection trace 15 in the first display region 10 and the second display region 20, the first connection trace 15 includes a first portion 15A located in the first display region 10 and a second portion 15B located in the second display region 20 that are electrically connected to each other, the first portion 15A includes a first light-transmissive routing layer to ensure light transmittance of the first display region 10, and the second portion 15B includes a metal routing layer.

For example, the material of the first light-transmitting routing layer may be a transparent conductive material, such as a transparent metal oxide, e.g., Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), and the material of the metal routing layer may include a metal material, e.g., silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti), or an alloy material thereof. Since the resistance of the metal routing layer is low, the first connection trace 15 can have a lower resistance than a trace including only a light-transmissive routing layer.

For example, as shown in fig. 4 and 5, the first display region 10 includes a plurality of first sub-pixels arranged in an array, each of the first sub-pixels includes a first light emitting device 11, the first light emitting device 11 includes a first electrode structure 111, a second electrode structure 113, and a first light emitting layer 112 between the first electrode structure 111 and the second electrode structure 113, the first electrode structure 111 includes a first electrode sublayer 111A, and the first electrode sublayer 111A is disposed on the same layer as and electrically connected to the first light-transmitting routing layer of the first portion 15A, for example, integrally connected, that is, the first electrode sublayer 111A is disposed on the same layer as and directly contacted to the first light-transmitting routing layer of the first portion 15A, so as to form an integral structure.

It should be noted that, in the embodiments of the present disclosure, the "same layer arrangement" means that two functional layers or structural layers are formed in the same layer and the same material in the hierarchical structure of the display substrate, that is, in the manufacturing process, the two functional layers or structural layers may be formed by the same material layer, and the required patterns and structures may be formed by the same patterning process. The primary patterning process includes, for example, processes of forming a photoresist, exposing, developing, etching, and the like.

Thus, in the embodiment of the present disclosure, the first electrode sub-layer 111A and the first light-transmitting routing layer of the first portion 15A may use the same material layer and be formed through the same patterning process, thereby simplifying the manufacturing process of the display substrate.

For example, in some embodiments, as shown in fig. 5, the first display region 10 includes a plurality of first sub-pixels arranged in an array, each of the first sub-pixels includes a first light emitting device 11, the display region includes a plurality of first connection traces 15, the second display region 20 includes a plurality of first pixel circuits D, and the plurality of first pixel circuits D are electrically connected to the first light emitting devices 11 of the plurality of first sub-pixels through the plurality of first connection traces 15, respectively, so as to drive the first light emitting devices 11 of the plurality of first sub-pixels. For example, in the embodiment shown in fig. 5, a plurality of first pixel circuits D correspond to the first light emitting devices 11 of a plurality of first sub-pixels one to one and are electrically connected through the first connecting trace 15, and at this time, one first pixel circuit D is used to drive the first light emitting device 11 of one first sub-pixel. For example, in other embodiments, one first pixel circuit D may be electrically connected to the first light emitting devices 11 of the first sub-pixels through the first connecting traces 15, and at this time, one first pixel circuit D may be used to drive the first light emitting devices 11 of the first sub-pixels. The embodiment of the present disclosure does not specifically limit the corresponding relationship between the first pixel circuit D and the first light emitting device 11 of the first sub-pixel.

For example, in some embodiments, the second portion 15B of the first connection trace 15 includes a second light-transmitting routing layer, and the second light-transmitting routing layer (i.e., the portion indicated by the mark 15B) and the first light-transmitting routing layer (i.e., the portion indicated by the mark 15A) are disposed on the same layer and integrally connected, i.e., the second light-transmitting routing layer, the first light-transmitting routing layer and the first electrode sub-layer 111A are disposed on the same layer and integrally connected, so that the manufacturing process of the display substrate can be simplified.

For example, in some embodiments, the first electrode structure 111 is a first anode structure of the first light emitting device 11, and the second electrode structure 113 is a first cathode structure of the first light emitting device 11. When a voltage difference is present between the first anode structure and the first cathode structure, the first light emitting layer 112 between the first anode structure and the first cathode structure can emit light. For example, an orthographic projection of the first light emitting layer 112 on the first anode structure is located inside the first anode structure, and an orthographic projection of the first light emitting layer 112 on the first cathode structure is located inside the first cathode structure, whereby the first anode structure and the first cathode structure can sufficiently drive the first light emitting layer 112 to emit light.

For example, in some embodiments, the first cathode structure may be a structure formed on the entire surface of the display substrate, and the first cathode structure may include, for example, a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), or the like. Since the first cathode structure can be formed as a thin layer, the first cathode structure 113 has good light transmittance.

For example, as shown in fig. 4, the first anode structure may include a multi-layered stack structure. For example, the first anode structure may include a second electrode sublayer 111B and a third electrode sublayer 111C stacked with the first electrode sublayer 111A in addition to the first electrode sublayer 111A, whereby the first anode structure has a three-layer stacked structure. Of course, in other embodiments of the present disclosure, the first anode structure may also be a single-layer structure, a double-layer structure, and the like, and the embodiments of the present disclosure do not limit the specific form of the first anode structure.

For example, the first electrode sublayer 111A, the second electrode sublayer 111B, and the third electrode sublayer 111C are all planar electrodes, the planar shapes and sizes of the first electrode sublayer 111A, the second electrode sublayer 111B, and the third electrode sublayer 111C are substantially the same (i.e., the orthogonal projection shapes and sizes of the first electrode sublayer 111A, the second electrode sublayer 111B, and the third electrode sublayer 111C on the substrate 14 are substantially the same), and any two adjacent electrode sublayers are in direct and complete contact with each other. At this time, the orthographic projection of the first light emitting layer 112 on any one electrode sublayer in the first anode structure is located inside the electrode sublayer.

For example, in some embodiments, the material of the first electrode sub-layer 111A may include Indium Tin Oxide (ITO), the material of the second electrode sub-layer 111B may include silver (Ag) or a silver alloy, and the material of the third electrode sub-layer 111C may include Indium Tin Oxide (ITO). Thus, the first anode structure has an ITO/Ag/ITO three-layer stack structure.

For example, the display substrate includes a substrate 14, and a first light-transmitting wiring layer, a second light-transmitting wiring layer, and a first electrode sub-layer 111A are located on the substrate 14. In the embodiment shown in fig. 4, the second portion 15B of the first connection trace 15 may comprise only a second light-transmissive trace layer. For example, in other embodiments, as shown in fig. 6, the second portion 15B of the first connection trace 15 may further include a first metal routing layer 16 located on a side of the second light-transmissive routing layer away from the substrate base plate 14. The arrangement of the metal wiring layer 16 can reduce the resistance of the first connection trace 15.

For example, the material of the metal routing layer 16 may include a metal material such as silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti), or an alloy material thereof. Therefore, the metal wiring layer 16 has higher conductivity, and the resistance of the first connection trace 15 can be significantly reduced.

For example, the second electrode sub-layer 111B is located on a side of the first electrode sub-layer 111A away from the substrate 14, and the second electrode sub-layer 111B is disposed on the same layer as the first metal wiring layer 16. Thus, the second electrode sub-layer 111B and the first metal wiring layer 16 may be formed by the same patterning process using the same material layer, so as to simplify the manufacturing process of the display substrate.

For example, in some embodiments, the second portion 15B may further include an oxidation protection layer 17 located on a side of the first metal routing layer 16 away from the substrate 14, and the oxidation protection layer 17 may prevent the metal routing layer 16 from being oxidized, so as to ensure that the metal routing layer 16 maintains high conductivity; in addition, the oxidation prevention protective layer 17 can also enhance adhesion of the metal wiring layer 16 and an insulating layer 146 (also a pixel defining layer, described later) formed thereon to prevent poor connection between the metal wiring layer 16 and the insulating layer 145.

For example, in some embodiments, the oxidation protection layer 17 may be made of a transparent oxide material, such as ITO, IZO, or other transparent conductive oxide materials, so as to further reduce the resistance of the first connection trace 15.

For example, the third electrode sublayer 111C is located on the side of the second electrode sublayer 111B away from the substrate 14, and the third electrode sublayer 111C and the oxidation prevention protective layer 17 are disposed in the same layer. At this time, the third electrode sublayer 111C and the oxidation protection layer 17 may be formed by using the same material layer and through the same patterning process, so as to simplify the manufacturing process of the display substrate.

Thus, in the above embodiments of the present disclosure, the second portion 15B of the first connection trace 15 is formed as a three-layer stacked conductive structure, which can significantly reduce the resistance of the first connection trace 15. When the plurality of first connecting wires 15 are respectively used for transmitting the driving signals to the plurality of first light emitting devices 11, the above design of the first connecting wires 15 can also improve the uniformity of the current flowing through the plurality of first connecting wires 15, thereby improving the display effect of the display substrate. Also, the three-layer stack structure of the second portion 15B may be formed in the same layer as the three-layer stack structure of the first anode structure, thereby also simplifying the manufacturing process of the display substrate.

For example, in some embodiments, as shown in fig. 4, the second portion 15B of the first connection trace 15 may further include an anti-oxidation protection layer 17 stacked with the metal routing layer 16, and the anti-oxidation protection layer 17 may prevent the metal routing layer 16 from being oxidized, so as to ensure that the metal routing layer 16 maintains a high conductive performance; in addition, the oxidation prevention protective layer 17 can also enhance the adhesion between the metal wiring layer 16 and the insulating layer 145 formed thereon, thereby preventing poor connection between the metal wiring layer 16 and the insulating layer 145. For example, in some embodiments, the oxidation protection layer 17 may be made of a transparent oxide material, such as ITO, IZO, or other transparent conductive oxide materials, so as to further reduce the resistance of the first connection trace 15.

For example, in some embodiments, as shown in fig. 4 and 6, the first light emitting device 11 includes a first anode structure 111, a first cathode structure 113, and a first light emitting layer 112 between the first anode structure 111 and the first cathode structure 113, and the first portion 15A of the first connection trace 15 is electrically connected with the first anode structure 111 through a via. For example, an insulating layer 145 is disposed on the first connection trace 15, the insulating layer 145 has a via hole 145A in the first display region 10, and the first portion 15A of the first connection trace 15 is electrically connected to the first anode structure 111 through the via hole 145A in the insulating layer 145.

For example, in some embodiments, the first anode structure 111 includes multiple anode sublayers, such as the three anode sublayers shown in the figure. For example, the three anode sublayers are an ITO/Ag/ITO three-layer laminated structure. For example, the first cathode structure 113 may be a structure formed on the entire surface of the display substrate, and the first cathode structure 113 may include a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag), for example. Since the first cathode structure 113 can be formed as a thin layer, the first cathode structure 113 has good light transmittance.

For example, in other embodiments, the second portion 15B of the first connection trace 15 can also adopt a different structure from the embodiments of fig. 4 and 6. For example, the second portion 15B of the first connection trace 15 may not include the second light-transmitting trace layer, but only include the metal trace layer. For example, as shown in fig. 7, in some embodiments, the second portion 15B includes a second metal routing layer disposed differently from the first light-transmissive routing layer of the first portion 15A and electrically connected by a via. For example, there is an insulating layer 145 over the second metal routing layer, there is a via 145A in the insulating layer 145, and the second metal routing layer is electrically connected to the first light-transmissive routing layer of the first portion 15A through the via 145A of the insulating layer 145.

For example, fig. 8 shows a plan view of the first display area 10 and the second display area 20 in the above-described case. For example, as shown in fig. 8, the second display area 20 has a via area (an area outlined by a dashed frame) at a position close to the first display area 10, and the first portion 15A and the second portion 15B of the first connection traces 15 can be electrically connected through a plurality of vias 145A disposed in the via area, respectively.

For example, in the embodiments shown in fig. 7 and 8, the second metal routing layer of the second portion 15B may include a metal material such as silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti), or an alloy thereof, so that the second metal routing layer has higher conductivity and can also significantly reduce the resistance of the first connection routing 15.

For example, fig. 9 shows a pattern of the first subpixel arrangement in the first display region. For example, the second sub-pixels in the second display region 20 also have the sub-pixel arrangement rule as shown in fig. 9. In this embodiment, each four sub-pixels constitute one pixel unit, each sub-pixel has a different shape, and accordingly, the anode structure of the light emitting device of each sub-pixel also has a different shape. For example, as shown in fig. 9, in one pixel unit of the first display region 10, the first anode structures 111 of the first light emitting devices of each first sub-pixel have different shapes and are arranged as shown in fig. 9.

For example, fig. 10 shows a connection manner of the data lines D in the case where the first sub-pixel in the first display region 10 and the second sub-pixel in the second display region 20 are arranged in the sub-pixels as described above. As shown in fig. 10, the data lines D are routed at the boundary of the second display region 20 near the first display region 10, and the pixel circuits of the sub-pixels located in the same column are electrically connected to the same data line D in the first display region 10 and the second display region 20. For example, in the embodiment shown in fig. 10, the first pixel circuit in the second display area 20 shown by a gray square is electrically connected to the light emitting device of the first left sub-pixel in the first display area 10 through the first connecting trace 15, and the pixel circuits of the sub-pixels (whether the first sub-pixel or the second sub-pixel) in the same column as the first left sub-pixel can be electrically connected through the routing of the data line D, so that the pixel circuits of the sub-pixels in the same column are electrically connected to the same data line. For example, a portion DA of the data line D (shown as a thick line portion horizontally extending from the upper side of the data line D in the drawing) may be disposed in a jumper manner, i.e., the portion DA of the data line D may be disposed in a different layer from other portions of the data line D. For example, when the arrangement density of the data lines D is large, the arrangement space of the data lines can be reduced by adopting a jumper design, thereby being more favorable for arrangement of routing.

For example, fig. 10 only shows the connection traces and data lines of one first sub-pixel in the first display area 10, and other first sub-pixels in the first display area 10 also have similar connection relationships, and the connection traces and data lines are not shown in fig. 10. For example, the area occupied by the gray box may have the first pixel circuits of the four first sub-pixels of one pixel unit, and at this time, the four first pixel circuits may be electrically connected to the four first sub-pixels of one pixel unit in the first display area 10 through the four first connection wirings 15, respectively.

For example, in some embodiments, the data lines D may be routed on one side of the second display area 20, for example, the routing on the upper side of the second display area 20 is shown in fig. 10. In other embodiments, as shown in fig. 11, the data lines D may also be wound on both the upper and lower sides of the second display area 20.

For example, as shown in fig. 11, in this embodiment, the pixel circuits of the first column of sub-pixels on the left side in the first display region 10 and the second display region 20 are electrically connected using the same data line D3 (the data line on the left side in the figure), and the pixel circuits of the second column of sub-pixels on the left side are electrically connected using the same data line D4 (the data line on the right side in the figure), at this time, the data lines are simultaneously routed on both the upper and lower sides of the second display region 20 to electrically connect the pixel circuits of the sub-pixels located in the same column, whereby the light emitting devices of the sub-pixels located in the same column can be driven by the same data line.

Similarly, the data line D3 and a portion DA of the data line D4 may also adopt a jumper design. For example, at the edge of the second display area 20, the data lines are densely arranged, so that the jumper design may be used for some data lines wound at the edge to save space and simplify the circuit arrangement.

Similarly, fig. 11 only shows the connection traces and data lines of the four first sub-pixels in the first display area 10, and other first sub-pixels in the first display area 10 also have similar connection relationships, and 11 is not shown in the figure. For example, the area occupied by the gray box may have the first pixel circuits of the four first sub-pixels of one pixel unit, and at this time, the four first pixel circuits may be electrically connected to the four first sub-pixels of one pixel unit in the first display area 10 through the four first connection wirings 15, respectively.

For example, as shown in fig. 12, the first subpixel of the third column on the left side of the first display region 10 is located in the same column as the second column of the second subpixel P in the second display region 20 above the first display region 10, and the first subpixel of the third column on the left side of the first display region 10 is driven by the first pixel circuit D in the first column in the second display region 20 above the first display region 10, at which time, the data line D may be electrically connected to the same data line through routing in the first column of the first pixel circuit D and the second column of the second subpixel P in the second display region 20, so that the pixel circuits of the subpixels located in the same column may be driven by the same data line.

For example, the pixel circuits of the sub-pixels located in the same row may be electrically connected to the same scan line, and thus the light emitting devices of the sub-pixels located in the same row may be driven by the same scan line. For example, as shown in fig. 12, the first light emitting device 11 of the first sub-pixel in the first row in the first display region 10 is electrically connected to one first pixel circuit D in the second display region 20 on the left side of the first display region 10, the light emitting device 11 of the second first sub-pixel in the first row in the first display region 10 is electrically connected to one first pixel circuit D in the second display region 20 on the upper side of the first display region 10, and the first pixel circuits D of the two first sub-pixels in the same row (the first row in the figure) can be electrically connected by a winding line of a scanning line G1 (a scanning line on the left side in the figure). Similarly, the first light emitting device 11 of the first sub-pixel in the third row in the first display region 10 is electrically connected to one first pixel circuit D in the second display region 20 on the left side of the first display region 10, the light emitting device 11 of the second first sub-pixel in the third row in the first display region 10 is electrically connected to one first pixel circuit D in the second display region 20 on the upper side of the first display region 10, and the first pixel circuits D of the two first sub-pixels in the same row (the third row in the figure) can be electrically connected by a wiring of the scanning line G2 (the scanning line on the right side in the figure). Thereby, the light emitting devices of the sub-pixels located in the same row can be driven by the same scanning line.

Therefore, in the embodiment of the disclosure, the pixel circuits of the sub-pixels located in the same column can be electrically connected to the same data line and the pixel circuits of the sub-pixels located in the same row can be electrically connected to the same scan line through the winding of the scan line and the data line, so as to simplify the driving control of each sub-pixel in the display panel.

For example, in fig. 12, the traces of different lines are respectively disposed in different trace layers, i.e., the traces of different lines are disposed in different layers. For example, in the figure, the first connecting trace 15 with the deepest color and the thickest line, the data line D with the deeper color and the thinner line, and the scan line G with the lightest color and the thinner line are respectively disposed on different layers, and thus different material layers are respectively used in the manufacturing process.

For example, in the display substrate illustrated in fig. 4, 6, and 7, as illustrated in fig. 5 and 8, the second display region 20 further includes a plurality of second sub-pixels P each including a second light emitting device and a second pixel circuit electrically connected to the second light emitting device, the second pixel circuit being configured to drive the second light emitting device; in the second display area 20, the plurality of second pixel circuits are arranged in a first array, i.e., an array in which gray squares are arranged in fig. 5 and 8. For example, in the direction perpendicular to the display substrate, the first connection trace 15 and the second sub-pixel P do not overlap.

For example, in some embodiments, in the second display region 20, a plurality of first pixel circuits D are dispersedly disposed in a first array and arranged with a plurality of second pixel circuits D in a second array, i.e., an array in which gray and white squares are arranged together in fig. 5 and 8.

For example, as shown in fig. 4, the first pixel circuit D for driving the first light emitting device 11 includes a thin film transistor 12 and a storage capacitor 13, the thin film transistor 12 includes an active layer 121, a gate electrode 122, source and drain electrodes (i.e., a source electrode 123 and a drain electrode 124), and the like, and the storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132.

For example, the active layer 121 is disposed on the substrate 14, a first gate insulating layer 141 is disposed on a side of the active layer 121 away from the substrate 14, the gate electrode 122 and the first capacitor plate 131 are disposed on a same layer on a side of the first gate insulating layer 141 away from the substrate 14, a second gate insulating layer 142 is disposed on a side of the gate electrode 122 and the first capacitor plate 131 away from the substrate 14, the second capacitor plate 132 is disposed on a side of the second gate insulating layer away from the substrate 14, an interlayer insulating layer 143 is disposed on a side of the second capacitor plate 132 away from the substrate 14, the source and drain electrodes are disposed on a side of the interlayer insulating layer 143 away from the substrate 14, and is electrically connected to the active layer 121 through via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143, and a planarization layer 144 is disposed on a side of the source-drain electrodes away from the substrate base plate 14 to planarize the first pixel circuit.

For example, fig. 13 shows a schematic cross-sectional view of a second display region 20, and as shown in fig. 13, the second display region 20 includes a second light emitting device 21 and a second pixel circuit driving the second light emitting device 21. For example, the second pixel circuit includes a thin film transistor 22, a storage capacitor 23, and the like. The second light emitting device 21 includes a second anode structure 211, a second cathode structure 213, and a second light emitting layer 212 between the second anode structure 211 and the second cathode structure 213, and the second anode structure 211 is electrically connected to the second pixel circuit through a via hole. For example, the second anode structure 211 may include a plurality of anode sublayers, for example, an ITO/Ag/ITO three-layer structure (not shown in the figure), and the embodiment of the disclosure does not limit the specific form of the second anode structure 211.

For example, the thin film transistor 22 includes an active layer 221, a gate electrode 222, and source and drain electrodes (i.e., a source electrode 223 and a drain electrode 224), and the storage capacitor 23 includes a first capacitor plate 231 and a second capacitor plate 232. For example, the active layer 221 is disposed on the substrate 14, a side of the active layer 221 away from the substrate 14 is provided with the first gate insulating layer 141, the gate electrode 222 and the first capacitor plate 231 are disposed on the same layer on a side of the first gate insulating layer 141 away from the substrate 14, a side of the gate electrode 222 and the first capacitor plate 231 away from the substrate 14 is provided with the second gate insulating layer 142, the second capacitor plate 232 is disposed on a side of the second gate insulating layer 142 away from the substrate 14, a side of the second capacitor plate 232 away from the substrate 14 is provided with the interlayer insulating layer 143, the source-drain electrodes are disposed on a side of the interlayer insulating layer 143 away from the substrate 14, and is electrically connected to the active layer 221 through via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143, and a planarization layer 144 is disposed on a side of the source-drain electrodes away from the substrate base plate 14 to planarize the second pixel circuit.

For example, the planarization layer 144 has a via hole 144A therein, and the second anode structure 211 is electrically connected to the source electrode 223 of the thin film transistor 22 through the via hole 144A in the planarization layer 144.

For example, in some embodiments, the source electrode 223 and the second anode structure 211 may further have a transition layer (not shown), which may be disposed on the same layer as the first connection trace 15.

For example, as shown in fig. 3, the display region further includes a third display region 30 at least partially surrounding the second display region 20, and the third display region 30 includes a plurality of third sub-pixels arranged in an array. For example, fig. 14 shows a schematic cross-sectional view of a third display region 30, and as shown in fig. 14, each third sub-pixel includes a third light emitting device 31 and a third pixel circuit electrically connected to the third light emitting device, and the third pixel circuit is configured to drive the third light emitting device 31. The third light emitting device 31 includes a third anode structure 311, a third cathode structure 313, and a third light emitting layer 312 between the third anode structure 311 and the third cathode structure 313, and the third anode structure 311 is electrically connected to the third pixel circuit through a via hole. For example, the third anode structure 311 may include a plurality of anode sublayers, for example, an ITO/Ag/ITO three-layer structure (not shown in the figure), and the embodiment of the disclosure does not limit the specific form of the third anode structure 311.

For example, the third pixel circuit includes a thin film transistor 32, a storage capacitor 33, and the like. For example, the thin film transistor 32 includes an active layer 331, a gate electrode 332, and source and drain electrodes (i.e., the source electrode 233 and the drain electrode 234), and the storage capacitor 33 includes a first capacitor plate 331 and a second capacitor plate 332. For example, the active layer 321 is disposed on the substrate 14, a side of the active layer 321 away from the substrate 14 is provided with the first gate insulating layer 141, the gate electrode 322 and the first capacitor plate 331 are disposed on the same layer on a side of the first gate insulating layer 141 away from the substrate 14, a side of the gate electrode 322 and the first capacitor plate 331 away from the substrate 14 is provided with the second gate insulating layer 142, the second capacitor plate 332 is disposed on a side of the second gate insulating layer 142 away from the substrate 14, a side of the second capacitor plate 332 away from the substrate 14 is provided with the interlayer insulating layer 143, the source and drain electrodes are disposed on a side of the interlayer insulating layer 143 away from the substrate 14, and is electrically connected to the active layer 321 through via holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143, and a planarization layer 144 is disposed on a side of the source-drain electrodes away from the substrate base plate 14 to planarize the third pixel circuit.

For example, the planarization layer 144 has a via hole 144B therein, and the third anode structure 311 is electrically connected to the source electrode 323 of the thin film transistor 32 through the via hole 144B in the insulating layer 145.

For example, in some embodiments, the source electrode 323 and the second anode structure 311 may further have a transition layer (not shown), which may be disposed at the same layer as the first connection trace 15.

For example, the first pixel circuit and the second pixel circuit in the second display region 20 are disposed at the same layer as the third pixel circuit in the third display region 30, and thus may be formed using the same patterning process in the manufacturing process. For example, the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144 are disposed at the same layer in the second display region 20 and the third display region 30, and are integrally connected in some embodiments, and thus the same reference numerals are used in the drawings.

For example, in some embodiments, as shown in fig. 4, 6 and 7, the first display area 10 further comprises a transparent support layer 18 on the substrate base 14, the first light emitting device 11 being located on a side of the transparent support layer 18 remote from the substrate base 14. Thereby, the first light emitting device 11 in the first display region 10 may be at substantially the same height as the second light emitting device 21 in the second display region 20 and the third light emitting device 31 in the third display region 30 with respect to the substrate base 14, so that the display effect of the display substrate may be improved.

For example, the transparent support layer 18 is disposed in the same layer as at least one of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144. For example, the transparent support layer 18 is disposed in the same layer as the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144, so that the first light emitting device 11 in the first display region 10 is at substantially the same height as the second light emitting device 21 in the second display region 20 and the third light emitting device 31 in the third display region 30, and the manufacturing process of the display substrate is simplified.

For example, in some embodiments, the display substrate further includes a pixel defining layer 146, an encapsulation layer 147, and the like, e.g., the pixel defining layer 146 is disposed on the first anode structure, and includes a plurality of openings, and the first light emitting layer is formed in the openings of the pixel defining layer 146. For example, the encapsulation layer 147 may include a single-layer or multi-layer encapsulation structure, for example, a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby enhancing the encapsulation effect on the display substrate.

For example, in the first display region 10, the second display region 20 and the third display region 30, the pixel defining layer 146 and the encapsulating layer 147 are disposed in the same layer, and are integrally connected in some embodiments, and thus the same reference numerals are used in the drawings.

For example, in various embodiments of the present disclosure, the substrate 14 may be a glass substrate, a quartz substrate, a metal substrate, a resin-based substrate, or the like. Embodiments of the present disclosure are not limited in this regard.

For example, the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144, the insulating layer 145, the pixel defining layer 146, the encapsulation layer 147, and the insulating layer 148 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or may include an organic insulating material such as polyimide, polyththalimide, polyththalamide, acrylic resin, benzocyclobutene, or phenol resin. The embodiment of the present disclosure does not specifically limit the materials of the functional layers.

For example, the material of the active layer may include a semiconductor material such as polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). For example, a portion of the active layer 121/221/321 may be rendered conductive by a conductive process such as doping, thereby having higher conductivity.

For example, the material of the gate electrode, the first capacitor plate and the second capacitor plate may include a metal material or an alloy material, such as molybdenum, aluminum, titanium, and the like.

For example, the source/drain electrode may include a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed by molybdenum, aluminum, titanium, and the like, for example, the multi-layer structure is a multi-metal layer stack, such as a titanium, aluminum, titanium three-layer metal stack (Ti/Al/Ti), and the like.

For example, the display substrate provided by the embodiment of the present disclosure may be a display substrate such as an Organic Light Emitting Diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the specific type of the display substrate is not limited by the embodiment of the present disclosure.

For example, in the case where the display substrate is an organic light emitting diode display substrate, the light emitting layer 111/211/311 may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light emitting material or a phosphorescent light emitting material, may emit red light, green light, blue light, or may emit white light, etc. In addition, according to actual needs, the light-emitting layer 111/211/311 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in different examples.

For example, where the display substrate is a quantum dot light emitting diode (QLED) display substrate, the light emitting layer 111/211/311 may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, and the like, with the particle size of the quantum dots being 2-20 nm.

For example, in the embodiment of the present disclosure, the first display region 10 may have various shapes such as a circle (the situation shown in fig. 3), a rectangle, and a triangle, and the shape of the first display region 10 of the embodiment of the present disclosure is not limited.

For example, in some embodiments, as shown in fig. 4, 6 and 7, the display substrate may further include a sensor 19, such as an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 19 may be implemented in the form of, for example, a chip, etc. For example, the sensor 19 is arranged at the second side of the display substrate, for example, the sensor 19 is arranged at the second side of the display panel by means of a double-sided tape or the like, and an orthographic projection of the sensor 19 on the substrate 14 at least partially overlaps the first display area 10, configured to receive light from the first side. Thus, the first display region 10 facilitates the arrangement of the sensor 19 while realizing the display.

At least one embodiment of the present disclosure provides a method of manufacturing a display substrate having a first side for display and a second side opposite to the first side, the method including: forming a display area comprising a first display area and a second display area at least partially surrounding the first display area, the first display area allowing at least partial transmission of light from the first side to the second side; forming at least one first connecting wire in the first display area and the second display area, wherein the first connecting wire comprises a first part and a second part, the first part and the second part are electrically connected with each other and are positioned in the first display area, and the first part comprises a first light-transmitting wiring layer; a plurality of first sub-pixels arranged in an array are formed in the first display area, each first sub-pixel comprises a first light-emitting device, each first light-emitting device comprises a first electrode structure, a second electrode structure and a first light-emitting layer between the first electrode structure and the second electrode structure, each first electrode structure comprises a first electrode sub-layer, and the first electrode sub-layers and the first light-transmitting wiring layers are formed on the same layer and electrically connected, for example integrally connected.

For example, in some embodiments, the at least one first connection trace comprises a plurality of first connection traces; the method for manufacturing a display substrate further includes: and forming a plurality of first pixel circuits in the second display area, wherein the plurality of first pixel circuits are respectively electrically connected with the first electrode structures of the plurality of first light-emitting devices through the plurality of first connecting wires so as to be used for driving the plurality of first light-emitting devices.

For example, in some embodiments, forming the second portion of the first connection trace includes: and forming a second light-transmitting wiring layer, wherein the second light-transmitting wiring layer and the first light-transmitting wiring layer are formed on the same layer and are integrally connected.

For example, in some embodiments, the method of preparing a display substrate further comprises: providing a substrate, wherein the second light-transmitting wiring layer and the first electrode sublayer are formed on the substrate, and the second part for forming the first connecting wiring further comprises: and forming a first metal wiring layer on one side of the second light-transmitting wiring layer, which is far away from the substrate, and forming a second electrode sublayer on one side of the first electrode sublayer, which is far away from the substrate, wherein the second electrode sublayer and the first metal wiring layer are formed on the same layer.

For example, in some embodiments, forming the second portion of the first connection trace further comprises: and forming an anti-oxidation protective layer on one side of the first metal wiring layer, which is far away from the substrate, and forming a third electrode sublayer on one side of the second electrode sublayer, which is far away from the substrate, wherein the third electrode sublayer and the anti-oxidation protective layer are formed on the same layer.

Next, a method for manufacturing a display substrate according to at least one embodiment of the present disclosure will be described with reference to the display substrate shown in fig. 4 as an example.

For example, as shown in fig. 15A, pixel circuits (including first, second, and third pixel circuits) in the second and

third display regions

20 and 30 are simultaneously formed on the substrate 14 using a patterning process, and the transparent support layer 18 is simultaneously formed.

Taking the formation of the first pixel circuit as an example, as shown in fig. 15A, the formation of the first pixel circuit includes forming a thin film transistor 12 and a storage capacitor 13, the thin film transistor 12 includes an active layer 121, a gate electrode 122 and source-

drain electrodes

123 and 124, and the storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132.

As shown in fig. 15A, the active layer 121 is formed on the base substrate 14, the first gate insulating layer 141 is formed on a side of the active layer 121 remote from the base substrate 14, the gate electrode 122 and the first capacitor plate 131 are formed on the same layer on the first gate insulating layer 141, a second gate insulating layer 142 is formed on the gate 122 and the side of the first capacitor plate 131 remote from the base substrate 14, a second capacitor plate 132 is formed on the side of the second gate insulating layer 142 remote from the substrate base 14, an interlayer insulating layer 143 is formed on the second capacitor plate 132 on a side thereof remote from the substrate base 14, source-

drain electrodes

123 and 124 are formed on a side of the interlayer insulating layer 143 remote from the substrate base 14, the source-

drain electrodes

123 and 124 are electrically connected to the active layer 121 through vias in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143, a planarization layer 144 is then formed on the side of source-

drain electrodes

123 and 124 remote from substrate base plate 14. For example, a via hole exposing the source and drain electrodes is formed in the planarization layer 144. For example, the transparent support layer 18 is formed in the same layer as at least one of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144. For example, the transparent support layer 18 is formed in the same layer as each of the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, and the planarization layer 144.

For example, each of the functional layers is formed by a patterning process. The primary patterning process includes, for example, processes of forming, exposing, developing, and etching a photoresist.

For example, in some embodiments, before the above structure is formed, a buffer layer (not shown in the figure) may be further formed on the substrate base plate 14, and the buffer layer may serve as a transition layer to prevent harmful substances in the substrate base plate 14 from invading into the interior of the display base plate, and may also increase the adhesion of the film layer in the display base plate on the substrate base plate 14. For example, the material of the buffer layer may include a single layer or a multilayer structure formed of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

For example, after the above structure is formed, the first connection wire 15 and the first electrode structure 111 are formed in the first display region 10 and the second display region 20. For example, as shown in fig. 12A, a first electrode material layer 151, a second electrode material layer 161, and a third electrode material layer 171 are sequentially deposited on the first display region 10 and the second display region 20 through a mask 40. For example, the mask 40 has a hollow portion (i.e., a white portion in the figure) so that the material forms a certain pattern through the hollow portion. Thus, the first electrode material layer 151, the second electrode material layer 161, and the third electrode material layer 171 deposited through the mask 40 have substantially the same pattern.

Then, as shown in fig. 15B, the third electrode material layer 171 and a portion of the second electrode material layer 161 located in the second display region 20 and a portion of the first display region 10 (i.e., a portion of the first portion 15A of the first connection trace 15 to be formed) are etched away using a first wet etching process (i.e., the first wet etching process completely etches the third electrode material layer 171 in the second display region 20 and a portion of the first display region 10, but the thickness of the etched second electrode material layer 161 is smaller than the forming thickness of the second electrode material layer 161); then, the second wet etching process is used to etch away the remaining second electrode material layer located in the second display region 20 and the portion of the first display region 10, so as to completely remove the second electrode material layer 161 located in the second display region 20 and the portion of the first display region 10 through two wet etching processes, thereby forming the first portion 15A of the first connection trace 15 in the portion of the first display region 10, and at this time, the second electrode material layer 161 and the third electrode material layer 171 that are not etched in the first display region 10 form the second electrode sublayer 111B and the third electrode sublayer 111C of the first electrode structure 111, respectively. The etching thickness of the material layer can be accurately controlled by a wet etching method twice so as to avoid over-etching; moreover, when the second electrode material layer 161 is made of Ag, the phenomenon of Ag precipitation during the etching process can be effectively suppressed by the wet etching twice, so as to ensure the etching accuracy.

For example, in other embodiments, the display substrates shown in fig. 6 and 7 may be formed using substantially the same method. For example, in forming the display substrate shown in fig. 6, after the first electrode material layer 151, the second electrode material layer 161, and the third electrode material layer 171 are sequentially deposited in the first display region 10 and the second display region 20 through the mask 40, as shown in fig. 16, the third electrode material layer 171 and a portion of the second electrode material layer 161 in a portion of the first display region 10 (i.e., a portion of the first portion 15A of the first connection trace 15 to be formed) may be etched away using a first wet etching process; then, the second wet etching process is used to etch away the remaining second electrode material layer 161 in the portion of the first display region 10, so as to completely remove the second electrode material layer 161 in the portion of the first display region 10 through two wet etching processes, thereby forming a first portion 15A of the first connection trace 15 in the portion of the first display region 10, at this time, the second electrode material layer 161 and the third electrode material layer 171, which are not etched in the first display region 10, form a second electrode sublayer 111B and a third electrode sublayer 111C of the first electrode structure, respectively, and the second electrode material layer 161 and the third electrode material layer 171, which are not etched in the second display region 20, form a metal routing 16 and an oxidation-preventing protection layer 17 of the second portion 15B of the first connection trace 15, respectively.

For example, in forming the display substrate shown in fig. 8, a patterning process may be used to first form the metal routing layer of the second portion 15B, then form the insulating layer 145 on the metal routing layer, and form a via in the insulating layer 145. Thereafter, a first light-transmitting wiring layer of the first portion 15A and a first electrode sub-layer of the first anode structure are formed on the insulating layer 145 at the same layer by a patterning process, and at this time, the first light-transmitting wiring layer is electrically connected to the second portion 15B through a via hole formed in the insulating layer 148, thereby forming a first connection wiring 15 including the first portion 15A and the second portion 15B.

For example, after the first connecting trace 15 is formed, the method for manufacturing the display substrate further includes forming structures such as a pixel defining layer, a light emitting device, and a packaging layer on the first connecting trace 15, and specific forming manners of these structures may refer to related technologies, which are not described herein again.

For example, referring to fig. 4, 6 and 7, after the above-described structure of the display substrate is formed, the method for manufacturing the display substrate may further include: a sensor is provided and bonded to the second side of the display substrate. At this time, the orthographic projection of the sensor on the substrate base plate at least partially overlaps the first display region, whereby light from the first side can be received through the first display region.

For example, fig. 17 shows a plan view of another first display area 10 and second display area 20. As shown in fig. 17, in some embodiments, the first connection trace 15 may cross over the second sub-pixel P in the second display region 20 to electrically connect the first light emitting device 11 (e.g., including an anode, a light emitting layer, a cathode) located in the first display region 10 and the first pixel circuit D (e.g., including a driving transistor, a storage capacitor, etc.) located in the second display region 20 for driving the first light emitting device 11. For example, in the embodiment shown in fig. 17, the first connection wire 15 may electrically connect the first light emitting device 11 located in the first display region 10 and the first pixel circuit D located in the second display region 20 for driving the first light emitting device 11 in a straight line shape. For example, the data lines D (e.g., D1, D2) for driving the first sub-pixels in the first display region 10 may be routed at the boundary of the second display region 20 near the first display region 10.

For example, the pixel circuits of the sub-pixels positioned in the same column may be electrically connected to the same data line, and thus the light emitting devices of the sub-pixels positioned in the same column may be driven by the same data line. For example, in the embodiment shown in fig. 17, the left data line D1 is electrically connected to the pixel circuits of the first column of left sub-pixels in the first display region 10 through a routing line, and the right data line D2 is electrically connected to the pixel circuits of the second column of left sub-pixels in the first display region 10. Of course, the other columns of sub-pixels in the first display area 10 are also connected to a data line, which is not shown in the figure.

It should be noted that, in the embodiments of the present disclosure, a column direction refers to a vertical direction in the drawings, and a row direction refers to a horizontal direction in the drawings, and in other embodiments, the column direction and the row direction may be interchanged, which is not limited in the embodiments of the present disclosure.

For example, a wiring dense area exists between the first display area 10 and the second display area 20, as shown by the dashed box in the figure, and in this case, for the convenience of wiring and space saving, in some embodiments, the wiring dense area may adopt a jumper design, that is, the wirings are arranged in different wiring layers.

In the display substrate provided by the embodiment of the present disclosure (or the display substrate prepared by the preparation method provided by the embodiment of the present disclosure), the first display region has high light transmittance, so that the display can be realized, and convenience is provided for the arrangement of the sensor. In addition, the first connecting wires in the first display area and the first electrode structures of the first light-emitting devices can be formed in the same layer, so that the preparation process of the display substrate can be simplified.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) For purposes of clarity, the thickness of layers or regions in the figures used to describe embodiments of the present disclosure are exaggerated or reduced, i.e., the figures are not drawn on a true scale. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

A display substrate having a first side for displaying and a second side opposite the first side, the display substrate comprising:

a display area, wherein the display area comprises a first display area and a second display area at least partially surrounding the first display area, the first display area allowing at least partial transmission of light from the first side to the second side;

at least one first connection wire in the first display region and the second display region, wherein the first connection wire comprises a first portion located in the first display region and a second portion located in the second display region, which are electrically connected to each other, and the first portion comprises a first light-transmitting wire layer;

the first display area comprises a plurality of first sub-pixels arranged in an array, each first sub-pixel comprises a first light-emitting device, each first light-emitting device comprises a first electrode structure, a second electrode structure and a first light-emitting layer arranged between the first electrode structure and the second electrode structure, each first electrode structure comprises a first electrode sublayer, and the first electrode sublayers and the first light-transmitting wiring layers are arranged on the same layer and electrically connected.
The display substrate according to claim 1, wherein the at least one first connection trace comprises a plurality of first connection traces;

the second display area comprises a plurality of first pixel circuits which are electrically connected with the first electrode structures of the first light-emitting devices through the first connecting wires respectively so as to be used for driving the first light-emitting devices.
A display substrate according to claim 1 or 2, wherein the second portion comprises a second light-transmissive routing layer, the second light-transmissive routing layer being disposed on a same layer as the first light-transmissive routing layer and being integrally connected thereto.
A display substrate according to claim 3, wherein the display substrate comprises a substrate base plate, the second light-transmitting routing layer and the first electrode sub-layer being located on the substrate base plate,

the second part also comprises a first metal wiring layer positioned at one side of the second light-transmitting wiring layer far away from the substrate, the first electrode structure also comprises a second electrode sublayer positioned at one side of the first electrode sublayer far away from the substrate,

the second electrode sublayer and the first metal wiring layer are arranged on the same layer.
The display substrate of claim 4, wherein the second portion further comprises an oxidation protection layer on a side of the first metal routing layer away from the substrate base, the first electrode structure further comprises a third electrode sublayer on a side of the second electrode sublayer away from the substrate base,

the third electrode sublayer and the anti-oxidation protection layer are arranged on the same layer.
The display substrate of claim 5, wherein the first electrode structure is a first anode structure and the second electrode structure is a first cathode structure;

the material of the first electrode sub-layer comprises indium tin oxide, the material of the second electrode sub-layer comprises silver or a silver alloy, and the material of the third electrode sub-layer comprises indium tin oxide.
A display substrate according to claim 1 or 2, wherein the second portion comprises a second metal routing layer arranged differently from the first light-transmissive routing layer and electrically connected by a via.
The display substrate of claim 2, wherein the second display region further comprises a plurality of second sub-pixels, each second sub-pixel comprising a second light emitting device and a second pixel circuit electrically connected to the second light emitting device, the second pixel circuit configured to drive the second light emitting device,

in the second display region, the plurality of second pixel circuits are arranged in a first array.
The display substrate according to claim 8, wherein the plurality of first pixel circuits are dispersedly disposed in the first array and arranged in a second array with the plurality of second pixel circuits in the second display region.
The display substrate of claim 8 or 9, wherein the second light emitting device comprises a second anode structure, a second cathode structure, and a second light emitting layer between the second anode structure and the second cathode structure,

the second anode structure is electrically connected to the second pixel circuit through a via.
The display substrate of any of claims 1-10, wherein the display region further comprises a third display region at least partially surrounding the second display region, the third display region comprising a plurality of third sub-pixels arranged in an array, each third sub-pixel comprising a third light emitting device and a third pixel circuit electrically connected to the third light emitting device, the third pixel circuit configured to drive the third light emitting device,

the third light emitting device includes a third anode structure, a third cathode structure, and a third light emitting layer between the third anode structure and the third cathode structure, and the third anode structure is electrically connected to the third pixel circuit through a via hole.
The display substrate of any of claims 2-6, wherein the display substrate comprises a base substrate,

the first display area further comprises a transparent support layer positioned on the substrate base plate, and the first light-emitting device is positioned on one side of the transparent support layer far away from the substrate base plate.
The display substrate according to claim 12, wherein the first pixel circuit comprises a thin film transistor and a storage capacitor,

the thin film transistor comprises an active layer, a grid electrode and a source drain electrode; the storage capacitor comprises a first capacitor plate and a second capacitor plate,

the active layer is arranged on the substrate base plate, a first gate insulating layer is arranged on one side of the active layer far away from the substrate base plate,

the grid electrode and the first capacitor plate are arranged on the same layer on one side of the first grid insulating layer far away from the substrate, a second grid insulating layer is arranged on one side of the grid electrode and the first capacitor plate far away from the substrate,

the second capacitor plate is arranged on one side of the second gate insulating layer far away from the substrate base plate, an interlayer insulating layer is arranged on one side of the second capacitor plate far away from the substrate base plate,

the source and drain electrodes are arranged on one side of the interlayer insulating layer far away from the substrate base plate and are electrically connected with the active layer through the first gate insulating layer, the second gate insulating layer and the through holes in the interlayer insulating layer, and a planarization layer is arranged on one side of the source and drain electrodes far away from the substrate base plate;

the transparent support layer is disposed on the same layer as at least one of the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the planarization layer.
The display substrate of claim 12, further comprising a sensor, wherein the sensor is disposed on a second side of the display substrate and an orthographic projection of the sensor on the substrate at least partially overlaps the first display area, configured to receive light from the first side.
A method of manufacturing a display substrate having a first side for display and a second side opposite the first side, the method comprising:

forming a display area comprising a first display area and a second display area at least partially surrounding the first display area, the first display area allowing at least partial transmission of light from the first side to the second side;

forming at least one first connecting wire in the first display area and the second display area, wherein the first connecting wire comprises a first part and a second part, the first part and the second part are electrically connected, the first part is positioned in the first display area, the second part is positioned in the second display area, and the first part comprises a first light-transmitting wire layer;

and forming a plurality of first sub-pixels arranged in an array manner in the first display area, wherein each first sub-pixel comprises a first light-emitting device, the first light-emitting device comprises a first electrode structure, a second electrode structure and a first light-emitting layer between the first electrode structure and the second electrode structure, the first electrode structure comprises a first electrode sub-layer, and the first electrode sub-layer and the first light-transmitting wiring layer are formed on the same layer and are electrically connected.
The method for manufacturing a display substrate according to claim 15, wherein the at least one first connection trace comprises a plurality of first connection traces;

the preparation method further comprises the following steps: and forming a plurality of first pixel circuits in the second display area, wherein the plurality of first pixel circuits are electrically connected with the first electrode structures of the plurality of first light-emitting devices through the plurality of first connecting wires respectively so as to drive the plurality of first light-emitting devices.
The method for manufacturing a display substrate according to claim 15 or 16, wherein forming the second portion of the first connection trace includes:

and forming a second light-transmitting wiring layer, wherein the second light-transmitting wiring layer and the first light-transmitting wiring layer are formed on the same layer and are integrally connected.
The method for manufacturing a display substrate according to claim 17, further comprising: providing a substrate, wherein the second light-transmitting trace layer and the first electrode sub-layer are formed on the substrate, and the forming of the second portion of the first connection trace further comprises:

forming a first metal wiring layer on one side of the second light-transmitting wiring layer far away from the substrate, forming a second electrode sub-layer on one side of the first electrode sub-layer far away from the substrate,

the second electrode sublayer and the first metal wiring layer are formed on the same layer.
The method for manufacturing a display substrate according to claim 18, wherein forming the second portion of the first connection trace further comprises:

an anti-oxidation protective layer is formed on one side of the first metal wiring layer, which is far away from the substrate base plate, a third electrode sub-layer is formed on one side of the second electrode sub-layer, which is far away from the substrate base plate,

the third electrode sublayer and the anti-oxidation protection layer are formed on the same layer.
The method for preparing a display substrate according to any one of claims 16 to 19, wherein forming the first connection trace and the first electrode structure comprises:

sequentially depositing a first electrode material layer, a second electrode material layer and a third electrode material layer in the first display area and the second display area through a mask plate;

etching away at least part of the third electrode material layer and part of the second electrode material layer in the first display region by using a first wet etching process;

and etching away at least the remaining second electrode material layer located in the portion of the first display region using a second wet etching process.
The method of manufacturing a display substrate according to any one of claims 16 to 20, wherein forming the first pixel circuit includes forming a thin film transistor and a storage capacitor,

the thin film transistor comprises an active layer, a grid electrode and a source drain electrode; the storage capacitor comprises a first capacitor plate and a second capacitor plate,

wherein the active layer is formed on a substrate base plate, a first gate insulating layer is formed on one side of the active layer far away from the substrate base plate,

the grid electrode and the first capacitor plate are formed on the same layer on one side of the first grid insulating layer far away from the substrate base plate, a second grid insulating layer is formed on one side of the grid electrode and the first capacitor plate far away from the substrate base plate,

the second capacitor plate is formed on one side of the second gate insulating layer far away from the substrate base plate, an interlayer insulating layer is formed on one side of the second capacitor plate far away from the substrate base plate,

the source and drain electrodes are formed on one side of the interlayer insulating layer far away from the substrate base plate and are electrically connected with the active layer through the first gate insulating layer, the second gate insulating layer and the through holes in the interlayer insulating layer, and a planarization layer is formed on one side of the source and drain electrodes far away from the substrate base plate;

forming the first display region further comprises: forming a transparent support layer between the substrate base and the first light emitting device,

wherein the transparent support layer is formed in the same layer as at least one of the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the planarization layer.
The method for manufacturing a display substrate according to claim 18 or 19, further comprising: providing a sensor and bonding the sensor to a second side of the display substrate,

wherein an orthographic projection of the sensor on the substrate base plate at least partially overlaps the first display area, configured to receive the light from the first side.