CN113438024B

CN113438024B - Visible light communication system based on FPGA and CMOS camera

Info

Publication number: CN113438024B
Application number: CN202110763182.8A
Authority: CN
Inventors: 董润泽
Original assignee: Individual
Current assignee: Individual
Priority date: 2021-07-06
Filing date: 2021-07-06
Publication date: 2023-03-31
Anticipated expiration: 2041-07-06
Also published as: CN113438024A

Abstract

The invention discloses a visible light communication system based on an FPGA (field programmable gate array) and a CMOS (complementary metal oxide semiconductor) camera, which belongs to the field of wireless communication and comprises a program burning module, a signal transmitting module, a signal receiving module, a phase-locked loop module, a data caching module, a data optimizing module and a data extracting module, wherein the signal transmitting module is respectively in communication connection with the program burning module and the signal receiving module, the signal receiving module is respectively in communication connection with the phase-locked loop module and the data caching module, the data caching module is in communication connection with the data optimizing module, and the data extracting module is in communication connection with the data optimizing module; the invention can avoid the generation of acquisition errors, increase the communication reliability, simultaneously adjust the frequency of the output signal in real time, improve the stability of data transmission, reduce the error rate, record the error rate and the communication effect in real time, facilitate the recording of workers, optimize the communication system and improve the working efficiency of the workers.

Description

Visible light communication system based on FPGA and CMOS camera

Technical Field

The invention relates to the field of wireless communication, in particular to a visible light communication system based on an FPGA (field programmable gate array) and a CMOS (complementary metal oxide semiconductor) camera.

Background

The existing radio signal transmission equipment has many limitations, such as rare, expensive and inefficient, for example, mobile phones, millions of base stations around the world help them to enhance signals, but most of energy is consumed in cooling, the efficiency is only 5%, compared with the used wireless local area network (wireless LAN), the "visible light communication" system can use indoor lighting equipment to transmit signals instead of the wireless LAN base station, the communication speed can reach tens of mega to hundreds of mega per second, and the future transmission speed may exceed optical fiber communication. By using a special computer and a mobile information terminal which can send and receive signals, data can be downloaded and uploaded for a long time only in a place illuminated by indoor light. The visible light system also has the characteristic of high safety. The shielding object is used for shielding and shielding light, information cannot leak out of a transmission area, information can be transmitted only by additionally arranging the control chip on the LED lamp which is visible everywhere, and the method is very simple, convenient and efficient, and therefore, visible light communication has very wide and good development prospect, and therefore, the invention of the visible light communication system based on the FPGA and the CMOS camera becomes particularly important;

through retrieval, the chinese patent No. CN103684597A discloses a visible light video communication system and method based on FPGA, which realizes short-distance, high-speed visible light video communication, but when collecting LED light signals, collection errors are easily generated, resulting in a large output error rate; in addition, the existing visible light communication system based on the FPGA and the CMOS camera cannot record the error rate in the communication process, so that a worker cannot analyze data of the visible light communication system, and the working efficiency of the worker is reduced.

Disclosure of Invention

The invention aims to solve the defects in the prior art, and provides a visible light communication system based on an FPGA and a CMOS camera.

In order to achieve the purpose, the invention adopts the following technical scheme:

the visible light communication system based on the FPGA and the CMOS camera comprises a program burning module, a signal transmitting module, a signal receiving module, a phase-locked loop module, a data caching module, a data optimizing module and a data extracting module;

the signal transmitting module is respectively in communication connection with the program burning module and the signal receiving module, the signal receiving module is respectively in communication connection with the phase-locked loop module and the data cache module, the data cache module is in communication connection with the data optimization module, and the data extracting module is in communication connection with the data optimization module;

the signal transmitting module comprises a program analyzing unit and an LED lamp array;

the signal receiving module comprises a signal conversion unit and a CMOS camera, wherein the specific model of the CMOS camera is ov5640;

the phase-locked loop module comprises a voltage-controlled oscillator, a phase comparator and a reference frequency oscillator.

Further, the program burning module is used for connecting the first FPGA development board with a computer LINK and receiving a program written by a worker through the Quartus software.

Further, the program analysis unit is configured to receive a program that is completed in burning and perform data analysis on the program, where the data analysis specifically includes the following steps:

the method comprises the following steps: the program analysis unit analyzes the burned program, classifies the program-controlled electric signals according to the high-level signal and the low-level signal, and marks the program-controlled electric signals as T and F respectively;

step two: extracting timing data in a program, and marking the conversion time of high and low level signals as C;

step three: extracting corresponding array position data displayed by the high-level signals and the low-level signals, and respectively marking the data as (Xi, yi) and (Zn, ln), wherein i and n are natural numbers;

the LED lamp array is used for receiving T, F, C, (Xi, yi) and (Zn, ln) and starting to transmit signals, and the specific steps of the signal transmission are as follows:

step (1): the LED lamp array receives T and F and starts to search (Xi, yi) and (Zn, ln) corresponding to T and F;

step (2): adjusting the brightness of the LED lamps corresponding to (Xi, yi) and (Zn, ln) in the LED lamp array according to the corresponding high-low level signals;

and (3): and when the LED lamp display time reaches C, the LED lamp array starts to receive T and F again and display.

Furthermore, the CMOS camera collects the optical signals sent by the LED lamp array in real time and sends the collected optical signals to the signal conversion unit;

the signal conversion unit is used for the second FPGA development board to carry out various processing on the optical signals collected by the CMOS camera to generate original sending electric signals and output the original sending electric signals.

Further, the phase-locked loop module is used for detecting the phase difference of the output signal of the signal receiving module in real time and adjusting the frequency of the phase difference, and the frequency adjustment specifically comprises the following steps:

s1: when the signal receiving module starts to output a sending electric signal, the phase-locked loop module starts to compare the phase of the sending electric signal with the phase of a signal of the voltage-controlled oscillator, and if a phase difference exists between the two groups of signals, a phase error signal is generated and output;

s2: the phase-locked loop module receives the error signal, detects the frequencies of the reference frequency oscillator and the voltage-controlled oscillator at the same time, and marks the frequencies as B1 and B2;

s3: if B1 is larger than B2, the phase-locked loop module starts to control the phase comparator to generate a positive pulse wave signal, and the frequency of an oscillator of the voltage-controlled oscillator is increased;

s4: if B1 is less than B2, the phase-locked loop module starts to control the phase comparator to generate a negative pulse wave signal, and the frequency of the oscillator of the voltage-controlled oscillator is reduced.

Furthermore, the data cache module is used for receiving the sending electric signal output by the signal conversion unit and caching the sending electric signal;

the data optimization module is used for extracting and optimizing the transmitting electric signals stored in the data cache module, and the information optimization specifically comprises the following steps:

and (4) SS1: the data optimization module extracts the sending electric signal, performs time sequence matching on the sending electric signal and converts the time sequence of the sending electric signal into a VGA time sequence;

and (4) SS2: and after the time sequence conversion is finished, carrying out gray processing on the time sequence conversion, and generating result data after carrying out correction processing on the gray value through effective row selection and threshold judgment.

Further, the data extraction module is used for receiving the result data and comparing the result data, and the data comparison specifically comprises the following steps:

p1: the data extraction module is in communication connection with an external oscilloscope and sends result data to the oscilloscope for waveform display;

p2: comparing the input waveform with the output waveform, judging the communication effect, simultaneously extracting data displayed by the oscilloscope, and analyzing the error rate of the data;

p3: and the computer receives the communication effect and the error rate, generates a recording table for recording, and feeds back the recorded recording table to the staff.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention is provided with a signal receiving module, a first FPGA development board is connected with a LINK of a computer through a program analyzing unit and receives a program written by staff through Quartus software, the program analyzing unit is used for receiving and analyzing the program which is burnt, an LED lamp array starts to send optical signals according to the analyzed data, a CMOS camera collects the optical signals sent by the LED lamp array in real time and sends the collected optical signals to a signal conversion unit for signal conversion processing and output, a phase-locked loop module carries out frequency adjustment on output signals, and the optical signals sent by the LED lamp array are collected through the CMOS camera, so that the collection error can be avoided, the communication reliability is increased, meanwhile, the frequency of the output signals is adjusted in real time, the stability of data transmission is improved, and the error rate is reduced;

2. the invention is provided with a data extraction module, wherein the data cache module starts to receive a sending electric signal output by a signal conversion unit and caches the sending electric signal, the data optimization module starts to extract data cached in the data cache module and matches the time sequence of the data, the time sequence of the data is converted into a VGA time sequence, the time sequence conversion is completed, the data is subjected to gray scale processing, the gray scale value is corrected through effective row selection and threshold judgment to generate result data, the data extraction module sends the result data to an oscilloscope for waveform display, the input waveform and the output waveform are compared, the communication effect of the data is judged, meanwhile, the data displayed by the oscilloscope are extracted, the error rate of the data is analyzed, a computer receives the communication effect and the error rate, records the record table and feeds the record table to a worker, the error rate and the communication effect can be recorded in real time, the worker can conveniently record and optimize the communication system, and the working efficiency of the worker is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.

Fig. 1 is a system block diagram of a visible light communication system based on an FPGA and a CMOS camera according to the present invention;

fig. 2 is a schematic structural diagram of a signal transmitting module in a visible light communication system based on an FPGA and a CMOS camera according to the present invention;

fig. 3 is a schematic structural diagram of a signal receiving module in a visible light communication system based on an FPGA and a CMOS camera according to the present invention;

fig. 4 is a schematic structural diagram of a phase-locked loop module in a visible light communication system based on an FPGA and a CMOS camera according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

Example 1

Referring to fig. 1-4, the visible light communication system based on the FPGA and the CMOS camera includes a program burning module, a signal transmitting module, a signal receiving module, and a phase-locked loop module;

the signal transmitting module is respectively in communication connection with the program burning module and the signal receiving module, the signal receiving module is respectively in communication connection with the phase-locked loop module and the data caching module, the data caching module is in communication connection with the data optimizing module, and the data extracting module is in communication connection with the data optimizing module;

the signal receiving module comprises a signal conversion unit and a CMOS camera;

the phase-locked loop module includes a voltage-controlled oscillator, a phase comparator, and a reference frequency oscillator.

The program burning module is used for connecting the first FPGA development board with a computer LINK and receiving a program written by a worker through Quartus software, the program analyzing unit starts to receive the program which is burnt and analyzes the program, the LED lamp array receives the data which is analyzed and completed by the program analyzing unit and starts to send signals, the CMOS camera collects optical signals sent by the LED lamp array in real time and sends the collected optical signals to the signal conversion unit, the signal conversion unit is used for the second FPGA development board to carry out various processing on the optical signals collected by the CMOS camera to generate original sending electric signals and output the original sending electric signals, and the phase-locked loop module is used for detecting the phase difference of the output signals of the signal receiving module in real time and carrying out frequency adjustment on the original sending electric signals.

Specifically, firstly, the program analyzing unit analyzes the programmed program, classifies the electric signals controlled by the program according to a high-level signal and a low-level signal, and respectively marks the electric signals as T and F, meanwhile, the program analyzing unit extracts timing data in the program, and marks the conversion time of the high-level signal and the low-level signal as C, extracts corresponding array position data displayed by the high-level signal and the low-level signal, and respectively marks the data as (Xi, yi) and (Zn, ln), wherein i and n are natural numbers, secondly, the LED lamp array starts to receive T and F, starts to search corresponding (Xi, yi) and (Zn, ln), and carries out brightness adjustment on the LED lamps corresponding to (Xi, yi) and (Zn, ln) in the LED lamp array according to the corresponding high-level signal and low-level signal, when the display time of the corresponding LED lamp reaches C, the LED lamp array starts to receive T and F again and display, meanwhile, the CMOS camera starts to collect optical signals sent by the LED lamp array in real time, the collected optical signals are sent to the signal conversion unit, the second FPGA development board carries out multiple processing on the optical signals collected by the CMOS camera through the signal conversion unit to generate original sending electric signals and outputs the original sending electric signals, the phase-locked loop module starts to compare the phase of the signals with the phase of the signals of the voltage-controlled oscillator while outputting the signals, phase error signal output can be generated if the phase difference exists between the two groups of signals, the phase-locked loop module receives the error signals, detects the frequencies of the reference frequency oscillator and the voltage-controlled oscillator simultaneously, and marks the frequencies of the reference frequency oscillator and the voltage-controlled oscillator as B1 and B2; if B1 is greater than B2, the phase-locked loop module starts to control the phase comparator to generate a positive pulse wave signal, the oscillator frequency of the voltage-controlled oscillator is increased, if B1 is less than B2, the phase-locked loop module starts to control the phase comparator to generate a negative pulse wave signal, the oscillator frequency of the voltage-controlled oscillator is reduced, the light signals sent by the LED lamp array are collected through the CMOS camera, the collection error can be avoided, the communication reliability is improved, meanwhile, the output signal frequency is adjusted in real time, the stability of data transmission is improved, and the error rate is reduced.

The specific model of the CMOS camera in this embodiment is ov5640.

Example 2

Except that the structure is the same as that of the embodiment 1, the embodiment mainly explains the data processing optimization process, which comprises a data caching module, a data optimization module and a data extraction module;

the data caching module receives the sending electric signals output by the signal conversion unit and caches the sending electric signals, the data optimizing module is used for extracting and optimizing the sending electric signals stored in the data caching module, and the data extracting module is used for receiving result data and comparing the result data with the result data.

Specifically, firstly, the data optimization module extracts and matches a transmission electric signal, converts the time sequence of the transmission electric signal into a VGA time sequence, completes time sequence conversion, performs gray level processing on the time sequence, generates result data after performing correction processing on the gray level value through effective row selection and threshold judgment, is in communication connection with an external oscilloscope, transmits the result data to the oscilloscope for waveform display, compares an input waveform with an output waveform by a computer, judges the communication effect of the input waveform, extracts the data displayed by the oscilloscope, analyzes the error rate of the data, receives the communication effect and the error rate by the computer, generates a record table for recording, and feeds the record table which is recorded back to a worker.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims

1. The visible light communication system based on the FPGA and the CMOS camera is characterized by comprising a program burning module, a signal transmitting module, a signal receiving module, a phase-locked loop module, a data caching module, a data optimizing module and a data extracting module;

the phase-locked loop module comprises a voltage-controlled oscillator, a phase comparator and a reference frequency oscillator;

the phase-locked loop module is used for detecting the phase difference of the output signals of the signal receiving module in real time and adjusting the frequency of the phase-locked loop module, and the frequency adjustment comprises the following specific steps:

2. The visible light communication system based on the FPGA and the CMOS camera as claimed in claim 1, wherein the program burning module is used for connecting the FPGA development board I with a LINK of a computer and receiving a program written by staff through a Quartus software.

3. The visible light communication system based on the FPGA and the CMOS camera according to claim 1, wherein the program analyzing unit is configured to receive a program that is completed by burning and perform data analysis on the program, and the data analysis specifically includes the following steps:

4. The visible light communication system based on the FPGA and the CMOS camera as claimed in claim 3, wherein the CMOS camera collects the light signals sent by the LED lamp array in real time and sends the collected light signals to the signal conversion unit;

5. The visible light communication system based on the FPGA and the CMOS camera as claimed in claim 4, wherein the data buffer module is configured to receive the transmission electrical signal output by the signal conversion unit and perform data buffer on the transmission electrical signal;

6. The visible light communication system based on the FPGA and the CMOS camera according to claim 5, wherein the data extraction module is configured to receive result data and compare the result data, and the data comparison specifically comprises the following steps:

p2: comparing the input waveform with the output waveform, judging the communication effect of the waveforms, extracting data displayed by the oscilloscope and analyzing the error rate of the data;