CN113436669A

CN113436669A - LPDDR bank address mapping method

Info

Publication number: CN113436669A
Application number: CN202110705286.3A
Authority: CN
Inventors: 谢登煌; 宋文杰; 刘孜
Original assignee: Shenzhen Jingcun Technology Co ltd
Current assignee: Shenzhen Jingcun Technology Co ltd
Priority date: 2021-06-24
Filing date: 2021-06-24
Publication date: 2021-09-24

Abstract

The invention discloses a method for mapping a bank address of an LPDDR (low data density digital radiography), which comprises the following steps of: respectively writing test data into and reading each bank of the LPDDR chip by a DRAM controller of the SOC chip by adopting a test algorithm; respectively comparing whether the test data written in each bank is consistent with the read data, and if so, judging that the corresponding bank is qualified; and if the qualified bank number is not less than half of the total bank number of the LPDDR chip, remapping the addresses of all the banks of the LPDDR chip according to a preset mapping relation, and mapping the addresses of the qualified banks to a plurality of previous continuous bank address spaces. According to the LPDDR bank address mapping method, the addresses of the banks of the LPDDR chip can be mapped again, only normal banks are used, and bad banks are shielded, so that the utilization rate of the LPDDR chip is improved.

Description

LPDDR bank address mapping method

Technical Field

The invention relates to the technical field of memory chips, in particular to a bank address mapping method of LPDDR.

Background

Along with the development of integrated circuits, the density and speed of the integrated circuits are higher and higher, and meanwhile, the failure rate of the integrated circuits is also improved. For LPDDR (Low Power Double Data Rate SDRAM, Low Power Double Data Rate memory), an architecture of 8 banks is generally adopted, and as long as one bank has a problem, the whole chip is determined to be unqualified and cannot be used normally. In order to improve the utilization rate of LPDDR, only bank which functions normally may be used. However, because LPDDR has no independent bank address line, which is multiplexed with a control line, a bad bank address needs to be found, and the bad bank address space is masked, so that only the normal bank address space is accessed.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a method for mapping the bank address of the LPDDR, which can remap the address of the bank of the LPDDR chip and only use the normal bank to shield the bad bank.

The method for mapping the bank address of the LPDDR comprises the following steps: respectively writing test data into and reading each bank of the LPDDR chip by a DRAM controller of the SOC chip by adopting a test algorithm; respectively comparing whether the test data written in each bank is consistent with the read data, and if so, judging that the corresponding bank is qualified; and if the qualified bank number is not less than half of the total bank number of the LPDDR chip, remapping all the addresses of the banks of the LPDDR chip according to a preset mapping relation, and mapping the qualified addresses of the banks to a plurality of previous continuous bank address spaces.

The method for mapping the bank address of the LPDDR in the embodiment of the invention at least has the following beneficial effects: all the banks of the LPDDR chip are tested according to a test algorithm, if the number of the qualified banks is not less than half of the total number of the banks of the LPDDR chip, the addresses of all the banks of the LPDDR chip are remapped, the addresses of the qualified banks are mapped to a plurality of previous continuous bank address spaces, so that the DRAM controller can only access the previous address spaces of the qualified banks, bad bank address spaces are shielded, and the utilization rate of the LPDDR chip is further improved.

According to some embodiments of the invention, the total number of banks of the LPDDR chip is 8.

According to some embodiments of the present invention, the remapping all the bank addresses of the LPDDR chip according to a preset mapping relationship, and mapping the addresses of the qualified banks to the consecutive bank address spaces in the front, specifically: generating a mapping relation table by a bubble sorting method, remapping all the addresses of the banks of the LPDDR chip by the mapping relation table, and mapping the qualified addresses of a plurality of the banks to a plurality of previous continuous bank address spaces.

According to some embodiments of the invention, further comprising: and writing the mapping relation into a configuration register of the DRAM controller, and accessing by the DRAM controller according to the mapped bank address.

According to some embodiments of the invention, the test algorithm employs March C or checkerbard.

According to some embodiments of the invention, the LPDDR chip is determined to be defective if the number of qualified banks is less than half of the total number of banks of the LPDDR chip.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a flowchart illustrating a method for mapping a bank address of an LPDDR in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram of an 8-bank architecture of an LPDDR chip according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a bank address mapping relationship according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.

In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.

SOC: system on Chip, System on Chip.

DRAM: dynamic Random Access Memory.

Referring to fig. 1 to 3, a method for mapping a bank address of an LPDDR according to an embodiment of the present invention includes the following steps:

s100: test data are written and read in each bank of the LPDDR chip respectively through a DRAM controller of the SOC chip by adopting a test algorithm.

Specifically, test data (such as 0x 555555555555 or other custom data) is respectively written into each bank of the LPDDR chip by a DRAM controller of the SOC chip and by using a corresponding test algorithm, such as March C, Checkerboard (Checkerboard algorithm) and butterfly algorithm, and then read from each bank by the DRAM controller of the SOC chip.

S200: and respectively comparing whether the test data written in each bank is consistent with the read data, and if so, judging that the corresponding bank is qualified.

Comparing whether the data read out from each bank is consistent with the written test data by the CPU of the SOC chip, and if so, indicating that the bank is qualified; if the bank is inconsistent with the bank, indicating that the bank is damaged; and simultaneously, recording the physical addresses of all the banks.

S300: and if the qualified bank number is not less than half of the total bank number of the LPDDR chip, remapping the addresses of all the banks of the LPDDR chip according to a preset mapping relation, and mapping the addresses of the qualified banks to a plurality of previous continuous bank address spaces.

The method for mapping the bank address of the LPDDR according to an embodiment of the present invention is described in detail with reference to fig. 1 to 3, and it should be understood that the following description is only exemplary and not intended to limit the present invention.

As shown in FIG. 2, assume that the LPDDR chip has a total of 8 banks, namely bank0-bank7, and 8 banks are a way of independent memory arrays on die; respectively writing test data into the 8 banks by a DRAM controller of the SOC chip by adopting a March C algorithm; determining whether the data read from each bank is consistent with the written data through a DRAM controller and a CPU of the SOC chip, and if so, indicating that the bank is qualified; if not, indicating that the bank is damaged; as shown in FIG. 3, PASS represents PASS, FALL represents fail; meanwhile, the physical addresses of the 8 banks are recorded. And if the number of the qualified banks is less than 4, judging that the whole LPDDR chip is a defective product. As shown in fig. 3, if the number of the qualified banks is greater than or equal to 4, a mapping relation table is generated by using a bubble sorting method, addresses of 8 banks of the LPDDR chip are remapped through the mapping relation table, and the addresses of the qualified banks are mapped to a plurality of consecutive bank address spaces in the front. Assuming that a total of 4 banks are qualified, namely bank2, bank3, bank4 and bank7, the 4 banks are located in the front 4 bank address spaces and the 4 unqualified banks are located in the rear 4 bank address spaces by the bubble sorting method. And simultaneously, writing the mapping relation into a configuration register of the DRAM controller, and accessing the qualified bank by the DRAM controller according to the mapped address and shielding the damaged bank.

According to the LPDDR bank address mapping method, all banks of the LPDDR chip can be tested through a test algorithm, when the number of the qualified banks is not less than half of the total number of the banks of the LPDDR chip, all the banks of the LPDDR chip are remapped, the addresses of the qualified banks are mapped to the previous continuous bank address spaces, so that a DRAM controller can only access the previous qualified bank address spaces, the bad bank address spaces are shielded, and the utilization rate of the LPDDR chip is further improved.

In the description herein, references to the description of "one embodiment," "a further embodiment," "some specific embodiments," or "some examples," etc., mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for mapping a bank address of an LPDDR (low data density data register) is characterized by comprising the following steps:

respectively writing test data into and reading each bank of the LPDDR chip by a DRAM controller of the SOC chip by adopting a test algorithm;

respectively comparing whether the test data written in each bank is consistent with the read data, and if so, judging that the corresponding bank is qualified;

and if the qualified bank number is not less than half of the total bank number of the LPDDR chip, remapping all the addresses of the banks of the LPDDR chip according to a preset mapping relation, and mapping the qualified addresses of the banks to a plurality of previous continuous bank address spaces.

2. The method of claim 1, wherein the total number of banks of the LPDDR chip is 8.

3. The method according to claim 1 or 2, wherein the remapping of all the bank addresses of the LPDDR chip according to a predetermined mapping relationship maps a plurality of qualified bank addresses to a plurality of previous consecutive bank address spaces, specifically:

generating a mapping relation table by a bubble sorting method, remapping all the addresses of the banks of the LPDDR chip by the mapping relation table, and mapping the qualified addresses of a plurality of the banks to a plurality of previous continuous bank address spaces.

4. The method of LPDDR bank address mapping of claim 1, further comprising:

and writing the mapping relation into a configuration register of the DRAM controller, and accessing by the DRAM controller according to the mapped bank address.

5. The method of LPDDR bank address mapping of claim 1 wherein said test algorithm employs March C or Checkerboard.

6. The method of claim 1 or 5, wherein the LPDDR chip is determined to be defective if the number of qualified banks is less than half of the total number of banks of the LPDDR chip.