CN113433740A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN113433740A CN113433740A CN202110662967.6A CN202110662967A CN113433740A CN 113433740 A CN113433740 A CN 113433740A CN 202110662967 A CN202110662967 A CN 202110662967A CN 113433740 A CN113433740 A CN 113433740A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
- G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
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Abstract
The application discloses a display panel and a display device. The display panel comprises a color film substrate and an array substrate, wherein the color film substrate comprises a first substrate and a first electrode layer which are sequentially stacked, the array substrate comprises a second substrate, a signal layer and a second electrode layer which are sequentially stacked, and the display panel also comprises a barrier layer, wherein the barrier layer is attached to the surfaces of the first electrode layer, the second electrode layer and/or the second substrate and is positioned in a non-effective display area surrounding an effective display area; therefore, when the color film substrate and/or the array substrate are/is extruded by an external force, the barrier layer can isolate the electrode layer (namely, the first electrode layer) of the color film substrate from the electrode layer (namely, the second electrode layer) of the array substrate, so that the phenomenon of poor display of the display panel is avoided, and the display effect of the display panel is improved.
Description
Technical Field
The present application relates to the field of display panel technology, and in particular, to a display panel and a display device.
Background
Currently, there are an Active Area (AA) and a non-Active Area surrounding the Active Area in a liquid crystal display panel, wherein there are signal lines in the Active Area: data lines (also called data lines) and scan lines (also called gate lines). When the head ends or the tail ends (i.e. the non-effective display areas) of the data lines and the scanning lines are extruded by external force and fall off by foreign matters, pressure lines are easy to appear, so that the signal parts of the Color Filter (CF) substrate and the Array (Array) substrate are conducted, abnormal signals appear, and the normal display of the display panel is influenced.
Therefore, how to improve the display effect of the display panel is an urgent problem to be solved.
Disclosure of Invention
The main objective of the present application is to provide a display panel and a display device, where a barrier layer is disposed between a color film substrate and an array substrate, and the barrier layer can separate an electrode layer (i.e., a first electrode layer) of the color film substrate from an electrode layer (i.e., a second electrode layer) of the array substrate when the color film substrate and/or the array substrate is squeezed by an external force, so as to avoid a phenomenon of poor display of the display panel, and to improve a display effect of the display panel.
In order to achieve the above object, the present application provides a display panel, including a color film substrate and an array substrate, where the color film substrate includes a first substrate and a first electrode layer that are sequentially stacked, the array substrate includes a second substrate, a signal layer and a second electrode layer that are sequentially stacked, the signal layer includes a gate line and a data line, and the display panel further includes:
and the barrier layer is attached to the first electrode layer, the second electrode layer and/or the surface of the second substrate and is positioned in a non-effective display area surrounding the effective display area.
An embodiment of this application, the barrier layer includes a plurality of separation sections, and every separation section is laminated the setting respectively and is in first electrode layer surface or second electrode layer surface, just the position of every separation section laminating, with the gate line and/or the position one-to-one of data line.
In one embodiment of the present application, the signal layer includes:
the gate line is deposited on the surface of the second substrate base plate, the first insulating layer is deposited on the surface of the second substrate base plate, and the first insulating layer protrudes with an opposite top platform at the position corresponding to the gate line;
the data line structure comprises a second insulating layer deposited on the surface of the second substrate base plate, a data line deposited on the surface of the second insulating layer and a third insulating layer deposited on the surface of the second insulating layer, wherein a butting platform is protruded on the third insulating layer at a position corresponding to the data line.
In one embodiment of the present application, the first,
the second electrode layer is deposited on the surfaces of the first insulating layer and the gate line, and a butting platform protrudes from the second electrode layer at a position corresponding to the gate line;
the second electrode layer is further deposited on the third insulating layer and the surface of the data line, and a butting platform protrudes from the second electrode layer at a position corresponding to the data line.
The utility model provides an embodiment, the laminating of barrier layer sets up second electrode layer surface that the gate line corresponds, just the barrier layer is in the position protrusion that the gate line corresponds has the butt-top platform.
An embodiment of this application, the laminating of barrier layer sets up second electrode layer surface that the data line corresponds, just the barrier layer is in the position protrusion that the data line corresponds has the platform to the top.
In one embodiment of the present application, the barrier layer is made of a photoreactive LCD gap control material or an insulating material.
An embodiment of this application, the barrier layer is the support column, the support column laminating sets up second substrate base plate surface, just the height of support column is higher than the signal layer with the overall height of second electrode layer.
In an embodiment of the present application, the supporting pillar includes N1 layers, and the signal layer and the second electrode layer include N2 layers, where N1 is N2, and N1 and N2 are positive integers;
the i1 th layer of the support pillar is the same as the material of the i2 th layer of the signal layer and the second electrode layer, wherein i1 is equal to i2, and i1 and i2 are positive integers.
In order to achieve the above object, the present application further provides a display device, which includes the display panel as described above, further including a backlight module, a main control circuit board and a frame, wherein the display panel the backlight module and the main control circuit board are all assembled in the frame, and the main control circuit board is connected to the input circuit of the display panel.
According to the technical scheme, the display panel comprises a color film substrate and an array substrate, wherein the color film substrate comprises a first substrate and a first electrode layer which are sequentially stacked, the array substrate comprises a second substrate, a signal layer and a second electrode layer which are sequentially stacked, and the display panel further comprises a barrier layer, wherein the barrier layer is attached to the surfaces of the first electrode layer, the second electrode layer and/or the second substrate and is positioned in a non-effective display area surrounding an effective display area; therefore, when the color film substrate and/or the array substrate are/is extruded by external force, the barrier layer can isolate the electrode layer (namely, the first electrode layer) of the color film substrate from the electrode layer (namely, the second electrode layer) of the array substrate, so that the problem of poor display effect of the display panel in the prior art is solved, the phenomenon of poor display of the display panel is avoided, and the display effect of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the structures shown in the drawings without any inventive work.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a first detailed structural diagram of the display panel shown in FIG. 1;
FIG. 3 is a second detailed structural diagram of the display panel shown in FIG. 1;
FIG. 4 is a schematic diagram of a detailed structure of the display panel shown in FIG. 1;
FIG. 5 is a schematic diagram illustrating the effect of the display panel shown in FIG. 4 being squeezed;
FIG. 6 is a schematic structural diagram of a display panel according to a second embodiment of the present application;
FIG. 7 is a first detailed structural diagram of the display panel shown in FIG. 6;
FIG. 8 is a second detailed structural diagram of the display panel shown in FIG. 6;
FIG. 9 is a third schematic diagram illustrating a detailed structure of the display panel shown in FIG. 6;
fig. 10 is a schematic structural diagram of a display panel according to a third embodiment of the present application;
FIG. 11 is a schematic diagram of a detailed structure of the display panel shown in FIG. 10;
fig. 12 is a schematic structural diagram of a display device according to a fourth embodiment of the present application.
Description of reference numerals:
the implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The first embodiment is as follows:
referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application, where the display panel includes:
the color film substrate 1 comprises a first substrate 11 and a first electrode layer 12 which are sequentially stacked, the array substrate 2 comprises a second substrate 21, a signal layer 22 and a second electrode layer 23 which are sequentially stacked, and the signal layer 22 comprises a gate line and a data line; wherein, the display panel still includes:
and the barrier layer 3 is attached to the surface of the first electrode layer 12 and is positioned in the non-effective display area surrounding the effective display area.
The color film substrate 1 in the first embodiment of the present application includes: a first substrate 11 and a first electrode layer 12 stacked in this order; wherein:
the first substrate 11 may be a glass substrate, and the glass substrate may be classified into an alkali glass substrate and an alkali-free glass substrate. The alkali glass substrate comprises sodium glass and neutral borosilicate glass, is mostly applied to TN and STN LCDs, and is mainly produced by a floating method; the alkali-free Glass substrate is mainly made of alkali-free aluminosilicate Glass (such as SiO2, Al2O3, B2O3 and BaO, etc.), the total alkali metal content of the alkali-free aluminosilicate Glass is below 1%, the alkali-free aluminosilicate Glass substrate is mainly used for TFT-LCD, and the production is mainly carried out by an overflow fusion method.
The first electrode layer 12 may be made of a transparent conductive material, and since the transparent conductive material has a small grating effect, the influence of the grating effect and the diamond grains may be effectively reduced.
It should be noted that the color film substrate 1 may further include other layers, and in practical application, the color film substrate may be flexibly adjusted according to a specific application scenario.
The array substrate 2 in the first embodiment of the present application may be a Thin Film Transistor (TFT) array substrate, which includes: a second base substrate 21, a signal layer 22, and a second electrode layer 23 stacked in this order; wherein:
the second substrate 21 may be a glass substrate, which may be the same or different substrate as the first substrate 11.
Referring to fig. 1 again, the signal layer 22 includes a gate line 221 deposited on the surface of the second substrate 21, and a first insulating layer 222 deposited on the surface of the second substrate 21, and the first insulating layer 222 protrudes a pair of mesas 226 at positions corresponding to the gate line 221; and a second insulating layer 223 deposited on the surface of the second substrate 21, a data line 224 deposited on the surface of the second insulating layer 223, and a third insulating layer 225 deposited on the surface of the second insulating layer 223, wherein a pair of mesas 226 protrudes from the surface of the third insulating layer 225 at positions corresponding to the data line 224.
It is understood that the gate line 221 is mainly used to transmit a signal for turning on the switching element of each sub-pixel unit, which is driven by the gate driver; the data line 224 is mainly used to transmit a data signal of each pixel unit, and is driven by a source driver.
Referring to fig. 1 again, the second electrode layer 23 is deposited on the surfaces of the first insulating layer 222 and the gate line 221, and the second electrode layer 23 protrudes from the corresponding position of the gate line 221 with a pair of mesas 226; and the second electrode layer 23 is deposited on the surfaces of the third insulating layer 225 and the data line 224, and the second electrode layer 23 protrudes from the data line 224 with a pair of mesas 226.
It is understood that the second electrode layer 23 may be made of a transparent conductive material, and since the transparent conductive material has a small grating effect, the influence of the grating effect and the diamond grains may be effectively reduced, which may be made of the same or different conductive material as the first electrode layer 12.
It should be noted that the barrier layer 3 shown in fig. 1 is attached to the surface of the first electrode layer 12, in some examples, the barrier layer 3 may be attached to the surface of the second electrode layer 23 and/or the second substrate 21, and in practical applications, the barrier layer may be flexibly disposed according to a specific application scenario.
It should be understood that the gate line 221, the first insulating layer 222, and the second electrode layer 23 form a gate line end, and the second insulating layer 223, the data line 224, the third insulating layer 225, and the second electrode layer 23 form a data line end; a plurality of gate line terminals and a plurality of data line terminals are usually disposed on the second substrate 21, wherein the plurality is two or more, it can be understood that fig. 1 only illustrates 1 gate line terminal and 1 data line terminal, and in practical application, the number of the gate line terminals and the number of the data line terminals can be flexibly adjusted according to a specific application scenario.
It should be noted that the array substrate 2 may further include other layers, and in practical applications, the adjustment may be flexibly performed according to a specific application scenario.
In some examples of the first embodiment of the present application, if the blocking layer 3 is disposed on the surface of the first electrode layer 12 in an attaching manner, please refer to fig. 2, where the blocking layer 3 may include a plurality of blocking segments 31, where a plurality refers to two or more, each blocking segment 31 is disposed on the surface of the first electrode layer 12 in an attaching manner, and the attaching position of each blocking segment 31 may correspond to the position of each gate line 221 on the array substrate 2 one to one; fig. 2 illustrates 2 gate line ends and 1 data line end, and the barrier segments 31 have 2 total, and correspond to the positions of the gate line ends respectively.
In some examples of the first embodiment of the present invention, if the barrier layer 3 is disposed on the surface of the first electrode layer 12 in an attaching manner, please refer to fig. 3, where the barrier layer 3 may include a plurality of barrier segments 31, where a plurality refers to two or more, each barrier segment 31 is disposed on the surface of the first electrode layer 12 in an attaching manner, and the attaching position of each barrier segment 31 may correspond to the position of each data line 224 on the array substrate 2 one to one; fig. 3 shows 1 gate line end and 2 data line ends, and the total number of the barrier segments 31 is 2, which correspond to the positions of the data line ends.
In some examples of the first embodiment of the present invention, if the barrier layer 3 is disposed on the surface of the first electrode layer 12 in an attaching manner, please refer to fig. 4, the barrier layer 3 may include a plurality of barrier segments 31, wherein the plurality means two or more, each barrier segment 31 is disposed on the surface of the first electrode layer 12 in an attaching manner, and the attaching position of each barrier segment 31 may correspond to the position of each gate line 221 and each data line 224 on the array substrate 2 one to one; fig. 4 shows 1 gate line end and 2 data line ends, and the total number of the barrier segments 31 is 3, which correspond to the positions of the gate line end and the data line end respectively.
That is, when the barrier layer 3 is attached to the surface of the first electrode layer 12, the barrier layer may be a plurality of barrier segments 31 corresponding to the positions of each gate line 221 and/or each data line 224 one by one, so that the materials of the barrier layer 3 attached to the surface of the first electrode layer can be reduced, the cost can be saved, and the height of the barrier layer 3 can be flexibly set; in practical applications, the specific number of the barrier segments 31 is determined according to the gate line end and/or the data line end.
The barrier layer 3 in the first embodiment of the present application may be made of a photo-reactive LCD gap control material (PS) or an insulating material. Wherein, the photoreaction type LCD gap control material has the characteristics of proper mechanical strength, no pollution to liquid crystal molecules, film thickness uniformity, good density, good aging resistance, good chemical resistance and the like; the insulating material may be an organic insulating material such as epoxy resin, benzocyclobutene, or photo acryl, or may be an inorganic insulating material such as silicon oxide, silicon nitride, or the like.
Fig. 5 is a schematic view showing the effect of the display panel shown in fig. 4 being squeezed; when the color filter substrate 1 is squeezed by an external force, the plurality of barrier segments 31 attached to the surface of the first electrode layer 12 are squeezed by the external force, and at this time, according to the difference of the strength of the external force, the barrier segments 31 may contact with the gate line end and the data line end on the array substrate 2, so that the first electrode layer 12 of the color filter substrate 1 and the second electrode layer 23 of the array substrate 2 are isolated. In fig. 5, the external force intensity applied to the blocking section 31 located at the middle position is the greatest, and at this time, the blocking section 31 located at the left side is in contact with the second electrode layer 23 at the data line end in the middle of the array substrate 2, while the external force intensity applied to the blocking section 31 located at the left side is relatively smaller, and at this time, the blocking section 31 located at the right side is not in contact with the second electrode layer 23 at the gate line end on the left side of the array substrate 2, and the external force intensity applied to the blocking section 31 located at the right side is also relatively smaller, and at this time, the blocking section 31 located at the right side is not in contact with the second electrode layer 23 at the data line end on the right side of the array substrate 2; in practical application, the method is subject to specific application scenarios.
In the first embodiment of the application, the display panel includes a color film substrate and an array substrate, the color film substrate includes a first substrate and a first electrode layer which are sequentially stacked, the array substrate includes a second substrate, a signal layer and a second electrode layer which are sequentially stacked, and the display panel further includes a barrier layer, wherein the barrier layer is attached to the surface of the first electrode layer and is located in a non-effective display area surrounding an effective display area; therefore, when the color film substrate and/or the array substrate are/is extruded by external force, the barrier layer can isolate the electrode layer (namely, the first electrode layer) of the color film substrate from the electrode layer (namely, the second electrode layer) of the array substrate, so that the problem of poor display effect of the display panel in the prior art is solved, the phenomenon of poor display of the display panel is avoided, and the display effect of the display panel is improved.
Example two:
referring to fig. 6, fig. 6 is a schematic structural diagram of a display panel according to a second embodiment of the present application, where the display panel includes:
the color film substrate 1 comprises a first substrate 11 and a first electrode layer 12 which are sequentially stacked, the array substrate 2 comprises a second substrate 21, a signal layer 22 and a second electrode layer 23 which are sequentially stacked, and the signal layer 22 comprises a gate line and a data line; wherein, the display panel still includes:
and the barrier layer 3 is attached to the surface of the second electrode layer 23 and is positioned in the non-effective display area surrounding the effective display area.
Please refer to the description of the first embodiment for the color film substrate 1 and the array substrate 2 in the second embodiment of the present application, which is not repeated herein.
In some examples of the second embodiment of the present application, if the blocking layer 3 is attached to the surface of the second electrode layer 23, please refer to fig. 7, the blocking layer 3 may be attached to the surface of the second electrode layer 23 corresponding to the gate line 221, and the blocking layer 3 protrudes from the position corresponding to the gate line 221 to form a counter-top 226; fig. 7 illustrates 2 gate line terminals and 1 data line terminal, and the barrier layer 3 is attached to the surface of the second electrode layer 23 at the gate line terminal.
In some examples of the second embodiment of the present application, if the barrier layer 3 is attached to the surface of the second electrode layer 23, please refer to fig. 8, the barrier layer 3 may be attached to the surface of the second electrode layer 23 corresponding to the data line 224, and the counter-mesa 226 protrudes from the barrier layer 3 at a position corresponding to the data line 224; fig. 8 illustrates 1 gate line end and 2 data line ends, and the barrier layer 3 is attached to the surface of the second electrode layer 23 at the data line end.
In some examples of the second embodiment of the present application, if the blocking layer 3 is attached to the surface of the second electrode layer 23, please refer to fig. 9, the blocking layer 3 may be attached to the surface of the second electrode layer 23 corresponding to the gate line 221 and the data line 224, and the blocking layer 3 protrudes from the position corresponding to the gate line 221 and the data line 224 to form a pair of mesas 226; fig. 9 illustrates 2 gate line terminals and 1 data line terminal, and the barrier layer 3 is respectively attached to the surfaces of the second electrode layers 23 at the gate line terminals and the data line terminals.
That is, when the laminating of barrier layer 3 set up on second electrode layer 23 surface, barrier layer 3 can laminate and set up on second electrode layer 23 surface that gate line 221 and/or data line 224 correspond respectively, and barrier layer 3's height can set up in a flexible way simultaneously, in practical application, can carry out nimble adjustment according to specific application scene.
Please refer to the description of the first embodiment for the barrier layer 3 in the second embodiment of the present application, which is not repeated herein.
In the second embodiment of the present application, the display panel includes a color film substrate and an array substrate, the color film substrate includes a first substrate and a first electrode layer that are sequentially stacked, the array substrate includes a second substrate, a signal layer and a second electrode layer that are sequentially stacked, and the display panel further includes a barrier layer, wherein the barrier layer is attached to a surface of the second electrode layer and is located in a non-effective display area surrounding an effective display area; therefore, when the color film substrate and/or the array substrate are/is extruded by external force, the barrier layer can isolate the electrode layer (namely, the first electrode layer) of the color film substrate from the electrode layer (namely, the second electrode layer) of the array substrate, so that the problem of poor display effect of the display panel in the prior art is solved, the phenomenon of poor display of the display panel is avoided, and the display effect of the display panel is improved.
Example three:
referring to fig. 10, fig. 10 is a schematic structural diagram of a display panel in the third embodiment of the present application, where the display panel includes:
the color film substrate 1 comprises a first substrate 11 and a first electrode layer 12 which are sequentially stacked, the array substrate 2 comprises a second substrate 21, a signal layer 22 and a second electrode layer 23 which are sequentially stacked, and the signal layer 22 comprises a gate line and a data line; wherein, the display panel still includes:
and the barrier layer 3 is attached to the surface of the second substrate 21 and is located in the non-effective display area surrounding the effective display area.
Please refer to the description of the first embodiment for the color film substrate 1 and the array substrate 2 in the third embodiment of the present application, which is not repeated herein.
In some examples of the third embodiment of the present application, if the barrier layer 3 is attached to the surface of the second substrate 21, please refer to fig. 11, the barrier layer 3 may be a supporting pillar 32, for example, a Dummy supporting pillar, where the supporting pillar 32 is attached to the surface of the second substrate 21, and a height H1 of the supporting pillar 32 is higher than a total height H2 of the signal layer 22 and the second electrode layer 23; fig. 11 illustrates 1 gate line end, 1 data line end, and 1 support post, and the height of the gate line end and the height of the data line end are all H2. If the heights of the gate line end and the data line end are different, the supporting column 32 is higher than the higher one of the gate line end and the data line end; that is, the supporting posts 32 are higher than the gate line end and the data line end at the same time. In practical applications, the number of the supporting columns 32 can be flexibly adjusted according to specific application scenarios, for example, the supporting columns 32 are attached to the surface of the second substrate 21 according to a certain rule, or the supporting columns 32 are attached to the surface of the second substrate 21 randomly. It is understood that the supporting pillar 32 includes N1 layers, and the signal layer 22 and the second electrode layer 23 include N2 layers, where N1 is N2, and N1 and N2 are positive integers; the i1 th layer of the supporting pillar 32 is made of the same material as the i2 th layer of the signal layer 22 and the second electrode layer 23, wherein i1 is i2, and i1 and i2 are positive integers. That is, the supporting pillars 32 and the array substrate 2 are manufactured in the same process, so that the manufacturing time of the supporting pillars 32 can be saved, and the complexity of the manufacturing process can be reduced.
For example, the following steps are carried out:
the number of layers of the supporting pillars 32 may be respectively one-to-one corresponding to the number of layers of the gate line ends, that is, the supporting pillars 32 may include the gate lines, the first insulating layers, and the second electrode layers, which are sequentially stacked, and the difference is that the height of the supporting pillars 32 is higher than the height of the gate line ends; the height of one layer of the support pillars 32 may be higher than that of the corresponding gate line end, for example, the height of the i1 th layer of the support pillars 32 is higher than that of the i2 th layer of the gate line end, where i1 is equal to i2, or the heights of the layers of the support pillars 32 are respectively higher than that of the i2 th layer of the corresponding gate line end, for example, the height of the i1 th layer of the support pillars 32 is higher than that of the i2 th layer of the gate line end, and the height of the i3 th layer of the support pillars 32 is higher than that of the i4 th layer of the gate line end, where i1 is equal to i 63 2 and i3 is equal to i 4.
The number of layers of the supporting column 32 may be respectively one-to-one corresponding to the number of layers of the data line end, that is, the supporting column 32 may include a second insulating layer, a data line, a third insulating layer, and a second electrode layer, which are sequentially stacked, and the difference is that the height of the supporting column 32 is higher than that of the data line end; the height of one layer of the supporting pillars 32 may be higher than that of the corresponding data line end, for example, the height of the i1 th layer of the supporting pillars 32 is higher than that of the i2 th layer of the data line end, where i1 is equal to i2, or the heights of the layers of the supporting pillars 32 are respectively higher than that of the corresponding data line end, for example, the height of the i1 th layer of the supporting pillars 32 is higher than that of the i2 th layer of the data line end, and the height of the i3 th layer of the supporting pillars 32 is higher than that of the i4 th layer of the data line end, where i1 is equal to i 63 2, and i3 is equal to i 4.
It will be appreciated that the fabrication process of the support posts 32 and the array substrate 2 may be different, which provides greater flexibility.
For example, the following steps are carried out:
the number of partial layers of the supporting column 32 may be respectively one-to-one corresponding to the number of layers of the gate line end, and each of the partial layers may be respectively the same as the height of each of the layers of the gate line end, for example, the supporting column 32 may include a gate line, a first insulating layer, a second electrode layer, and a color resistance layer, which are sequentially stacked; the color resistance layer can be any one or more of a red color resistance layer, a green color resistance layer and a blue color resistance layer. That is, the support pillar 32 is higher than the gate line end due to the arrangement of the color resist layer, wherein the higher the color resist layer is, the higher the support pillar 32 is.
The number of partial layers of the supporting column 32 may be respectively one-to-one corresponding to the number of layers of the data line end, and each of the partial layers may be respectively the same as the height of each of the layers of the data line end, for example, the supporting column 32 may include a second insulating layer, a data line, a third insulating layer, a second electrode layer, and a color resistance layer, which are sequentially stacked; the color resistance layer can be any one or more of a red color resistance layer, a green color resistance layer and a blue color resistance layer. That is, the support posts 32 are higher than the data line end due to the arrangement of the color resist layer, wherein the higher the color resist layer is, the higher the support posts 32 are.
The number of partial layers of the supporting column 32 may be respectively one-to-one corresponding to the number of layers of the gate line end, and each of the partial layers may be respectively the same as the height of each of the layers of the gate line end, for example, the supporting column 32 may include a gate line, a first insulating layer, a second electrode layer, and an insulating layer, which are sequentially stacked; the insulating layer can be made of any form of insulating material. That is, the support pillar 32 is higher than the gate line end due to the provision of the insulating layer, wherein the higher the insulating layer, the higher the support pillar 32.
The number of partial layers of the supporting column 32 may be respectively one-to-one corresponding to the number of layers of the data line end, and each of the partial layers may be respectively the same as the height of each of the layers of the data line end, for example, the supporting column 32 may include a second insulating layer, a data line, a third insulating layer, a second electrode layer, and an insulating layer, which are sequentially stacked; the insulating layer can be made of any form of insulating material. That is, the support posts 32 are higher than the data line end due to the provision of the insulating layer, wherein the higher the insulating layer, the higher the support posts 32.
The number of partial layers of the supporting column 32 may correspond to the number of layers of the gate line end one to one, respectively, and each of the partial layers may have the same height as that of each of the gate line end, respectively, for example, the supporting column 32 may include a gate line, a first insulating layer, a second electrode layer, and a PS layer, which are sequentially stacked. That is, the support pillars 32 are higher than the gate line end due to the arrangement of the PS layer, wherein the higher the PS layer is, the higher the support pillars 32 are.
The number of partial layers of the supporting column 32 may correspond to the number of layers of the data line end one to one, and each of the partial layers may have the same height as that of each of the data line end, for example, the supporting column 32 may include a second insulating layer, a data line, a third insulating layer, a second electrode layer, and a PS layer, which are sequentially stacked. That is, the support posts 32 are higher than the data line end due to the arrangement of the PS layer, wherein the higher the PS layer is, the higher the support posts 32 are.
It should be noted that the supporting column 32 may further include any two or more layers of a color resistance layer, an insulating layer, and a PS layer, and the stacking order and the heights of the layers may be flexibly adjusted according to a specific application scenario, which is not described herein any more.
It should be noted that, in the first embodiment, three positions respectively illustrated in fig. 1, fig. 6 in the second embodiment, and fig. 10 in the third embodiment are provided for the barrier layer 3 to be attached, where the three attaching positions may be combined arbitrarily, for example, the barrier layer 3 may be attached to the surfaces of the first electrode layer 12 and the second electrode layer 23 at the same time, or the barrier layer 3 may be attached to the surfaces of the first electrode layer 12 and the second substrate 21 at the same time, or the barrier layer 3 may be attached to the surfaces of the second electrode layer 23 and the second substrate 21 at the same time, or the barrier layer 3 may be attached to the surfaces of the first electrode layer 12, the second electrode layer 23, and the second substrate 21 at the same time; in practical application, the laminating position of the barrier layer 3 can be flexibly adjusted according to specific application scenes.
In the third embodiment of the present application, the display panel includes a color film substrate and an array substrate, the color film substrate includes a first substrate and a first electrode layer which are sequentially stacked, the array substrate includes a second substrate, a signal layer and a second electrode layer which are sequentially stacked, and the display panel further includes a barrier layer, wherein the barrier layer is attached to a surface of the second substrate and is located in a non-effective display area surrounding an effective display area; therefore, when the color film substrate and/or the array substrate are/is extruded by external force, the barrier layer can isolate the electrode layer (namely, the first electrode layer) of the color film substrate from the electrode layer (namely, the second electrode layer) of the array substrate, so that the problem of poor display effect of the display panel in the prior art is solved, the phenomenon of poor display of the display panel is avoided, and the display effect of the display panel is improved.
Example four:
in addition, a display device is further provided in the fourth embodiment of the present application on the basis of the display panels in the above embodiments, please refer to fig. 12, where fig. 12 is a schematic structural diagram of the display device in the fourth embodiment of the present application, and the display device 5 includes:
as for the display panel 4 of the above embodiment, the display panel 4 further includes a backlight module, a main control circuit board and a frame (not shown in fig. 12), the display panel 4, the backlight module and the main control circuit board are all assembled in the frame, and the main control circuit board is connected to the input circuit of the display panel 4. It should be noted that the display device in the fourth embodiment of the present application may further include other components, and in practical applications, the display device may be flexibly adjusted according to a specific application scenario.
The display device in the fourth embodiment of the present application may be implemented in various forms, wherein the display device may include a mobile display device such as a mobile phone, a tablet computer, a notebook computer, a palm top computer, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable device, a smart band, a pedometer, and a fixed display device such as a Digital TV, a desktop computer, and the like.
It should be noted that the display panel in the fourth embodiment of the present application has been described in detail above, and is not described again.
In the fourth embodiment of the present application, the display device includes a display panel, where the display panel includes a color film substrate and an array substrate, the color film substrate includes a first substrate and a first electrode layer that are sequentially stacked, the array substrate includes a second substrate, a signal layer and a second electrode layer that are sequentially stacked, and the display panel further includes a barrier layer, where the barrier layer is attached to the surfaces of the first electrode layer, the second electrode layer and/or the second substrate and is located in a non-effective display area surrounding an effective display area; therefore, when the color film substrate and/or the array substrate are/is extruded by external force, the barrier layer can isolate the electrode layer (namely, the first electrode layer) of the color film substrate from the electrode layer (namely, the second electrode layer) of the array substrate, so that the problem of poor display effect of the display panel in the prior art is solved, the phenomenon of poor display of the display panel is avoided, the display effect of the display panel is improved, the display effect of the display device is improved, and the display device is more beneficial to popularization and use.
In the fourth embodiment of the present application, all technical solutions of the above embodiments are adopted, so that at least all beneficial effects brought by the technical solutions of the above embodiments are achieved, and details are not repeated herein.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.
Claims (10)
1. The utility model provides a display panel, includes various membrane base plate and array substrate, various membrane base plate is including the first substrate base plate and the first electrode layer that stack gradually, array substrate is including the second substrate base plate, signal layer and the second electrode layer that stack gradually, the signal layer includes gate line and data line, its characterized in that, display panel still includes:
and the barrier layer is attached to the first electrode layer, the second electrode layer and/or the surface of the second substrate and is positioned in a non-effective display area surrounding the effective display area.
2. The display panel of claim 1, wherein the barrier layer comprises a plurality of barrier segments, each barrier segment is respectively attached to the surface of the first electrode layer or the surface of the second electrode layer, and the attachment position of each barrier segment corresponds to the position of the gate line and/or the data line.
3. The display panel of claim 1, wherein the signal layer comprises:
the gate line is deposited on the surface of the second substrate base plate, the first insulating layer is deposited on the surface of the second substrate base plate, and the first insulating layer protrudes with an opposite top platform at the position corresponding to the gate line;
the data line structure comprises a second insulating layer deposited on the surface of the second substrate base plate, a data line deposited on the surface of the second insulating layer and a third insulating layer deposited on the surface of the second insulating layer, wherein a butting platform is protruded on the third insulating layer at a position corresponding to the data line.
4. The display panel of claim 3,
the second electrode layer is deposited on the surfaces of the first insulating layer and the gate line, and a butting platform protrudes from the second electrode layer at a position corresponding to the gate line;
the second electrode layer is further deposited on the third insulating layer and the surface of the data line, and a butting platform protrudes from the second electrode layer at a position corresponding to the data line.
5. The display panel of claim 4, wherein the blocking layer is attached to the surface of the second electrode layer corresponding to the gate line, and the blocking layer protrudes from the position corresponding to the gate line to form an opposite platform.
6. The display panel according to claim 4, wherein the barrier layer is attached to a surface of the second electrode layer corresponding to the data line, and a counter-top is protruded from the barrier layer at a position corresponding to the data line.
7. The display panel of any one of claims 1-6, wherein the barrier layer is made of a photoreactive LCD gap control material or an insulating material.
8. The display panel of claim 1, wherein the barrier layer is a support pillar, the support pillar is attached to the surface of the second substrate, and the height of the support pillar is higher than the total height of the signal layer and the second electrode layer.
9. The display panel according to claim 8, wherein the support pillar comprises N1 layers, and the signal layer and the second electrode layer comprise N2 layers in total, wherein N1 is N2, and N1 and N2 are positive integers;
the i1 th layer of the support pillar is the same as the material of the i2 th layer of the signal layer and the second electrode layer, wherein i1 is equal to i2, and i1 and i2 are positive integers.
10. A display device, comprising the display panel according to any one of claims 1 to 9, further comprising a backlight module, a main control circuit board and a frame, wherein the display panel, the backlight module and the main control circuit board are all assembled in the frame, and the main control circuit board is connected with an input circuit of the display panel.
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| CN202110662967.6A CN113433740A (en) | 2021-06-15 | 2021-06-15 | Display panel and display device |
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| CN202110662967.6A CN113433740A (en) | 2021-06-15 | 2021-06-15 | Display panel and display device |
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| CN106896556A (en) * | 2017-02-28 | 2017-06-27 | 厦门天马微电子有限公司 | Array base palte and its manufacture method, display panel and display device |
| CN209590482U (en) * | 2019-04-17 | 2019-11-05 | 成都中电熊猫显示科技有限公司 | Liquid crystal display panel and display device |
| CN209911710U (en) * | 2019-06-12 | 2020-01-07 | 重庆惠科金渝光电科技有限公司 | Liquid crystal panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106896556A (en) * | 2017-02-28 | 2017-06-27 | 厦门天马微电子有限公司 | Array base palte and its manufacture method, display panel and display device |
| CN209590482U (en) * | 2019-04-17 | 2019-11-05 | 成都中电熊猫显示科技有限公司 | Liquid crystal display panel and display device |
| CN209911710U (en) * | 2019-06-12 | 2020-01-07 | 重庆惠科金渝光电科技有限公司 | Liquid crystal panel and display device |
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