CN113422411A - PD charging circuit and POS machine - Google Patents

PD charging circuit and POS machine Download PDF

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Publication number
CN113422411A
CN113422411A CN202110728097.8A CN202110728097A CN113422411A CN 113422411 A CN113422411 A CN 113422411A CN 202110728097 A CN202110728097 A CN 202110728097A CN 113422411 A CN113422411 A CN 113422411A
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CN
China
Prior art keywords
voltage
resistor
usb
circuit
output
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Pending
Application number
CN202110728097.8A
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Chinese (zh)
Inventor
周超超
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PAX Computer Technology Shenzhen Co Ltd
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PAX Computer Technology Shenzhen Co Ltd
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Application filed by PAX Computer Technology Shenzhen Co Ltd filed Critical PAX Computer Technology Shenzhen Co Ltd
Priority to CN202110728097.8A priority Critical patent/CN113422411A/en
Publication of CN113422411A publication Critical patent/CN113422411A/en
Priority to PCT/CN2022/096349 priority patent/WO2023273774A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00036—Charger exchanging data with battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/0071—Regulation of charging or discharging current or voltage with a programmable schedule
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters

Abstract

A PD charging circuit and a POS machine belong to the field of USB charging, and identify signals and power supply voltage through a power supply management circuit according to a first USB voltage output by first equipment and/or a second USB voltage output by second equipment; the control circuit outputs a first control signal according to the port identification signal; the first switching circuit forwards the first configuration channel interaction signal according to the control signal so that the first equipment maintains to output a first USB voltage, or forwards the second configuration channel interaction signal so that the second equipment maintains to output a second USB voltage; the energy storage assembly outputs a battery state signal; the control circuit outputs a second control signal according to the battery state signal so that the power management circuit converts the first USB voltage or the second USB voltage into a power supply voltage and a charging voltage for charging the energy storage assembly; therefore, the charging requirement under the conditions of multi-path USB voltage power supply and different battery charging sections is met.

Description

PD charging circuit and POS machine
Technical Field
The application belongs to the field of USB charging, and particularly relates to a PD charging circuit and a POS machine.
Background
A conventional Power Delivery Protocol (PD) charging circuit converts a Universal Serial Bus (USB) voltage output from an external device into a charging voltage to charge a battery. However, the conventional PD charging circuit cannot charge when the PD charging circuit has two USB interfaces (the two USB interfaces can respectively transfer two USB voltages output by two external devices) and the battery may be a single battery, a double battery or a quadruple battery.
Therefore, the traditional PD charging circuit can not meet the charging requirement under the conditions of multi-path USB voltage power supply and charging of batteries with different numbers.
Disclosure of Invention
The application aims to provide a PD charging circuit and a point of sale (POS) machine, and aims to overcome the defect that a traditional PD charging circuit cannot meet the charging requirement under the conditions of multi-path USB voltage power supply and charging of batteries with different numbers.
The embodiment of the application provides a PD charging circuit, includes:
the power management circuit is connected with the first device and/or the second device and is configured to output a port identification signal and a supply voltage according to the first USB voltage and/or the second USB voltage when receiving the first USB voltage output by the first device and/or the second USB voltage output by the second device; the power supply voltage is used for supplying power to each functional circuit;
the control circuit is connected with the power management circuit and is configured to output a first control signal according to the port identification signal;
the first switching circuit is used for being connected with the first device and/or the second device, and is also connected with the control circuit, and is configured to forward a first configuration channel interaction signal according to a first level of the control signal so as to enable the first device to keep outputting the first USB voltage, or forward a second configuration channel interaction signal according to a second level of the control signal so as to enable the second device to keep outputting the second USB voltage; wherein the first configuration channel interaction signal is a half-duplex communication signal between the control circuit and the first device; the second configuration channel interaction signal is a half-duplex communication signal between the control circuit and the second device;
the energy storage assembly is connected with the control circuit and configured to output a battery state signal;
the control circuit is further configured to output a second control signal according to the battery status signal;
the power management circuit is further configured to convert the first USB voltage or the second USB voltage into the supply voltage and a charging voltage according to the second control signal, where the charging voltage is used to charge the energy storage component.
In one embodiment, the method further comprises the following steps:
the second switching circuit is connected with the first device and/or the second device, is also connected with the control circuit, and is configured to forward a first USB data signal output by the first device according to the control signal of a first level or forward a second USB data signal output by the second device according to the control signal of a second level;
the control circuit is further configured to receive the first USB data signal or the second USB data signal.
In one embodiment, the second switching circuit includes a first analog switch, a first TVS transistor, a second TVS transistor, a first capacitor, a first resistor, a second resistor, and a third resistor;
the first positive data input end of the first analog switch and the first negative data input end of the first analog switch are connected to the first USB data signal input end of the second switching circuit, the second positive data input end of the first analog switch and the second negative data input end of the first analog switch are connected to the second USB data signal input end of the second switching circuit, the positive data input output end of the first analog switch and the negative data input output end of the first analog switch are connected to the first USB data signal output end of the second switching circuit and the second USB data signal output end of the second switching circuit, the selection end of the first analog switch is connected to the first end of the first TVS tube, the first end of the first capacitor and the first end of the first resistor, the second end of the first resistor and the first end of the second resistor are connected to the second switching circuit The output enable end of the first analog switch is connected with the first end of the second TVS tube and the first end of the third resistor, and the second end of the first TVS tube, the second end of the second TVS tube, the second end of the first capacitor, the second end of the second resistor and the second end of the third resistor are connected to a power ground in common.
In one embodiment, the method further comprises the following steps:
a first USB interface, connected to the first device, the power management circuit, the first switching circuit, and the second switching circuit, and configured to forward the first USB data signal, the first configuration channel interaction signal, and the first USB voltage.
In one embodiment, the method further comprises the following steps:
a second USB interface, connected to the second device, the power management circuit, the first switching circuit, and the second switching circuit, and configured to forward the second USB data signal, the second configuration channel interaction signal, and the second USB voltage.
In one embodiment, the first switching circuit includes a second analog switch, a third TVS transistor, a fourth TVS transistor, a second capacitor, a fourth resistor, a fifth resistor, and a sixth resistor;
a first positive data input terminal of the second analog switch and a first negative data input terminal of the second analog switch are commonly connected to a first configuration channel interaction signal input/output terminal of the first switching circuit, a second positive data input terminal of the second analog switch and a second negative data input terminal of the second analog switch are commonly connected to a second configuration channel interaction signal input/output terminal of the first switching circuit, a positive data input/output terminal of the second analog switch and a negative data input/output terminal of the second analog switch are commonly connected to a first configuration channel interaction signal input/output terminal of the first switching circuit and a second configuration channel interaction signal input/output terminal of the first switching circuit, a selection terminal of the second analog switch U2 is connected to a first terminal of the third TVS tube, a first terminal of the second capacitor and a first terminal of the fourth resistor, the second end of the fourth resistor and the first end of the sixth resistor are connected to the first control signal input end of the first switching circuit, the output enable end of the second analog switch is connected with the first end of the fourth TVS tube and the first end of the fifth resistor, and the second end of the third TVS tube, the second end of the fourth TVS tube, the second end of the second capacitor, the second end of the fifth resistor and the second end of the sixth resistor are connected to a power ground in common.
In one embodiment, the control circuit comprises a microprocessor;
a first PD configuration channel end of the microprocessor and a second PD configuration channel end of the microprocessor are commonly connected to a first configuration channel interaction signal input-output end of the control circuit and a second configuration channel interaction signal input-output end of the control circuit, a peripheral enable end of the microprocessor is connected to a first control signal output end of the control circuit, a first serial data end of the microprocessor and a first serial clock end of the microprocessor are commonly connected to a port identification signal input end of the control circuit and a second control signal output end of the control circuit, a second serial data end of the microprocessor and a second serial clock end of the microprocessor are commonly connected to a battery state signal input end of the control circuit, a positive USB data input end of the microprocessor and a negative USB data input end of the microprocessor are commonly connected to a first USB data signal input end of the control circuit and a negative USB data input end of the microprocessor And the second USB data signal input end of the control circuit.
In one embodiment, the power management circuit includes a voltage reduction chip, a first inductor, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first voltage regulator, a second voltage regulator, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor;
a first power input end of the voltage reduction chip is connected with a first end of the eleventh resistor, a second power input end of the voltage reduction chip is connected with a first end of the twelfth resistor, a second end of the eleventh resistor and a drain electrode of the second field-effect transistor are commonly connected to a first USB voltage input end of the power management circuit, and a second end of the twelfth resistor and a drain electrode of the fourth field-effect transistor are commonly connected to a second USB voltage input end of the power management circuit;
a source electrode of the second field effect transistor is connected with a first end of the eighth resistor, a first end of the seventh capacitor, an anode of the first voltage regulator tube and a source electrode of the first field effect transistor, a grid electrode of the second field effect transistor is connected with a second end of the eighth resistor, a second end of the seventh capacitor, a cathode of the first voltage regulator tube, a first end of the seventh resistor and a grid electrode of the first field effect transistor, and a second end of the seventh resistor is connected with a first power supply driving output end of the voltage reduction chip;
a source electrode of the fourth field effect transistor is connected with a first end of the tenth resistor, a first end of the eighth capacitor, a positive electrode of the second voltage regulator tube and a source electrode of the third field effect transistor, a grid electrode of the fourth field effect transistor is connected with a second end of the tenth resistor, a second end of the eighth capacitor, a negative electrode of the second voltage regulator tube, a first end of the ninth resistor and a grid electrode of the third field effect transistor, and a second end of the ninth resistor is connected with a second power supply driving output end of the voltage reduction chip;
the drain electrode of the first field effect transistor is connected with the drain electrode of the third field effect transistor, the first end of the ninth capacitor and a bus power supply end of the voltage reduction chip;
the battery power supply output end of the voltage reduction chip and the first end of the sixth capacitor are connected to the charging voltage output end of the power management circuit together, the system power supply output end of the voltage reduction chip and the first end of the fifth capacitor are connected to the power supply voltage output end of the power management circuit together, and the serial data output end of the voltage reduction chip and the serial clock output end of the voltage reduction chip are connected to the port identification signal output end of the power management circuit together;
the first soft start end of the voltage reduction chip is connected with the first end of the third capacitor, and the second end of the third capacitor is connected with the first channel first switch end of the voltage reduction chip, the first channel second switch end of the voltage reduction chip, the first channel third switch end of the voltage reduction chip, the first channel fourth switch end of the voltage reduction chip, the first channel fifth switch end of the voltage reduction chip and the first end of the first inductor;
the second soft start end of the voltage reduction chip is connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is connected with the second channel first switch end of the voltage reduction chip, the second channel second switch end of the voltage reduction chip, the second channel third switch end of the voltage reduction chip, the second channel fourth switch end of the voltage reduction chip, the second channel fifth switch end of the voltage reduction chip and the second end of the first inductor;
the second end of the fifth capacitor, the second end of the sixth capacitor and the second end of the ninth capacitor are connected to a power ground in common.
In one embodiment, the method further comprises the following steps:
the starting circuit is used for being connected with first equipment and/or second equipment, is also connected with the control circuit, the first switching circuit and the power management circuit, and is configured to forward the first configuration channel interaction signal to enable the first equipment to output a first USB voltage when power supply voltage is not received; and/or when the power supply voltage is not received, forwarding the second configuration channel interaction signal to enable the second equipment to output a second USB voltage;
the start-up circuit is further configured to stop forwarding the first configuration channel interaction signal and/or the first configuration channel interaction signal according to the supply voltage.
The embodiment of the application also provides a POS machine, which comprises the PD charging circuit.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the first switching circuit forwards the first configuration channel interaction signal or the second configuration channel interaction signal according to the control signal so as to enable the first equipment to maintain to output the first USB voltage or enable the second equipment to maintain to output the second USB voltage, and therefore power supply of multiple paths of USB voltages is achieved; the control circuit outputs a second control signal according to the battery state signal output by the energy storage assembly so that the power management circuit converts the first USB voltage or the second USB voltage into a charging voltage; the charging voltage is output according to the battery state, and the charging requirements of batteries with different numbers are met; therefore, the charging requirement under the conditions of multi-path USB voltage power supply and different battery charging sections is met.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 is a schematic structural diagram of a PD charging circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of another structure of a PD charging circuit according to an embodiment of the present application;
fig. 3 is a schematic diagram of another structure of a PD charging circuit according to an embodiment of the present application;
fig. 4 is a schematic diagram of another structure of a PD charging circuit according to an embodiment of the present application;
fig. 5 is a schematic diagram of another structure of a PD charging circuit according to an embodiment of the present application;
fig. 6 is a schematic circuit diagram of an example PD charging circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 1 shows a schematic structural diagram of a PD charging circuit according to a preferred embodiment of the present application, and for convenience of description, only the relevant portions of the PD charging circuit are shown, which are detailed as follows:
the PD charging circuit includes a power management circuit 11, a control circuit 12, a first switching circuit 13, and an energy storage device 14.
The power management circuit 11 is connected with the first device 81 and/or the second device 82 and configured to output a port identification signal and a supply voltage according to the first USB voltage and/or the second USB voltage when receiving the first USB voltage output by the first device 81 and/or the second USB voltage output by the second device 82; the power supply voltage is used for supplying power to each functional circuit;
a control circuit 12 connected to the power management circuit 11 and configured to output a first control signal according to the port identification signal;
the first switching circuit 13 is configured to forward the first configuration channel interaction signal according to a control signal at a first level to enable the first device 81 to maintain output of the first USB voltage, or forward the second configuration channel interaction signal according to a control signal at a second level to enable the second device 82 to maintain output of the second USB voltage; wherein, the first configuration channel interaction signal is a half-duplex communication signal between the control circuit 12 and the first device 81; the second configuration channel interaction signal is a half-duplex communication signal between the control circuit 12 and the second device 82;
the energy storage assembly 14 is connected with the control circuit 12 and configured to output a battery state signal; the energy storage assembly 14 may be a battery.
The control circuit 12 is further configured to output a second control signal in accordance with the battery status signal;
the power management circuit 11 is further configured to convert the first USB voltage or the second USB voltage into a supply voltage and a charging voltage according to the second control signal, wherein the charging voltage is used for charging the energy storage component 14.
In specific implementation, the port identification signal may carry first port information or second port information; the power management circuit 11 is specifically configured to output a port identification signal carrying a first port signal according to the first USB voltage; outputting a port identification signal carrying a second port signal according to the second USB voltage; and outputting a port identification signal carrying the first port signal according to the first USB voltage and the second USB voltage.
The control circuit 12 is specifically configured to output a control signal of a first level according to the first port information or a control signal of a second level according to the second port information.
The battery status signal carries battery status information including battery cell count, battery voltage, and battery rated voltage.
Wherein the first device 81 and the second device 82 may be a terminal device, an adapter or a docking station, respectively.
In particular implementations, the energy storage assembly 14 is further configured to output a battery voltage; the power management circuit 11 is also configured to convert the battery voltage to a supply voltage. When the first device 81 and the second device 82 are not externally connected, the energy storage component 14 supplies power to the PD charging circuit.
As shown in fig. 2, the PD charging circuit further includes a second switching circuit 15.
The second switching circuit 15 is connected to the first device 81 and/or the second device 82, and is further connected to the control circuit 12, and configured to forward the first USB data signal output by the first device 81 according to the control signal of the first level or forward the second USB data signal output by the second device 82 according to the control signal of the second level.
The control circuit 12 is also configured to receive either the first USB data signal or the second USB data signal.
The signal switching function in the two USB data signal links is realized by the second switching circuit 15.
As shown in fig. 3, the PD charging circuit further includes a first USB interface 16.
The first USB interface 16 is connected to the first device 81, the power management circuit 11, the first switching circuit 13, and the second switching circuit 15, and configured to forward the first USB data signal, the first configuration channel interaction signal, and the first USB voltage.
The connection of the PD charging circuit to the external first device 81 is realized through the first USB interface 16.
As shown in fig. 4, the PD charging circuit further includes a second USB interface 17.
The second USB interface 17 is connected to the second device 82, the power management circuit 11, the first switching circuit 13, and the second switching circuit 15, and configured to forward the second USB data signal, the second configuration channel interaction signal, and the second USB voltage.
The connection of the PD charging circuit to the external second device 82 is realized via the second USB interface 17.
As shown in fig. 5, the PD charging circuit further includes a start-up circuit 18.
The starting circuit 18 is connected to the first device 81 and/or the second device 82, and is further connected to the control circuit 12, the first switching circuit 13, and the power management circuit 11, and configured to forward the first configuration channel interaction signal to enable the first device 81 to output the first USB voltage when the power supply voltage is not received; and/or when the supply voltage is not received, forwarding the second configuration channel interaction signal to cause the second device 82 to output the second USB voltage;
the start-up circuit 18 is further configured to stop forwarding the first configuration channel interaction signal and/or the first configuration channel interaction signal in dependence of the supply voltage.
The powering up of the PD charging circuit is achieved by the start-up circuit 18. And after power-on, the start circuit 18 stops working, and the control circuit 12 only communicates with one device of the devices by the configuration channel interaction signals, so that crosstalk caused by the interaction signals of a plurality of configuration channels is prevented, and the stability of the PD charging circuit is enhanced.
Fig. 6 shows an exemplary circuit structure of a PD charging circuit provided in an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, and detailed descriptions are as follows:
the second switching circuit 15 includes a first analog switch U1, a first Transient Voltage Super (TVS) Z1, a second TVS tube Z2, a first capacitor C1, a first resistor R1, a second resistor R2, and a third resistor R3.
A first positive data input terminal HSD1+ of the first analog switch U1 and a first negative data input terminal HSD 1-of the first analog switch U1 are commonly connected to a first USB data signal input terminal of the second switching circuit 15, a second positive data input terminal HSD2+ of the first analog switch U1 and a second negative data input terminal HSD 2-of the first analog switch U1 are commonly connected to a second USB data signal input terminal of the second switching circuit 15, a positive data input output terminal D + of the first analog switch U1 and a negative data input output terminal D-of the first analog switch U1 are commonly connected to a first USB data signal output terminal of the second switching circuit 15 and a second USB data signal output terminal of the second switching circuit 15, a selection terminal SEL of the first analog switch U1 is connected to a first terminal of the first TVS tube Z1, a first terminal of the first capacitor C1 and a first terminal of the first resistor R1, the second terminal of the first resistor R1 and the first terminal of the second resistor R2 are commonly connected to the first control signal input terminal of the second switching circuit 15, the output enable terminal/OE of the first analog switch U1 is connected to the first terminal of the second TVS tube Z2 and the first terminal of the third resistor R3, and the second terminal of the first TVS tube Z1, the second terminal of the second TVS tube Z2, the second terminal of the first capacitor C1, the second terminal of the second resistor R2, and the second terminal of the third resistor R3 are commonly connected to the power ground.
The second switching circuit 15 is realized by an analog switch, so that the signal switching function in two USB data signal links is completed, the signal integrity and the system reliability are improved to the greatest extent, and the board distribution space is reduced.
The first switching circuit 13 includes a second analog switch U2, a third TVS transistor Z3, a fourth TVS transistor Z4, a second capacitor C2, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.
The first positive data input terminal HSD1+ of the second analog switch U2 and the first negative data input terminal HSD 1-of the second analog switch U2 are commonly connected to the first configuration channel interaction signal input/output terminal of the first switching circuit 13, the second positive data input terminal HSD2+ of the second analog switch U2 and the second negative data input terminal HSD 2-of the second analog switch U2 are commonly connected to the second configuration channel interaction signal input/output terminal of the first switching circuit 13, the positive data input/output terminal D + of the second analog switch U2 and the negative data input/output terminal D-of the second analog switch U2 are commonly connected to the first configuration channel interaction signal input/output terminal of the first switching circuit 13 and the second configuration channel interaction signal input/output terminal of the first switching circuit 13, the selection terminal SEL of the second analog switch U2 and the first terminal of the third TVS tube Z3, A first end of the second capacitor C2 and a first end of the fourth resistor R4 are connected, a second end of the fourth resistor R4 and a first end of the sixth resistor R6 are commonly connected to a first control signal input end of the first switching circuit 13, an output enable end/OE of the second analog switch U2 is connected to a first end of the fourth TVS tube Z4 and a first end of the fifth resistor R5, and a second end of the third TVS tube Z3, a second end of the fourth TVS tube Z4, a second end of the second capacitor C2, a second end of the fifth resistor R5 and a second end of the sixth resistor R6 are commonly connected to a power ground.
The first switching circuit 13 is realized by an analog switch, the signal switching function in the two configuration channel interaction signal links is completed, the signal integrity and the system reliability are improved to a greater extent, and the board distribution space is reduced.
The control circuit 12 includes a microprocessor U3.
The first PD configuration channel terminal PD _ CC1 of the microprocessor U3 and the second PD configuration channel terminal PD _ CC2 of the microprocessor are commonly connected to the first configuration channel interaction signal input/output terminal of the control circuit 12 and the second configuration channel interaction signal input/output terminal of the control circuit 12, the PERIPHERAL enable terminal PERIPHERAL _ EN0 of the microprocessor U3 is connected to the first control signal output terminal of the control circuit 12, the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3 are commonly connected to the port identification signal input terminal of the control circuit 12 and the second control signal output terminal of the control circuit 12, the second serial data terminal SDA4 of the microprocessor U3 and the second serial clock terminal SCL4 of the microprocessor U3 are commonly connected to the battery status signal input terminal of the control circuit 12, the positive USB data input terminal USB _ DP of the microprocessor U3 and the negative USB data input terminal USB _ DM of the microprocessor U3 are commonly connected to the first USB data signal input terminal USB data input terminal of the control circuit 12 And a second USB data signal input of control circuit 12.
The power management circuit 11 includes a voltage-reducing chip U4, a first inductor L1, a first fet M1, a second fet M2, a third fet M3, a fourth fet M4, a first regulator Z5, a second regulator Z6, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12.
The first power input terminal VAC1 of the buck chip U4 is connected to a first terminal of an eleventh resistor R11, the second power input terminal VAC2 of the buck chip U4 is connected to a first terminal of a twelfth resistor R12, a second terminal of the eleventh resistor R11 and a drain of the second fet M2 are commonly connected to a first USB voltage input terminal of the power management circuit 11, and a second terminal of the twelfth resistor R12 and a drain of the fourth fet M4 are commonly connected to a second USB voltage input terminal of the power management circuit 11.
The source of the second field-effect transistor M2 is connected to the first end of the eighth resistor R8, the first end of the seventh capacitor C7, the anode of the first regulator Z5, and the source of the first field-effect transistor M1, the gate of the second field-effect transistor M2 is connected to the second end of the eighth resistor R8, the second end of the seventh capacitor C7, the cathode of the first regulator Z5, the first end of the seventh resistor R7, and the gate of the first field-effect transistor M1, and the second end of the seventh resistor R7 is connected to the first power driving output terminal ACDRV1 of the buck chip U4.
A source electrode of the fourth field-effect transistor M4 is connected with a first end of a tenth resistor R10, a first end of an eighth capacitor C8, an anode of a second regulator Z6 and a source electrode of the third field-effect transistor M3, a gate electrode of the fourth field-effect transistor M4 is connected with a second end of a tenth resistor R10, a second end of an eighth capacitor C8, a cathode of the second regulator Z6, a first end of a ninth resistor R9 and a gate electrode of the third field-effect transistor M3, and a second end of the ninth resistor R9 is connected with a second power driving output terminal ACDRV2 of the buck chip U4.
The drain of the first fet M1 is connected to the drain of the third fet M3, the first terminal of the ninth capacitor C9, and the bus power source terminal VBUS of the buck chip U4.
The battery power output terminal BAT of the voltage-reducing chip U4 and the first end of the sixth capacitor C6 are commonly connected to the charging voltage output terminal of the power management circuit 11, the system power output terminal SYS of the voltage-reducing chip U4 and the first end of the fifth capacitor C5 are commonly connected to the power supply voltage output terminal of the power management circuit 11, and the serial data output terminal SDA of the voltage-reducing chip U4 and the serial clock output terminal SCL of the voltage-reducing chip U4 are commonly connected to the port identification signal output terminal of the power management circuit 11.
The first soft start terminal BTST1 of the buck chip U4 is connected to the first terminal of the third capacitor C3, and the second terminal of the third capacitor C3 is connected to the first channel first switch terminal SW1_1 of the buck chip U4, the first channel second switch terminal SW1_2 of the buck chip U4, the first channel third switch terminal SW1_3 of the buck chip U4, the first channel fourth switch terminal SW1_4 of the buck chip U4, the first channel fifth switch terminal SW1_5 of the buck chip U4, and the first terminal of the first inductor L1.
The second soft start terminal BTST2 of the buck chip U4 is connected to the first terminal of the fourth capacitor C4, and the second terminal of the fourth capacitor C4 is connected to the second channel first switch terminal SW2_1 of the buck chip U4, the second channel second switch terminal SW2_2 of the buck chip U4, the second channel third switch terminal SW2_3 of the buck chip U4, the second channel fourth switch terminal SW2_4 of the buck chip U4, the second channel fifth switch terminal SW2_5 of the buck chip U4, and the second terminal of the first inductor L1.
The second terminal of the fifth capacitor C5, the second terminal of the sixth capacitor C6 and the second terminal of the ninth capacitor C9 are connected to the power ground.
The first USB voltage and/or the second USB voltage is converted into a supply voltage and a charging voltage by the buck chip U2, and the USB voltage is recognized to output a port recognition signal.
The voltage reduction chip U2 identifies a first USB voltage and/or a second USB voltage through a first power input end VAC1 and a first power input end VAC1, and after identification, outputs a third control signal through a first power driving output end ACDRV1 so as to enable the first field effect transistor M1 and the second field effect transistor M2 to be conducted and forward the first USB voltage to a bus power supply end VBUS of the voltage reduction chip U4; or the fourth control signal is output through the second power driving output terminal ACDRV2, so that the third fet M3 and the fourth fet M4 are turned on and forward the second USB voltage to the bus power source terminal VBUS of the buck chip U4. The buck chip U4 converts the first USB voltage or the second USB voltage into a supply voltage and a charging voltage.
The description of fig. 6 is further described below in conjunction with the working principle:
by way of example and not limitation, PD charging circuit operation can be classified into the following 3 cases:
in the first case, the PD charging circuit is connected to the first device 81, and the PD charging circuit is not connected to the second device 82.
When the first power input terminal VAC1 of the buck chip U1 receives the first USB voltage output by the first device 81, the first power input terminal VAC1 identifies a signal and a power supply voltage according to the first USB voltage output port; the power supply voltage is used for supplying power to each functional circuit; wherein, the port identification signal is outputted from the serial data output terminal SDA of the buck chip U4 and the serial clock output terminal SCL of the buck chip U4 to the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3; the supply voltage is output from the system power supply output terminal SYS of the buck chip U4. The microprocessor U3 outputs a first control signal of a first level from the PERIPHERAL enable terminal period _ EN0 of the microprocessor U3 to the select terminal SEL of the first analog switch U1 and the select terminal SEL of the second analog switch U2 according to the port identification signal. The first analog switch U1 forwards the first configuration channel interaction signal according to the control signal of the first level to make the first device 81 maintain outputting the first USB voltage; the energy storage device 14 outputs a battery status signal to the second serial data terminal SDA4 of the microprocessor U3 and the second serial clock terminal SCL4 of the microprocessor U3. The microprocessor U3 outputs a second control signal from the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3 to the serial data output terminal SDA of the buck chip U4 and the serial clock output terminal SCL of the buck chip U4 according to the battery status signal; the voltage reduction chip U4 converts the first USB voltage into a supply voltage and a charging voltage according to the second control signal, and the charging voltage is used for charging the energy storage component 14. The second analog switch U2 forwards the first USB data signal output by the first device 81 according to the control signal of the first level, and the positive USB data input terminal USB _ DP of the microprocessor U3 and the negative USB data input terminal USB _ DM of the microprocessor U3 receive the first USB data signal.
In the second case, the PD charging circuit is not connected to the first device 81 and the PD charging circuit is connected to the second device 82.
When the second power input terminal VAC2 of the buck chip U1 receives the second USB voltage output by the second device 82, the signal and the power supply voltage are identified according to the second USB voltage output port; the power supply voltage is used for supplying power to each functional circuit; wherein, the port identification signal is outputted from the serial data output terminal SDA of the buck chip U4 and the serial clock output terminal SCL of the buck chip U4 to the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3; the supply voltage is output from the system power supply output terminal SYS of the buck chip U4. The microprocessor U3 outputs the first control signal of the second level from the PERIPHERAL enable terminal period _ EN0 of the microprocessor U3 to the select terminal SEL of the first analog switch U1 and the select terminal SEL of the second analog switch U2 according to the port identification signal. The first analog switch U1 forwards the second configuration channel interaction signal according to the control signal of the second level to make the second device 82 maintain outputting the second USB voltage; the energy storage device 14 outputs a battery status signal to the second serial data terminal SDA4 of the microprocessor U3 and the second serial clock terminal SCL4 of the microprocessor U3. The microprocessor U3 outputs a second control signal from the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3 to the serial data output terminal SDA of the buck chip U4 and the serial clock output terminal SCL of the buck chip U4 according to the battery status signal; the voltage reduction chip U4 converts the second USB voltage into a supply voltage and a charging voltage according to the second control signal, and the charging voltage is used for charging the energy storage component 14. The second analog switch U2 forwards the second USB data signal output by the second device 82 according to the control signal of the second level, and the positive USB data input terminal USB _ DP of the microprocessor U3 and the negative USB data input terminal USB _ DM of the microprocessor U3 receive the second USB data signal.
In the third case, the PD charging circuit is connected to the first device 81 and the PD charging circuit is connected to the second device 82.
When the first power input terminal VAC2 of the buck chip U1 receives the first USB voltage output by the first device 81 and the second power input terminal VAC2 of the buck chip U1 receives the second USB voltage output by the second device 82, the output port identification signal and the supply voltage are output according to the first USB voltage and the second USB voltage; the power supply voltage is used for supplying power to each functional circuit; wherein, the port identification signal is outputted from the serial data output terminal SDA of the buck chip U4 and the serial clock output terminal SCL of the buck chip U4 to the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3; the supply voltage is output from the system power supply output terminal SYS of the buck chip U4. The microprocessor U3 outputs a first control signal of a first level from the PERIPHERAL enable terminal period _ EN0 of the microprocessor U3 to the select terminal SEL of the first analog switch U1 and the select terminal SEL of the second analog switch U2 according to the port identification signal. The first analog switch U1 forwards the first configuration channel interaction signal according to the control signal of the first level to make the first device 81 maintain outputting the first USB voltage; the energy storage device 14 outputs a battery status signal to the second serial data terminal SDA4 of the microprocessor U3 and the second serial clock terminal SCL4 of the microprocessor U3. The microprocessor U3 outputs a second control signal from the first serial data terminal SDA6 of the microprocessor U3 and the first serial clock terminal SCL6 of the microprocessor U3 to the serial data output terminal SDA of the buck chip U4 and the serial clock output terminal SCL of the buck chip U4 according to the battery status signal; the voltage reduction chip U4 converts the first USB voltage into a supply voltage and a charging voltage according to the second control signal, and the charging voltage is used for charging the energy storage component 14. The second analog switch U2 forwards the first USB data signal output by the first device 81 according to the control signal of the first level, and the positive USB data input terminal USB _ DP of the microprocessor U3 and the negative USB data input terminal USB _ DM of the microprocessor U3 receive the first USB data signal.
The embodiment of the invention also provides the POS machine which comprises the PD charging circuit.
According to the embodiment of the invention, a power management circuit identifies a signal and a power supply voltage according to a first USB voltage output by first equipment and/or a second USB voltage output by second equipment; the power supply voltage is used for supplying power to each functional circuit; the control circuit outputs a first control signal according to the port identification signal; the first switching circuit forwards a first configuration channel interaction signal according to the control signal of the first level so as to enable the first equipment to keep outputting a first USB voltage, or forwards a second configuration channel interaction signal according to the control signal of the second level so as to enable the second equipment to keep outputting a second USB voltage; the first configuration channel interaction signal is a half-duplex communication signal between the control circuit and the first equipment; the second configuration channel interaction signal is a half-duplex communication signal between the control circuit and the second device; the energy storage assembly outputs a battery state signal; the control circuit outputs a second control signal according to the battery state signal; the power supply management circuit converts the first USB voltage or the second USB voltage into a power supply voltage and a charging voltage according to the second control signal, and the charging voltage is used for charging the energy storage assembly; the first switching circuit forwards the first configuration channel interaction signal or the second configuration channel interaction signal according to the control signal so as to enable the first equipment to maintain to output the first USB voltage or enable the second equipment to maintain to output the second USB voltage, and therefore power supply of multiple paths of USB voltages is achieved; the control circuit outputs a second control signal according to the battery state signal output by the energy storage assembly so that the power management circuit converts the first USB voltage or the second USB voltage into a charging voltage; the charging voltage is output according to the battery state, and the charging requirements of batteries with different numbers are met; therefore, the charging requirement under the conditions of multi-path USB voltage power supply and different battery charging sections is met.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A PD charging circuit, comprising:
the power management circuit is connected with the first device and/or the second device and is configured to output a port identification signal and a supply voltage according to the first USB voltage and/or the second USB voltage when receiving the first USB voltage output by the first device and/or the second USB voltage output by the second device; the power supply voltage is used for supplying power to each functional circuit;
the control circuit is connected with the power management circuit and is configured to output a first control signal according to the port identification signal;
the first switching circuit is used for being connected with the first device and/or the second device, and is also connected with the control circuit, and is configured to forward a first configuration channel interaction signal according to a first level of the control signal so as to enable the first device to keep outputting the first USB voltage, or forward a second configuration channel interaction signal according to a second level of the control signal so as to enable the second device to keep outputting the second USB voltage; wherein the first configuration channel interaction signal is a half-duplex communication signal between the control circuit and the first device; the second configuration channel interaction signal is a half-duplex communication signal between the control circuit and the second device;
the energy storage assembly is connected with the control circuit and configured to output a battery state signal;
the control circuit is further configured to output a second control signal according to the battery status signal;
the power management circuit is further configured to convert the first USB voltage or the second USB voltage into the supply voltage and a charging voltage according to the second control signal, where the charging voltage is used to charge the energy storage component.
2. The PD charging circuit of claim 1, further comprising:
the second switching circuit is connected with the first device and/or the second device, is also connected with the control circuit, and is configured to forward a first USB data signal output by the first device according to the control signal of a first level or forward a second USB data signal output by the second device according to the control signal of a second level;
the control circuit is further configured to receive the first USB data signal or the second USB data signal.
3. The PD charging circuit of claim 2, wherein the second switching circuit comprises a first analog switch, a first TVS transistor, a second TVS transistor, a first capacitor, a first resistor, a second resistor, and a third resistor;
the first positive data input end of the first analog switch and the first negative data input end of the first analog switch are connected to the first USB data signal input end of the second switching circuit, the second positive data input end of the first analog switch and the second negative data input end of the first analog switch are connected to the second USB data signal input end of the second switching circuit, the positive data input output end of the first analog switch and the negative data input output end of the first analog switch are connected to the first USB data signal output end of the second switching circuit and the second USB data signal output end of the second switching circuit, the selection end of the first analog switch is connected to the first end of the first TVS tube, the first end of the first capacitor and the first end of the first resistor, the second end of the first resistor and the first end of the second resistor are connected to the second switching circuit The output enable end of the first analog switch is connected with the first end of the second TVS tube and the first end of the third resistor, and the second end of the first TVS tube, the second end of the second TVS tube, the second end of the first capacitor, the second end of the second resistor and the second end of the third resistor are connected to a power ground in common.
4. The PD charging circuit of claim 2, further comprising:
a first USB interface, connected to the first device, the power management circuit, the first switching circuit, and the second switching circuit, and configured to forward the first USB data signal, the first configuration channel interaction signal, and the first USB voltage.
5. The PD charging circuit of claim 2, further comprising:
a second USB interface, connected to the second device, the power management circuit, the first switching circuit, and the second switching circuit, and configured to forward the second USB data signal, the second configuration channel interaction signal, and the second USB voltage.
6. The PD charging circuit of any of claims 1 to 5, wherein the first switching circuit includes a second analog switch, a third TVS transistor, a fourth TVS transistor, a second capacitor, a fourth resistor, a fifth resistor, and a sixth resistor;
a first positive data input terminal of the second analog switch and a first negative data input terminal of the second analog switch are commonly connected to a first configuration channel interaction signal input/output terminal of the first switching circuit, a second positive data input terminal of the second analog switch and a second negative data input terminal of the second analog switch are commonly connected to a second configuration channel interaction signal input/output terminal of the first switching circuit, a positive data input/output terminal of the second analog switch and a negative data input/output terminal of the second analog switch are commonly connected to a first configuration channel interaction signal input/output terminal of the first switching circuit and a second configuration channel interaction signal input/output terminal of the first switching circuit, a selection terminal of the second analog switch U2 is connected to a first terminal of the third TVS tube, a first terminal of the second capacitor and a first terminal of the fourth resistor, the second end of the fourth resistor and the first end of the sixth resistor are connected to the first control signal input end of the first switching circuit, the output enable end of the second analog switch is connected with the first end of the fourth TVS tube and the first end of the fifth resistor, and the second end of the third TVS tube, the second end of the fourth TVS tube, the second end of the second capacitor, the second end of the fifth resistor and the second end of the sixth resistor are connected to a power ground in common.
7. The PD charging circuit of any of claims 1 to 5, wherein the control circuit includes a microprocessor;
a first PD configuration channel end of the microprocessor and a second PD configuration channel end of the microprocessor are commonly connected to a first configuration channel interaction signal input-output end of the control circuit and a second configuration channel interaction signal input-output end of the control circuit, a peripheral enable end of the microprocessor is connected to a first control signal output end of the control circuit, a first serial data end of the microprocessor and a first serial clock end of the microprocessor are commonly connected to a port identification signal input end of the control circuit and a second control signal output end of the control circuit, a second serial data end of the microprocessor and a second serial clock end of the microprocessor are commonly connected to a battery state signal input end of the control circuit, a positive USB data input end of the microprocessor and a negative USB data input end of the microprocessor are commonly connected to a first USB data signal input end of the control circuit and a negative USB data input end of the microprocessor And the second USB data signal input end of the control circuit.
8. The PD charging circuit according to any of claims 1 to 5, wherein the power management circuit includes a buck chip, a first inductor, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a first voltage regulator, a second voltage regulator, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor;
a first power input end of the voltage reduction chip is connected with a first end of the eleventh resistor, a second power input end of the voltage reduction chip is connected with a first end of the twelfth resistor, a second end of the eleventh resistor and a drain electrode of the second field-effect transistor are commonly connected to a first USB voltage input end of the power management circuit, and a second end of the twelfth resistor and a drain electrode of the fourth field-effect transistor are commonly connected to a second USB voltage input end of the power management circuit;
a source electrode of the second field effect transistor is connected with a first end of the eighth resistor, a first end of the seventh capacitor, an anode of the first voltage regulator tube and a source electrode of the first field effect transistor, a grid electrode of the second field effect transistor is connected with a second end of the eighth resistor, a second end of the seventh capacitor, a cathode of the first voltage regulator tube, a first end of the seventh resistor and a grid electrode of the first field effect transistor, and a second end of the seventh resistor is connected with a first power supply driving output end of the voltage reduction chip;
a source electrode of the fourth field effect transistor is connected with a first end of the tenth resistor, a first end of the eighth capacitor, a positive electrode of the second voltage regulator tube and a source electrode of the third field effect transistor, a grid electrode of the fourth field effect transistor is connected with a second end of the tenth resistor, a second end of the eighth capacitor, a negative electrode of the second voltage regulator tube, a first end of the ninth resistor and a grid electrode of the third field effect transistor, and a second end of the ninth resistor is connected with a second power supply driving output end of the voltage reduction chip;
the drain electrode of the first field effect transistor is connected with the drain electrode of the third field effect transistor, the first end of the ninth capacitor and a bus power supply end of the voltage reduction chip;
the battery power supply output end of the voltage reduction chip and the first end of the sixth capacitor are connected to the charging voltage output end of the power management circuit together, the system power supply output end of the voltage reduction chip and the first end of the fifth capacitor are connected to the power supply voltage output end of the power management circuit together, and the serial data output end of the voltage reduction chip and the serial clock output end of the voltage reduction chip are connected to the port identification signal output end of the power management circuit together;
the first soft start end of the voltage reduction chip is connected with the first end of the third capacitor, and the second end of the third capacitor is connected with the first channel first switch end of the voltage reduction chip, the first channel second switch end of the voltage reduction chip, the first channel third switch end of the voltage reduction chip, the first channel fourth switch end of the voltage reduction chip, the first channel fifth switch end of the voltage reduction chip and the first end of the first inductor;
the second soft start end of the voltage reduction chip is connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is connected with the second channel first switch end of the voltage reduction chip, the second channel second switch end of the voltage reduction chip, the second channel third switch end of the voltage reduction chip, the second channel fourth switch end of the voltage reduction chip, the second channel fifth switch end of the voltage reduction chip and the second end of the first inductor;
the second end of the fifth capacitor, the second end of the sixth capacitor and the second end of the ninth capacitor are connected to a power ground in common.
9. The PD charging circuit of any of claims 1 to 5, further comprising:
the starting circuit is used for being connected with first equipment and/or second equipment, is also connected with the control circuit, the first switching circuit and the power management circuit, and is configured to forward the first configuration channel interaction signal to enable the first equipment to output a first USB voltage when power supply voltage is not received; and/or when the power supply voltage is not received, forwarding the second configuration channel interaction signal to enable the second equipment to output a second USB voltage;
the start-up circuit is further configured to stop forwarding the first configuration channel interaction signal and/or the first configuration channel interaction signal according to the supply voltage.
10. A POS machine, comprising the PD charging circuit of any one of claims 1 to 9.
CN202110728097.8A 2021-06-29 2021-06-29 PD charging circuit and POS machine Pending CN113422411A (en)

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