CN113421952A - Micro LED chip and preparation method thereof - Google Patents
Micro LED chip and preparation method thereof Download PDFInfo
- Publication number
- CN113421952A CN113421952A CN202110699384.0A CN202110699384A CN113421952A CN 113421952 A CN113421952 A CN 113421952A CN 202110699384 A CN202110699384 A CN 202110699384A CN 113421952 A CN113421952 A CN 113421952A
- Authority
- CN
- China
- Prior art keywords
- gallium nitride
- nitride layer
- type gallium
- layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 128
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 122
- 238000005530 etching Methods 0.000 claims abstract description 59
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000012670 alkaline solution Substances 0.000 claims abstract description 17
- 238000005516 engineering process Methods 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 157
- 238000000034 method Methods 0.000 claims description 32
- 239000011241 protective layer Substances 0.000 claims description 17
- 239000000243 solution Substances 0.000 claims description 15
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000003513 alkali Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 229910015844 BCl3 Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000005303 weighing Methods 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 13
- 230000002411 adverse Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 9
- 239000007789 gas Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 238000010849 ion bombardment Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
- Weting (AREA)
Abstract
The embodiment of the invention discloses a Micro LED chip and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; sequentially forming an n-type gallium nitride layer, a quantum well active layer and a p-type gallium nitride layer on one side of a substrate; removing the p-type gallium nitride layer and the quantum well active layer in the n electrode region by utilizing an Inductively Coupled Plasma (ICP) etching technology, and exposing the n-type gallium nitride layer in the n electrode region; corroding the n-type gallium nitride layer in part of the n-electrode area by using an alkaline solution; and forming a p electrode and an n electrode on the sides of the p-type gallium nitride layer and the n-type gallium nitride layer far away from the substrate respectively. The technical scheme of the embodiment of the invention can effectively reduce the roughness of the n-type gallium nitride layer after ICP etching, improve the contact between the evaporated metal of the n electrode and the n surface, reduce the working voltage of the device, remove the damaged layer after ICP etching and reduce the adverse effect of ICP etching on the performance of the device.
Description
Technical Field
The embodiment of the invention relates to the technology of semiconductor light-emitting devices, in particular to a Micro LED chip and a preparation method thereof.
Background
In the application of LED chips, the common LED chips are mainly applied to the backlight module of the lighting and display device, and the currently rapidly developed Mini LED mainly applies to indoor and outdoor display screens. However, the prior art cannot meet the requirements of many applications with higher requirements on size and resolution, so the Micro LED technology is a brand new display technology, and the application concepts thereof are completely different from the former two, so that the Micro LED technology can be applied to the fields of wearable watches, mobile phones, vehicle display devices, VR/AR, televisions and the like, and is considered as an ultimate display technology.
The structure of the LED epitaxial wafer generally consists of a p-type gallium nitride (p-GaN) layer, a Multiple Quantum Well (MQW) active layer, an n-type gallium nitride (n-GaN) layer, and a substrate. The metal of the n electrode of the Micro LED is evaporated on the n-GaN layer and mainly used for providing electrons, and the electrons and holes provided by the p-GaN layer are compounded in the active layer under the action of voltage to generate photons so as to emit light.
The mesa on which the n-electrode metal is evaporated is usually etched from the p-GaN layer, MQW of the epitaxial wafer to the n-GaN layer by an inductively coupled plasma ICP etching technique. The ICP acts on the gas as Cl2And BCl3Various ions are generated through glow discharge, positive ions bombard the surface of the GaN material under the action of an electric field to form physical sputtering, and active ions are adsorbed on the surface of the GaN material and perform chemical reaction. Under the combined action of physical bombardment and chemical reaction, the mesa used for the metal evaporation of the n electrode is etched, and the appearance of the n surface is also under the combined action of the two. The ion bombardment has certain energy, so that the n surface is rough in appearance, and the rough surface can cause poor contact between metal evaporated on the n surface and n-GaN, so that the working voltage of the device is increased. Because the ICP etching process simultaneously has a chemical etching process and a physical sputtering process caused by high-energy ion bombardment, the crystal quality of the GaN material is easily damaged, and particularly, the damage is more easily caused when deep etching is carried out on the GaN epitaxial layer. In addition, the defects of dislocation, film crack and the like in the epitaxial growth process of the LED are subjected to heat, stress, ion bombardment and the like in the ICP etching processNew cracks and pits can be generated under the action of factors, so that the internal quantum efficiency of the LED chip is reduced, the aging of devices is accelerated, the service life of the LED is shortened, and even the failure of the LED chip is directly caused in severe cases.
Disclosure of Invention
The embodiment of the invention provides a Micro LED chip and a preparation method thereof, which can effectively reduce the roughness of the n-type gallium nitride layer after ICP etching, improve the contact between the evaporated metal of an n electrode and an n surface, reduce the working voltage of a device, remove a damaged layer after ICP etching and reduce the adverse effect of ICP etching on the performance of the device.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a Micro LED chip, including:
providing a substrate;
sequentially forming an n-type gallium nitride layer, a quantum well active layer and a p-type gallium nitride layer on one side of the substrate;
removing the p-type gallium nitride layer and the quantum well active layer in the n electrode region by utilizing an Inductively Coupled Plasma (ICP) etching technology, and exposing the n-type gallium nitride layer in the n electrode region;
corroding the n-type gallium nitride layer in part of the n-electrode area by using an alkaline solution;
and forming a p electrode and an n electrode on one sides of the p-type gallium nitride layer and the n-type gallium nitride layer far away from the substrate respectively.
Optionally, the removing the p-type gallium nitride layer and the quantum well active layer in the n electrode region by using an Inductively Coupled Plasma (ICP) etching technique, where the n-type gallium nitride layer exposing the n electrode region includes:
forming a protective layer on one side of the p-type gallium nitride layer far away from the substrate;
removing the protective layer in the n electrode area by using a dry etching or wet etching photoetching process;
placing the sample in ICP etching equipment by using Cl2And BCl3And etching the p-type gallium nitride layer and the quantum well active layer in the n electrode region by using the mixed gas, and exposing the n-type gallium nitride layer in the n electrode region.
Optionally, the protective layer includes a silicon dioxide layer with a thickness of 200nm to 300 nm.
Optionally, before etching the n-type gallium nitride layer in a part of the n-electrode region with an alkaline solution, the method further includes:
and removing the protective layer in the region except the n electrode region.
Optionally, the etching, with an alkaline solution, the n-type gallium nitride layer in a part of the n-electrode region includes:
weighing 1mol/L alkali solution and a reaction vessel;
placing the sample subjected to ICP etching into the reaction vessel;
and (3) putting the reaction vessel into a water bath kettle at the temperature of 80 ℃ for 15min, taking out and cleaning.
Optionally, the alkali solution comprises KOH solution or TMAH (tetramethylammonium hydroxide) solution.
Optionally, before forming an n-type gallium nitride layer, a quantum well active layer, and a p-type gallium nitride layer in sequence on one side of the substrate, the method further includes:
and sequentially forming a buffer layer and a non-doped gallium nitride layer on one side of the substrate.
Optionally, the n-type gallium nitride layer is located on a side of the undoped gallium nitride layer away from the substrate.
Optionally, the thickness of the n-type gallium nitride layer is 1500nm to 3000nm, the thickness of the quantum well active layer is 250nm to 400nm, and the thickness of the p-type gallium nitride layer is 100nm to 300 nm.
In a second aspect, an embodiment of the present invention further provides a Micro LED chip, and the Micro LED chip is prepared by any one of the above preparation methods.
The embodiment of the invention provides a preparation method of a Micro LED chip, which comprises the following steps: providing a substrate; sequentially forming an n-type gallium nitride layer, a quantum well active layer and a p-type gallium nitride layer on one side of a substrate; removing the p-type gallium nitride layer and the quantum well active layer in the n electrode region by utilizing an Inductively Coupled Plasma (ICP) etching technology, and exposing the n-type gallium nitride layer in the n electrode region; corroding the n-type gallium nitride layer in part of the n-electrode area by using an alkaline solution; and forming a p electrode and an n electrode on the sides of the p-type gallium nitride layer and the n-type gallium nitride layer far away from the substrate respectively. The n-type gallium nitride layer etched by the ICP is corroded by the alkaline solution, so that the appearance after the ICP is etched can be effectively optimized, the roughness of the appearance of the n-type gallium nitride layer after the ICP is etched is effectively reduced, the contact between metal evaporated on the n electrode and the n surface is improved, the working voltage of a device is reduced, the damage layer after the ICP is etched can be removed, and the adverse effect of the ICP etching on the performance of the device is reduced.
Drawings
FIG. 1 is a schematic flow chart of a method for manufacturing a Micro LED chip according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram after step S120 according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram after step S130 according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a specific step of step S130 according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram corresponding to steps S131-S133 in the embodiment of the present invention;
fig. 6 is a schematic microscopic view of the surface topography of n-type gallium nitride after S140 according to an embodiment of the present invention;
fig. 7 is a flowchart illustrating a specific step of step S140 according to an embodiment of the present invention;
FIG. 8 is a schematic flow chart illustrating another method for fabricating a Micro LED chip according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram after step S220 according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram of a Micro LED chip according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of another Micro LED chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. It should be noted that the terms "upper", "lower", "left", "right", and the like used in the description of the embodiments of the present invention are used in the angle shown in the drawings, and should not be construed as limiting the embodiments of the present invention. In addition, in this context, it is also to be understood that when an element is referred to as being "on" or "under" another element, it can be directly formed on "or" under "the other element or be indirectly formed on" or "under" the other element through an intermediate element. The terms "first," "second," and the like, are used for descriptive purposes only and not for purposes of limitation, and do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Fig. 1 is a schematic flow chart of a preparation method of a Micro LED chip according to an embodiment of the present invention, and referring to fig. 1, the preparation method includes:
step S110, providing a substrate.
The substrate is an insulating substrate, and monocrystalline silicon, sapphire, silicon carbide, gallium nitride and the like can be adopted. The specific implementation can be selected according to actual needs, and the embodiment of the invention does not limit the specific implementation.
And step S120, forming an n-type gallium nitride layer, a quantum well active layer and a p-type gallium nitride layer on one side of the substrate in sequence.
In this embodiment, optionally, the thickness of the n-type gallium nitride layer 20 is 1500nm to 3000nm, the thickness of the quantum well active layer 30 is 250nm to 400nm, and the thickness of the p-type gallium nitride layer 40 is 100nm to 300 nm.
And S130, removing the p-type gallium nitride layer and the quantum well active layer in the n electrode region by utilizing an Inductively Coupled Plasma (ICP) etching technology, and exposing the n-type gallium nitride layer in the n electrode region.
The ICP is a common technology in the micro-nano processing process of the semiconductor chip, and micro-scale and nano-scale micro-patterns can be processed. The basic principle is to process and form a mask with a specific pattern on the surface of a semiconductor material, and then control etching gas by using an inductively coupled plasma etching machine (ICP-RIE) to etch away the part without the mask, so as to finally leave the specific pattern. During the etching of semiconductor materials by etching gases, there are two types of etching: physical etching and chemical etching. For different materials and micro patterns with different sizes, the two types of etching have different strengths, equipment parameters are required to be adjusted to achieve a balanced state, and finally, the ideal and required vertical etching result is obtained.
For example, fig. 3 is a schematic structural diagram after step S130 in the implementation of the present invention, and referring to fig. 3, in this embodiment, the p-type gallium nitride layer, the quantum well active layer, and a part of the n-type gallium nitride layer at the position of the n electrode region are removed by an ICP etching process, where the thickness of the n-type gallium nitride layer 20 to be removed is not limited, and may be selected according to actual situations in the specific implementation. Fig. 4 is a schematic flow chart of a specific step of step S130 according to an embodiment of the present invention, and referring to fig. 4, optionally, the p-type gallium nitride layer and the quantum well active layer in the n electrode region are removed by using an ICP etching technique using inductively coupled plasma, where the n-type gallium nitride layer exposing the n electrode region includes:
and S131, forming a protective layer on the side, away from the substrate, of the p-type gallium nitride layer.
And S132, removing the protective layer of the n electrode area by using a dry etching or wet etching process.
Step S133, placing the sample in ICP etching equipment by adopting Cl2And BCl3Etching the p-type gallium nitride layer and the quantum well active layer of the n-electrode region by the mixed gas to expose the n-type gallium nitride of the n-electrode regionAnd (3) a layer.
Exemplarily, fig. 5 is a schematic structural diagram corresponding to steps S131 to S133 in the embodiment of the present invention, wherein in S131, a protective layer 50 is formed on a side of the p-type gallium nitride layer 40 away from the substrate 10, where the protective layer 50 may be silicon dioxide, and in this embodiment, optionally, the protective layer 50 includes a silicon dioxide layer with a thickness of 200nm to 300 nm. In S132, the protective layer in the n electrode region is removed by using a dry etching or wet etching process, so as to expose the n electrode region to be etched by ICP. In S133, the p-type gallium nitride layer and the quantum well active layer in the n-electrode region are etched by using an ICP etching process to expose the n-type gallium nitride layer in the n-electrode region, and in specific implementation, the n-type gallium nitride layer may also be partially removed, and in specific implementation, the n-type gallium nitride layer may be flexibly selected according to actual conditions.
And step S140, corroding the n-type gallium nitride layer of part of the n-electrode region by using an alkaline solution.
The n-type gallium nitride layer etched by ICP has a relatively rough surface morphology, and the crystal quality of a part of the gallium nitride material may be damaged, so in this embodiment, the n-type gallium nitride layer in the n electrode region is etched by using an alkaline solution to optimize the surface morphology of the n-type gallium nitride. For example, fig. 6 is a microscopic schematic view of the surface topography of n-type gallium nitride after S140 according to the embodiment of the present invention, and the surface topography after the alkaline solution corrosion is effectively optimized, so as to improve the device performance.
Optionally, before etching the n-type gallium nitride layer in part of the n-electrode region with an alkaline solution, the method further includes:
and removing the protective layer of the region except the n electrode region.
The method for removing the protective layer may be: in BOE (HF: NH)4F is 6:1) solution is soaked for 5mins to remove the silicon dioxide protective layer, and deionized water is used for ultrasonic cleaning for 10 mins.
Fig. 7 is a schematic flowchart of a specific step of step S140 according to an embodiment of the present invention, and referring to fig. 7, optionally, the etching the n-type gallium nitride layer in a part of the n-electrode region with an alkaline solution includes:
step S141, 1mol/L of alkali solution is weighed and added into a reaction vessel.
S142, placing the sample subjected to ICP etching into a reaction vessel;
and step S143, putting the reaction vessel into a water bath kettle at 80 ℃ for 15min, taking out and cleaning.
After the end, the sample is soaked for 5mins by dilute HCl solution, washed for 10mins by acetone and isopropanol respectively, and washed for 10mins by deionized water. Optionally, the alkali solution includes a KOH solution or a TMAH (tetramethylammonium hydroxide) solution, and may be selected according to actual requirements in specific implementation.
And S150, forming a p electrode and an n electrode on the sides of the p-type gallium nitride layer and the n-type gallium nitride layer far away from the substrate respectively.
The p-electrode and the n-electrode may be formed by depositing metal on the surface of the p-type gallium nitride layer and the surface of the n-type gallium nitride layer by using a vapor deposition process, and the specific materials of the p-electrode and the n-electrode may be selected according to actual situations, which is not limited in this embodiment.
According to the technical scheme, the n-type gallium nitride layer after ICP etching is corroded by the alkaline solution, the appearance after ICP etching can be effectively optimized, the roughness of the appearance of the n-type gallium nitride layer after ICP etching is effectively reduced, the contact between metal and an n surface of an n electrode evaporation metal is improved, the working voltage of a device is reduced, meanwhile, a damage layer after ICP etching can be removed, and the adverse effect of ICP etching on the performance of the device is reduced.
On the basis of the above technical solution, fig. 8 is a schematic flow chart of another method for manufacturing a Micro LED chip according to an embodiment of the present invention, and referring to fig. 8, the method includes:
step S210, providing a substrate.
Step S220, a buffer layer and a non-doped gallium nitride layer are sequentially formed on one side of the substrate.
When the n-type gallium nitride layer is directly formed on the substrate, defects may be caused due to different materials and the like, so that the buffer layer and the undoped gallium nitride layer can be formed on the substrate firstly. Exemplarily, fig. 9 is a schematic structural diagram after step S220 in the embodiment of the present invention, and referring to fig. 9, the structure includes a substrate 10, and a buffer layer 60 and an undoped gallium nitride layer 70 located on one side of the substrate 10. Optionally, the n-type gallium nitride layer is located on one side of the undoped gallium nitride layer away from the substrate, so as to avoid defects formed during growth of the n-type gallium nitride layer.
And step S230, forming an n-type gallium nitride layer, a quantum well active layer and a p-type gallium nitride layer on one side of the substrate in sequence.
And S240, removing the p-type gallium nitride layer and the quantum well active layer in the n electrode region by utilizing an Inductively Coupled Plasma (ICP) etching technology, and exposing the n-type gallium nitride layer in the n electrode region.
And step S250, corroding the n-type gallium nitride layer of part of the n-electrode region by using an alkaline solution.
And step S260, forming a p electrode and an n electrode on the sides of the p-type gallium nitride layer and the n-type gallium nitride layer far away from the substrate respectively.
According to the technical scheme, the n-type gallium nitride layer after ICP etching is corroded by the alkaline solution, the appearance after ICP etching can be effectively optimized, the roughness of the appearance of the n-type gallium nitride layer after ICP etching is effectively reduced, the contact between metal and an n surface of an n electrode evaporation metal is improved, the working voltage of a device is reduced, meanwhile, a damage layer after ICP etching can be removed, and the adverse effect of ICP etching on the performance of the device is reduced.
The embodiment of the invention also provides a Micro LED chip, and the Micro LED chip can be prepared by any one of the preparation methods provided by the embodiments. Exemplarily, fig. 10 is a schematic structural diagram of a Micro LED chip according to an embodiment of the present invention, and referring to fig. 10, the Micro LED chip includes a substrate 10, an n-type gallium nitride layer 20, an n electrode 80 located on a side of the n-type gallium nitride layer 20 away from the substrate 10, a quantum well active layer 30, a p-type gallium nitride layer 40, and a p electrode 90 located on a side of the p-type gallium nitride layer 40 away from the substrate; fig. 11 is a schematic structural diagram of another Micro LED chip according to an embodiment of the present invention, and referring to fig. 11, the Micro LED chip includes a substrate 10, a buffer layer 60, an undoped gallium nitride layer 70, an n-type gallium nitride layer 20, an n-electrode 80 located on a side of the n-type gallium nitride layer 20 away from the substrate 10, a quantum well active layer 30, a p-type gallium nitride layer 40, and a p-electrode 90 located on a side of the p-type gallium nitride layer 40 away from the substrate.
According to the technical scheme, the n-type gallium nitride layer after ICP etching is optimized in morphology, roughness of the n-type gallium nitride layer after ICP etching is effectively reduced, the contact between metal and an n surface of an n electrode evaporation metal is improved, the working voltage of a device is reduced, a damage layer after ICP etching can be removed, adverse effects of ICP etching on device performance are reduced, and therefore the performance of a Micro LED chip is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A preparation method of a Micro LED chip is characterized by comprising the following steps:
providing a substrate;
sequentially forming an n-type gallium nitride layer, a quantum well active layer and a p-type gallium nitride layer on one side of the substrate;
removing the p-type gallium nitride layer and the quantum well active layer in the n electrode region by utilizing an Inductively Coupled Plasma (ICP) etching technology, and exposing the n-type gallium nitride layer in the n electrode region;
corroding the n-type gallium nitride layer in part of the n-electrode area by using an alkaline solution;
and forming a p electrode and an n electrode on one sides of the p-type gallium nitride layer and the n-type gallium nitride layer far away from the substrate respectively.
2. The method for preparing a Micro LED chip according to claim 1, wherein the removing the p-type gallium nitride layer and the quantum well active layer in the n-electrode region by using an Inductively Coupled Plasma (ICP) etching technique, the exposing the n-type gallium nitride layer in the n-electrode region comprising:
forming a protective layer on one side of the p-type gallium nitride layer far away from the substrate;
removing the protective layer in the n electrode area by using a dry etching or wet etching process;
placing the sample in ICP etching equipment by using Cl2And BCl3And etching the p-type gallium nitride layer and the quantum well active layer in the n electrode region by using the mixed gas, and exposing the n-type gallium nitride layer in the n electrode region.
3. A method of fabricating a Micro LED chip according to claim 2, wherein the protective layer comprises a 200nm to 300nm thick layer of silicon dioxide.
4. The method for fabricating a Micro LED chip according to claim 2, wherein before etching the n-type gallium nitride layer in a portion of the n-electrode region with an alkaline solution, further comprising:
and removing the protective layer in the region except the n electrode region.
5. The method of claim 1, wherein the etching the n-type gallium nitride layer of a portion of the n-electrode region with an alkaline solution comprises:
weighing 1mol/L alkali solution and a reaction vessel;
placing the sample subjected to ICP etching into the reaction vessel;
and (3) putting the reaction vessel into a water bath kettle at the temperature of 80 ℃ for 15min, taking out and cleaning.
6. A method of fabricating a Micro LED chip according to claim 5, wherein the alkali solution comprises KOH solution or TMAH (tetramethylammonium hydroxide) solution.
7. The method for preparing a Micro LED chip according to claim 1, wherein before forming the n-type gallium nitride layer, the quantum well active layer and the p-type gallium nitride layer in sequence on one side of the substrate, the method further comprises:
and sequentially forming a buffer layer and a non-doped gallium nitride layer on one side of the substrate.
8. The method of claim 7, wherein the n-type gallium nitride layer is on a side of the undoped gallium nitride layer away from the substrate.
9. A method for preparing a Micro LED chip according to any one of claims 1 to 8, wherein the n-type GaN layer has a thickness of 1500nm to 3000nm, the quantum well active layer has a thickness of 250nm to 400nm, and the p-type GaN layer has a thickness of 100nm to 300 nm.
10. A Micro LED chip, which is prepared by the preparation method of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110699384.0A CN113421952A (en) | 2021-06-23 | 2021-06-23 | Micro LED chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110699384.0A CN113421952A (en) | 2021-06-23 | 2021-06-23 | Micro LED chip and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113421952A true CN113421952A (en) | 2021-09-21 |
Family
ID=77716494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110699384.0A Pending CN113421952A (en) | 2021-06-23 | 2021-06-23 | Micro LED chip and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113421952A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847673A (en) * | 2009-03-27 | 2010-09-29 | 大连美明外延片科技有限公司 | GaN-based LED epitaxial wafer and growing method thereof |
| CN103208571A (en) * | 2013-04-08 | 2013-07-17 | 合肥彩虹蓝光科技有限公司 | GaN-based LED (light emitting diode) epitaxial wafer and production method thereof |
| CN103824915A (en) * | 2014-03-13 | 2014-05-28 | 华延芯光（北京）科技有限公司 | Gallium nitride-based light-emitting diode and preparation method thereof |
| CN103855263A (en) * | 2014-02-25 | 2014-06-11 | 广东省工业技术研究院(广州有色金属研究院) | GaN-base LED epitaxial wafer with polarization tunnel junction and preparation method of GaN-base LED epitaxial wafer |
| CN103887371A (en) * | 2014-03-24 | 2014-06-25 | 北京工业大学 | Technology method for evenly etching InP cardinal plane array device |
| CN104868023A (en) * | 2015-05-11 | 2015-08-26 | 南京大学 | III-nitride semiconductor/quantum dot hybrid white light LED device and preparing method thereof |
| CN106206874A (en) * | 2016-08-12 | 2016-12-07 | 泉州市三星消防设备有限公司 | A kind of electrode aberration ameliorative way of LED chip based on roughening epitaxial wafer |
| CN107994094A (en) * | 2017-11-22 | 2018-05-04 | 贵州振华风光半导体有限公司 | A kind of method for improving extension wavelength indium gallium arsenic detector etching injury |
| CN111490133A (en) * | 2019-01-29 | 2020-08-04 | 山东浪潮华光光电子股份有限公司 | Growth method for coarsening surface of GaN-based L ED blue-green light epitaxial wafer |
-
2021
- 2021-06-23 CN CN202110699384.0A patent/CN113421952A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847673A (en) * | 2009-03-27 | 2010-09-29 | 大连美明外延片科技有限公司 | GaN-based LED epitaxial wafer and growing method thereof |
| CN103208571A (en) * | 2013-04-08 | 2013-07-17 | 合肥彩虹蓝光科技有限公司 | GaN-based LED (light emitting diode) epitaxial wafer and production method thereof |
| CN103855263A (en) * | 2014-02-25 | 2014-06-11 | 广东省工业技术研究院(广州有色金属研究院) | GaN-base LED epitaxial wafer with polarization tunnel junction and preparation method of GaN-base LED epitaxial wafer |
| CN103824915A (en) * | 2014-03-13 | 2014-05-28 | 华延芯光（北京）科技有限公司 | Gallium nitride-based light-emitting diode and preparation method thereof |
| CN103887371A (en) * | 2014-03-24 | 2014-06-25 | 北京工业大学 | Technology method for evenly etching InP cardinal plane array device |
| CN104868023A (en) * | 2015-05-11 | 2015-08-26 | 南京大学 | III-nitride semiconductor/quantum dot hybrid white light LED device and preparing method thereof |
| CN106206874A (en) * | 2016-08-12 | 2016-12-07 | 泉州市三星消防设备有限公司 | A kind of electrode aberration ameliorative way of LED chip based on roughening epitaxial wafer |
| CN107994094A (en) * | 2017-11-22 | 2018-05-04 | 贵州振华风光半导体有限公司 | A kind of method for improving extension wavelength indium gallium arsenic detector etching injury |
| CN111490133A (en) * | 2019-01-29 | 2020-08-04 | 山东浪潮华光光电子股份有限公司 | Growth method for coarsening surface of GaN-based L ED blue-green light epitaxial wafer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8298842B2 (en) | Method for manufacturing semiconductor light-emitting device | |
| CN105702820B (en) | The reversed polarity AlGaInP base LED and its manufacturing method of surface covering ITO | |
| WO2010020069A1 (en) | METHOD FOR FABRICATING InGaAlN LIGHT-EMITTING DIODES WITH A METAL SUBSTRATE | |
| CN205723599U (en) | Surface covers the reversed polarity AlGaInP base LED of ITO | |
| CN108389955B (en) | Method for reducing voltage of 3D through hole superstructure LED chip by in-hole oxygen-free dry etching | |
| JP2012500479A (en) | Method for manufacturing a semiconductor light-emitting device with double-sided passivation | |
| US20110253972A1 (en) | LIGHT-EMITTING DEVICE BASED ON STRAIN-ADJUSTABLE InGaAIN FILM | |
| CN103247724B (en) | A kind of semiconductor structure and forming method thereof | |
| CN103999245A (en) | Semiconductor device and method of fabricating the same | |
| CN102569541B (en) | Manufacturing method of semiconductor luminous chip | |
| US7148149B2 (en) | Method for fabricating nitride-based compound semiconductor element | |
| CN109698123B (en) | Substrate corrosion method of GaAs-based LED wafer | |
| JP4314188B2 (en) | Method of manufacturing nitride compound semiconductor device | |
| CN113421952A (en) | Micro LED chip and preparation method thereof | |
| CN107123705A (en) | A kind of preparation method of light emitting diode | |
| CN111710761A (en) | LED chip preparation method | |
| CN101911258A (en) | Semiconductor device manufacturing method | |
| JP2005191099A (en) | Light-emitting diode device | |
| US8679877B2 (en) | Nitride semiconductor light emitting device and method for manufacturing the same | |
| US11715635B2 (en) | Removing or preventing dry etch-induced damage in Al/In/GaN films by photoelectrochemical etching | |
| CN110544736A (en) | Preparation method of GaN-based LED chip | |
| CN102447020A (en) | Method for manufacturing high-brightness vertical light emitting diode | |
| WO2020211145A1 (en) | Light-emitting element and manufacturing method thereof, and array substrate | |
| TWI438924B (en) | Method for manufacturing light emitting chip | |
| TW201411690A (en) | A reclaimed wafer and a method for reclaiming a wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210921 |