CN113421883A - Integrated chip and method of forming memory device - Google Patents

Integrated chip and method of forming memory device Download PDF

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Publication number
CN113421883A
CN113421883A CN202110110471.8A CN202110110471A CN113421883A CN 113421883 A CN113421883 A CN 113421883A CN 202110110471 A CN202110110471 A CN 202110110471A CN 113421883 A CN113421883 A CN 113421883A
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region
bit line
well region
disposed
substrate
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陈世宪
柯钧耀
徐英杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Various embodiments of the present disclosure are directed to an integrated chip that includes a first well region, a second well region, and a third well region disposed within a substrate. The second well region is laterally between the first well region and the third well region. An isolation structure is disposed within the substrate and laterally surrounds the first, second, and third well regions. A floating gate overlies the substrate and extends laterally from the first well region to the third well region. The dielectric structure is disposed under the floating gate. A bit line write region is disposed within the second well region and includes source/drain regions disposed on opposite sides of the floating gate. A bit line read region is disposed within the second well region and laterally offset from the bit line write region by a non-zero distance and includes source/drain regions disposed on opposite sides of the floating gate.

Description

Integrated chip and method of forming memory device
Technical Field
Embodiments of the invention relate to integrated chips and methods of forming memory devices.
Background
Many modern electronic devices include electronic memory configured to store data. The electronic memory may be a volatile memory (NVM) or a non-volatile memory (NVM). Volatile memory stores data when it is powered, while NVM is capable of holding data when power is removed. Multi-time programmable (MTP) cells are a promising candidate for next-generation NVM. The MTP cell may be integrated in a system-on-chip (SoC) application using a bipolar-complementary metal-oxide-semiconductor (CMOS) DMOS (bipolar-oxide-semiconductor, BCD) technology and/or a High Voltage (HV) CMOS technology. The MTP unit is integrated by using an HV (high voltage battery) technology or a BCD (binary coded decimal) technology and is applied to an internet of things (IoT), power management, a smart card, a microcontroller unit (MCU) and an automobile device.
Disclosure of Invention
In some embodiments, the present application provides an integrated chip comprising a first well region, a second well region, and a third well region disposed within a substrate, wherein the second well region is laterally spaced between the first well region and the third well region; an isolation structure is arranged in the front surface of the substrate, wherein the isolation structure transversely surrounds the first well region, the second well region and the third well region; a floating gate overlying the front surface of the substrate, wherein the floating gate continuously extends laterally from the first well region to the third well region; the dielectric structure is arranged between the substrate and the floating gate; a bit line write region disposed within the second well region, wherein the bit line write region includes source/drain regions disposed on opposite sides of the floating gate; a bit line read region is disposed within the second well region and laterally offset a non-zero distance from the bit line write region, wherein the bit line read region includes source/drain regions disposed on opposite sides of the floating gate.
In some embodiments, the present application provides an integrated chip comprising a well region disposed within a substrate; an isolation structure disposed within the front surface of the substrate, wherein the isolation structure laterally surrounds the well region; a bit line writing region disposed in the well region; a bit line reading region disposed in the well region and laterally offset from the bit line writing region by a non-zero distance; a first memory transistor comprising a source/drain region disposed within the bit line write region and a first gate electrode comprising a first floating gate portion of the floating gate, wherein the source/drain region of the first memory transistor is disposed on opposite sides of the floating gate, wherein the floating gate overlies the well region of the substrate; and a second memory transistor including a source/drain region disposed within the bit line read region and a second gate electrode including a second floating gate portion of the floating gate, wherein the source/drain region of the second memory transistor is disposed on an opposite side of the floating gate.
In some embodiments, the present application provides a method for forming a memory device, the method comprising forming an isolation structure in a substrate, wherein the isolation structure comprises inner sidewalls defining a device region of the substrate; doping the substrate to form a middle well region within a device region of the substrate; forming a floating gate on at least a portion of the middle well region and at least a portion of the isolation structure; and doping the substrate to form a bit line read region within a first portion of the middle well region and a bit line write region within a second portion of the middle well region, wherein the bit line read region includes source/drain regions on opposite sides of the floating gate and the bit line write region includes source/drain regions on opposite sides of the floating gate, wherein the first portion of the middle well region is laterally offset from the second portion of the middle well region by a non-zero value distance.
Drawings
Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A-1C illustrate various views of some embodiments of a memory cell including a floating gate overlying a first bit line active region and a second bit line active region.
Fig. 2 illustrates a block diagram of some embodiments of a circuit including multiple rows and columns of Memory Cells (MCs).
FIG. 3 illustrates a circuit diagram of some embodiments of the memory cell of FIGS. 1A-1C.
FIG. 4 illustrates a table corresponding to some embodiments of some operating conditions of the memory cells of FIGS. 1A-1C.
Fig. 5 illustrates a layout diagram of some embodiments of a memory cell including a plurality of p-channel metal oxide semiconductor (pMOS) transistors, according to some alternative embodiments of the memory cell of fig. 1A-1C.
FIG. 6 illustrates a table corresponding to some embodiments of some operating conditions of the memory cell of FIG. 5.
Fig. 7A-11B illustrate various views of some embodiments of forming a memory cell including a floating gate overlying a first bit line active region and a second bit line active region.
Fig. 12 illustrates a flow diagram of some embodiments of a method of forming a memory device including a floating gate overlying a first bit line active region and a second bit line active region.
Fig. 13A-13C illustrate various views of some embodiments of memory cells according to some alternative embodiments of the memory cells of fig. 1A-1C.
Fig. 14 illustrates cross-sectional views of some different embodiments of the memory cell of fig. 13A-13C.
Fig. 15A-19B illustrate various views of some embodiments of a second method for forming a memory cell including a floating gate overlying a first bit line active area and a second bit line active area.
Figure 20 illustrates a flow diagram of some embodiments of a second method for forming a memory cell including a floating gate overlying a first bit line active region and a second bit line active region.
Detailed Description
The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, formation of a first feature "over" or "on" a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to describe one element or feature's relationship to another (other) element or feature for ease of description. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.
The integrated chip may include a non-volatile memory (NVM) configured to retain stored information even when the integrated chip is not powered. Multiple Time Programmable (MTP) cells are one form of NVM that can include multiple transistors and multiple capacitors. For example, an MTP cell may include a storage transistor, a selection transistor, a coupling capacitor, and a tunneling capacitor (tunneling capacitor), such that the MTP cell is in a two-transistor two-capacitor (2T 2C) configuration. The coupling capacitor, the tunneling capacitor, and the storage transistor may share a floating gate. Further, the bit line may be coupled to a bit line active region disposed in a substrate underlying the floating gate. The floating gate may be separated from the substrate by a gate dielectric structure. The bit line active regions are discrete regions of the substrate and are part of the memory transistors. An appropriate bias voltage may be applied to the bit line active region to read the data value of the MTP cell or to write (e.g., erase or program) the data value of the MTP cell.
During operation, the MTP cell can be programmed and/or erased by Fowler-Nordheim (FN) tunneling. In an erase operation, charge stored in the floating gate can be moved from the floating gate to the first electrode of the tunneling capacitor by FN tunneling, thereby placing the MTP cell in a high resistance state. In a program operation, charge carriers (e.g., electrons) can be injected from the bit line active region into the floating gate by FN tunneling, thereby placing the MTP cell in a low resistance state. In a read operation, appropriate bias conditions are applied to the MTP cell so that the data state of the MTP cell can be accessed at the source/drain regions within the bitline active region. However, during erase or program operations, charge carriers may be trapped within the gate dielectric structure and/or damage the lattice of the gate dielectric structure. This may result in part in device failure, inaccurate read operations, and/or reduced device reliability after multiple programming operations. For example, inaccurate read operations may occur because charge carriers trapped within the gate dielectric structure may be mistaken for the data state of the MTP cell. For example, in applications utilizing 110 nanometer (nm) transistors or less than 110 nm transistors, the MTP cell may fail due to damage to the gate dielectric structure after about 10,000 program operations. In yet another example, in high voltage applications with 40 nm transistors, MTP cells may fail due to damage to the gate dielectric structure after about 1,000 program operations.
Accordingly, in some embodiments, the present application relates to an NVM memory cell having a four-transistor two-capacitor (4T2C) configuration and having increased endurance and reliability. The NVM cell includes a coupling capacitor, a tunneling capacitor, a first storage transistor, a second storage transistor, a first select transistor, and a second select transistor. The coupling capacitor, the tunneling capacitor, the first storage transistor and the second storage transistor share a floating gate overlying the substrate. The gate dielectric structure is disposed between the floating gate and the substrate. The first memory transistor and the select transistor include a bit line write active region, and the second memory transistor and the select transistor include a bit line read active region. The bit line read active region and the bit line write active region are each discrete regions of the substrate that are laterally offset from one another. The memory cell is configured to perform a program operation such that FN tunneling occurs between the floating gate and the bit line write active region. Further, the memory cell is configured to perform a read operation such that a data state of the memory cell can be accessed at the second select transistor and within the bit line read active region. Thus, the FN tunneling utilized in the program operation is isolated from the bit line read active region so that the gate dielectric structure between the floating gate and the bit line read active region is not damaged during the program operation. This may partially mitigate and/or eliminate damage to the gate dielectric structure of the read active region adjacent to the bit line, thereby increasing the number of program and/or erase operations that may be performed on the memory cell, reducing inaccurate read operations, and/or increasing the endurance of the memory cell.
1A-1C illustrate various views of some embodiments of a memory cell 100, the memory cell 100 including an overlying bit line write (BL)W) Region 112 and bit line read (BL)R) A Floating Gate (FG)120 over region 114. Fig. 1A illustrates some embodiments of a layout of a memory cell 100 from a front side 102f of a substrate 102. FIG. 1B illustrates various embodiments of a cross-sectional view taken along line A-A' of FIG. 1A. FIG. 1C shows an alternative embodiment of a cross-sectional view taken along line B-B' of FIG. 1A.
The memory cell 100 may include a plurality of transistors N1-N4 and a plurality of capacitors CEN、CWL. In some embodiments, memory cell 100 may be in a four transistor and two capacitor (4T2C) configuration. In a further embodiment, the memory cell 100 includes a conductive feature overlying the front surface 102f of the substrate 102 and a doped region disposed within the substrate 102. In some embodiments, the conductive features include FG120 and Select Gate (SG) 116. FG120 and SG 116 overlie front surface 102f of substrate 102. FG120 is separated from front surface 102f of substrate 102 by dielectric structure 134, and SG 116 is separated from front surface 102f of substrate 102 by select gate dielectric structure 152. In addition, sidewall spacer structures 118Laterally around the sidewalls of FG120 and SG 116, respectively. The isolation structure 103 extends from the front surface 102f of the substrate 102 to a point below the front surface 102 f. In a further embodiment, an interconnect dielectric structure 132 overlies FG120, SG 116, and front surface 102f of substrate 102. In some embodiments, the doped regions include a first well region 104, a second well region 106, and a third well region 108. The FG120 extends laterally continuously over the first well region 104, the second well region 106, and the third well region 108. In some embodiments, the FG120 includes a first FG portion 122 overlying the first well region 104, a second FG portion 124 overlying the second well region 106, and a third FG portion 126 overlying the third well region 108. An SG 116 overlies the second well 106. In some embodiments, SG 116 and FG120, for example, may each be or may each include a conductive material, such as polysilicon or another suitable conductive material.
In some embodiments, the first well region 104, the second well region 106, and the third well region 108 are laterally offset from one another by a non-zero distance and/or are discrete from one another. In some embodiments, the substrate 102 may be or may include, for example, a bulk semiconductor substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate material, and/or may include a first doping type (e.g., p-type). In some embodiments, the first well region 104 is a discrete region of the substrate 102 and comprises a second doping type (e.g., n-type) opposite the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. In a further embodiment, the second well region 106 is a discrete region of the substrate 102 and comprises a first doping type (e.g., p-type) having a higher doping concentration than the substrate 102. In still other embodiments, the third well 108 is a discrete region of the substrate 102 and includes a second doping type (e.g., n-type).
A first capacitor active region 110 is disposed within the first well region 104 and may include a second doping type (e.g., n-type). Thus, in some embodiments, the first capacitor active region 110 comprises the same doping type as the first well region 104. This facilitates the first capacitor active region 110 and the first well region 104 to be configured as the first capacitor CENThe first electrode of (1). In a further embodiment, a first FG portion 122 of the FG120 overlying the first capacitor active region 110 and/or the first well region 104 is configured as a first capacitor CENThe second electrode of (1). Thus, the area where the first FG portion 122 overlaps the first capacitor active region 110 and/or the first well region 104 defines a first capacitor CENThe capacitance of (c). Furthermore, the region of the dielectric structure 134 disposed between the first FG portion 122 and the first capacitor active region 110 and/or the first well region 104 may be configured as a first capacitor CENThe first capacitor dielectric layer of (1). The first capacitor active region 110 may include contact regions 110a, 110b disposed on opposite sides of the first FG portion 122. In some embodiments, the via 130 is disposed over the contact region 110a of the first capacitor active region 110 and is electrically coupled to an Erase Node (EN). In some embodiments, EN may be electrically coupled to an erase line configured to perform an erase operation on memory cell 100.
In some embodiments, the bit line write region 112 and the bit line read region 114 are both disposed within the second well region 106 and are laterally offset from each other by a non-zero distance. In some embodiments, the bit line write region 112 and the bit line read region 114 each comprise a second doping type (e.g., n-type), such that the bit line write region 112 and the bit line read region 114 comprise an opposite doping type as the second well region 106. Thus, in some embodiments, depletion regions may come from around the bit line write region 112 and the bit line read region 114, respectively, facilitating electrical isolation between the bit line write region 112 and the bit line read region 114. The second well region 106, the bit line write region 112, and the SG 116 are configured to form a first select transistor N1. The second well region 106, the bit line read region 114, and the SG 116 are configured to form a second select transistor N2. The second well region 106, the bit line write region 112 and the second FG portion 124 are configured to form a first memory transistor N3. The second well region 106, the bit line read region 114 and the second FG portion 124 are configured to form a second memory transistor N4. In some embodiments, transistors N1 through N4 may each be or may each include, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a high voltage transistor, a Bipolar Junction Transistor (BJT), an N-channel metal oxide semiconductor (nMOS) transistor, a p-channel metal oxide semiconductor (pMOS) transistor, or another suitable transistor. In some embodiments, transistors N1 through N4 are each configured as nMOS transistors. In further embodiments, transistors N1 through N4 are each configured as pMOS transistors.
A second FG portion 124 of FG120 divides the bit line write region 112 into a first source/drain region 140 and a second source/drain region 142. In some embodiments, the section of the second FG portion 124 disposed between the first and second source/ drain regions 140 and 142 is configured as a first floating gate (FG1) of the first memory transistor N3. SG 116 is laterally disposed between second source/drain region 142 and third source/drain region 144 of bit line write region 112. A section of SG 116 disposed between the second source/drain region 142 and the third source/drain region 144 is configured as a first select gate (SG1) of the first select transistor N1. A second FG portion 124 of FG120 divides the bit line read region 114 into a fourth source/drain region 146 and a fifth source/drain region 148. In some embodiments, the section of the second FG portion 124 disposed between the fourth and fifth source/ drain regions 146 and 148 is configured as a second floating gate (FG2) of the second memory transistor N4. SG 116 is laterally disposed between fifth source/drain region 148 and sixth source/drain region 150 of bit line read region 114. The section of SG 116 disposed between the fifth source/drain region 148 and the sixth source/drain region 150 is configured as a second select gate (SG2) of the second select transistor N2. In some embodiments, source/drain regions 140-150 may be configured as source or drain regions, respectively, for respective transistors, for example. In a further embodiment, the second source/drain region 142 is configured as a first common source/drain region shared by the first select transistor N1 and the first storage transistor N3 such that the first select transistor N1 is coupled in series with the first storage transistor N3. In still other embodiments, the fifth source/drain region 148 is configured as a second common source/drain region shared by the second select transistor N2 and the second storage transistor N4 such that the second select transistor N2 is coupled in series with the second storage transistor N4.
In some embodiments, the selector line is electrically coupled to SG 116 through overlying via 130. The selector lines may be configured to apply appropriate bias conditions to SG 116 during erase operations, program operations, and/or read operations performed on memory cells 100. In a further embodiment, a Source Line (SL) is electrically coupled to the third source/drain region 144 and/or the sixth source/drain region 150 through the via 130 and/or a conductive line (not shown). Thus, the third source/drain region 144 and the sixth source/drain region 150 may be electrically coupled together. SL may be configured to apply appropriate bias conditions to the source/drain regions of the first and second select transistors N1 and N2 during erase, program, and/or read operations performed on the memory cell 100.
In some embodiments, a first bit line (BL1) is electrically coupled to the first source/drain region 140 of the first memory transistor N3 through a via 130. In some embodiments, BL1 may be electrically coupled to supporting circuitry (e.g., a bit line decoder, a word line decoder, a control unit such as a microcontroller unit (MCU), etc.) (not shown), such as a bit line decoder (not shown) configured to perform a write operation (i.e., a program operation) on memory cell 100. In a further embodiment, a second bit line (BL2) is electrically coupled to fourth source/drain region 146 of second memory transistor N3 through via 130. In some embodiments, BL2 may be electrically coupled to support circuitry, such as a bit line decoder, configured to perform read operations on memory cell 100. In some embodiments, the width Ww of the bit line write region 112 is less than the width Wr of the bit line read region 114. In a further embodiment, the width Ww of the bit line write region 112 is equal to the width Wr of the bit line read region 114 (not shown).
In some embodiments, the second capacitor active region 117 is disposed within the third well 108 and may include a second doping type (e.g., n-type). Thus, in some embodiments, the second capacitor active region 117 comprises the same doping type as the third well 108. This facilitates the second capacitor active region 117 and the third well 108 being configured as a second capacitor CWLThe first electrode of (1). In some embodiments, overlying the second capacitor active region 117 and/or the third well region 108The third FG portion 126 of the FG120 is configured as a second capacitor CWLThe second electrode of (1). Thus, the area where the third FG portion 126 overlaps the second capacitor active region 117 and/or the third well region 108 defines a second capacitor CWLThe capacitance of (c). Furthermore, the region of the dielectric structure 134 disposed between the third FG portion 126 and the second capacitor active region 117 and/or the third well 108 may be configured as a second capacitor CWLOf the second capacitor dielectric layer. In some embodiments, one or more vias 130 overlie the second capacitor active region 117 and may be electrically coupled to a Word Line (WL). In some embodiments, the WL may be electrically coupled to support circuitry, such as a word line decoder (not shown), configured to perform read and/or write operations on the memory cell 100. In some embodiments, the area of the first FG portion 122 over the first capacitor active region 110 is smaller than the area of the third FG portion 126 over the second capacitor active region 117, so that the first capacitor CENIs smaller than the second capacitor CWLThe capacitance of (c).
In some embodiments, lightly doped region 136 is disposed within substrate 102 and may be disposed between FG120 and/or SG 116 and an adjacent active region (e.g., second capacitor active region 117, bit line write region 112, and/or bit line read region 114). In various embodiments, lightly doped region 136 comprises the same doping type (e.g., a second doping type) as the adjacent active region. In still other embodiments, lightly doped region 136 may have a lower doping concentration than an adjacent active region (e.g., second capacitor active region 117). In some embodiments, lightly doped region 136 may be a portion of an adjacent source/drain region.
In some embodiments, during a programming operation performed on the memory cell 100, charge carriers (e.g., electrons) may be injected into the FG120 from the first source/drain region 140 of the bit line write region 112 by fowler-nordheim (FN) tunneling. In such an embodiment, the programming operation may damage the section of the dielectric structure 134 disposed between the first floating gate FG1 and the second well region 106 and/or the bit line write region 112. In a further embodiment, during a read operation performed on the memory cell 100, the data state of the memory cell 100 may be accessed at the sixth source/drain region 150 of the bit line read region 114 by the second memory transistor N4 and the second select transistor N2. In such an embodiment, since the bit line write region 112 and the bit line read region 114 are laterally offset from each other by a non-zero distance, damage to the dielectric structure 134 from programming operations may not adversely affect the read operations performed on the memory cell 100. For example, the section of the dielectric structure 134 disposed between the second floating gate FG2 and the second well region 106 and/or the bit line read region 114 may not be damaged by the programming operation. This, in turn, may mitigate inaccurate read operations, increase the number of write operations (i.e., erase and/or program operations) that may be performed on the memory cell 100, and/or increase the reliability of the memory cell 100.
FIG. 2 illustrates a block diagram of some embodiments of a circuit 200 including multiple rows and columns of Memory Cells (MCs).
The circuit 200 includes a plurality of MCs, a plurality of bit lines BL1-m (m is an integer), a plurality of source lines SL1-n (n is an integer), a plurality of word lines WL1-n, a plurality of selector lines S1-n, a plurality of erase lines E1-n, a control unit 202, a Word Line (WL) decoder 204, and a Bit Line (BL) decoder 206. In some embodiments, the MCs may be configured as the memory cells 100 of FIGS. 1A-1C, respectively, such that each MC has a bit line write region (112 of FIG. 1A) that is laterally offset from a bit line read region (114 of FIG. 1A), and each MC is in a 4T2C configuration, respectively. The MC is arranged within a memory array that includes rows and columns. The MCs within a row of the memory array are operably coupled to a word line WL1-n, while the MCs within a column of the memory array are operably coupled to one or more bit lines BL 1-m. This associates the plurality of MCs with addresses defined by the intersection of a WL and one or more BL, respectively. In some embodiments, each MC may be configured as a non-volatile memory (NVM) Multiple Time Programmable (MTP) cell such that the resistance value of each MC may be set and/or reset between at least two resistance values. In further embodiments, the resistance value of each NVM MTP cell may be set and/or reset multiple times (e.g., greater than 10,000 set and/or reset operations may be performed per cell).
The memory array is electrically coupled to support circuitry configured to perform write operations (i.e., erase operations and/or program operations) and/or read operations on the plurality of MCs. In some embodiments, the support circuitry includes a control unit 202, a WL decoder 204, and a BL decoder 206. In a further embodiment, the control unit 202 is a microprocessor circuit. In still other embodiments, the plurality of selector lines S1-n and/or the plurality of erase lines E1-n may be electrically coupled to control unit 202 and/or WL decoder 204. The control unit 202 is configured to control the WL decoder 204 and/or the BL decoder 206, e.g., the control unit 202 may supply addresses (e.g., associated with a single MC in the memory array) to the WL decoder 204 and/or the BL decoder 206. In some embodiments, WL decoder 204 is configured to selectively apply signals (e.g., currents and/or voltages) to one or more of word lines WL1-n, one or more of erase lines E1-n, and/or one or more of selector lines S1-n based on a received address. BL decoder 206 is configured to selectively apply signals (e.g., currents and/or voltages) to one or more of bit lines BL1-m based on a received address. In some embodiments, the plurality of source lines SL1-n are electrically coupled to supporting read circuitry (not shown), such as multiplexers and/or amplifiers, configured to determine the output of a read operation.
In some embodiments, each MC is directly electrically coupled to at least two bit lines BL 1-m. For example, a first bit line BL1 and a second bit line BL2 are electrically coupled to the memory cell 100. In various embodiments, the first bit line BL1 is electrically coupled directly to a bit line write region (e.g., 112 of FIG. 1A), while the second bit line BL2 is electrically coupled directly to a bit line read region (e.g., 114 of FIG. 1A). In such an embodiment, the resistance value of the memory cell 100 may be set during a write operation (e.g., an erase or program operation) using the first BL1 and/or the bit line write region (e.g., 112 of fig. 1A), such that FN tunneling occurs in the bit line write region (e.g., 112 of fig. 1A). During a write operation, an unselect bias voltage (unselect bias voltage) may be applied to the second bit line BL2 such that the bit line read region (e.g., 114 of FIG. 1A) is unselected. Further, during a read operation performed on the memory cell 100, an unselected bias voltage is applied to the first bit line BL1, so that the bit line write region (e.g., 112 of fig. 1A) is not selected. Accordingly, during a write operation, FN tunneling may not occur in the bit line read region (e.g., 114 of fig. 1A), thereby increasing the endurance and reliability of the memory cell 100.
Fig. 3 illustrates a circuit diagram 300 of some embodiments of the memory cell 100 of fig. 1A-1C. Fig. 4 illustrates a table 400 corresponding to some embodiments of some operating conditions of the memory cell 100 of fig. 1A-1C.
As shown in fig. 3, the select gate SG includes a first select gate SG1 and a second select gate SG2 directly electrically coupled to each other. The select gate voltage V may be applied to the select gate SGSG. The first select transistor N1 includes a first select gate SG1, and the second select transistor N2 includes a second select gate SG 2. The first select source/drain region of the first select transistor N1 and the first select source/drain region of the second select transistor N2 are both electrically coupled to a source line SL. A source line voltage V may be applied to the source line SLSL. The first storage source/drain region of the first storage transistor N3 is electrically coupled directly to the second select source/drain region of the first select transistor N1. The first storage source/drain region of the second storage transistor N4 is electrically coupled directly to the second select source/drain region of the second select transistor N2. In some embodiments, the floating gate FG includes a first floating gate FG1 and a second floating gate FG 2. The first memory transistor N3 includes a first floating gate FG1, and the second memory transistor N4 includes a second floating gate FG 2. The second storage source/drain region of the first memory transistor N3 is electrically coupled directly to the first bit line BL1, and the second storage source/drain region of the second memory transistor N4 is electrically coupled directly to the second bit line BL 2. The first bit line voltage V may be applied to the first bit line BL1BL1And a second bit line voltage V may be applied to the second bit line BL2BL2。
A first capacitor CENIs arranged between the floating gate FG and the Erase Node (EN). In some embodiments, the first capacitor CENCan be defined by a first doped region of the substrate, e.g., a first capacitor active region (110 of FIG. 1A) and/or a first well region (104 of FIG. 1A), and a first capacitor CENSecond of (2)The electrodes may be defined by floating gates FG. In some embodiments, the first capacitor CENFor example, may be configured as a tunneling capacitor. Can be applied to the first capacitor CENFirst electrode applying an erase node voltage VEN. In some embodiments, the erase node voltage V may be applied to the first capacitor active region (110 of FIG. 1A)EN. In a further embodiment, the erase node voltage V may be applied directly to the first well region (104 of FIG. 1A)EN. In various embodiments, the erase node voltage VENFor example, to the first capacitor C via the erase line ELENThe first electrode of (1). A second capacitor CWLIs disposed between the floating gate FG and the word line WL. In some embodiments, the second capacitor CWLCan be defined by a second doped region of the substrate, e.g., a second capacitor active region (117 of fig. 1A) and/or a third well region (108 of fig. 1A), and a second capacitor CWLMay be defined by the floating gate FG. In some embodiments, the second capacitor CWLFor example, may be configured with a coupling capacitor. Can be applied to the second capacitor CWLFirst electrode of (2) applying a word line voltage VWL. In some embodiments, the word line voltage V may be applied directly to the third well region (108 of FIG. 1A)WL. In a further embodiment, the word line voltage V may be applied directly to the second capacitor active region (117 of FIG. 1A)WL. In various embodiments, the second capacitor C may be paired, for example, by a word line WLWLFirst electrode of (2) applying a word line voltage VWL。
Table 400 of fig. 4 illustrates some embodiments of various operating conditions of the circuit diagram of fig. 3. In some embodiments, select gate voltage V applied to select gate SG during an erase operationSGAbout 0 volts (V). Word line voltage VWLE.g., about 0V, and may be applied to the third well region (108 of fig. 1A). Erase node voltage VENSuch as a High Voltage (HV), and may be applied to the first well region (104 of fig. 1A). In some embodiments, HV may be, for example, in the range of about 7V to 10V, in the range of about 11V to 18V, in the range of about 7V to 18V, or another suitable value. First bit line voltage VBL1For example, is about0V and may be applied to a second storage source/drain region (e.g., first source/drain region 140 of fig. 1A) of the first storage transistor N3. Second bit line voltage VBL2For example, about 0V, and may be applied to a second storage source/drain region (e.g., the fourth source/drain region 146 of fig. 1A) of the second storage transistor N4. Source line voltage VSLIs about 0V and may be applied to the first select source/drain regions (e.g., the third source/drain region 144 and the sixth source/drain region 150 of fig. 1A) of the first select transistor N1 and the second select transistor N2. In some embodiments, bulk substrate voltage VBULKIs about 0V and may be applied to the bulk region of the substrate (102 of fig. 1A-1C). In a further embodiment, the bulk region of the substrate (102 of fig. 1A-1C) may be a region of the substrate (102 of fig. 1A-1C) that is offset with respect to the first, second, and third well regions (104, 106, 108 of fig. 1A). Under the above operating conditions, the first capacitor CENThe voltage at (C) is high enough that charge carriers (e.g. electrons) are discharged from the floating gate FG to the first capacitor C by FN tunnelingENE.g., the first well region (104 of fig. 1A) and/or the first capacitor active region (110 of fig. 1A)). This partially erases the data state of the floating gate FG, so that the floating gate FG is in a high resistance state. By utilizing FN tunneling to erase the floating gate FG, the power consumption of the circuit 300 may be reduced.
In some embodiments, the circuit diagram 300 of FIG. 3 is disposed in an array of memory cells. In such an embodiment, the circuit diagram 300 represents a single memory cell (e.g., the memory cell 100 of fig. 2) with a first unselected bit line voltage applied to the second storage source/drain of a first storage transistor of one or more unselected Memory Cells (MCs) and a second unselected bit line voltage applied to the second storage source/drain region of a second storage transistor of the one or more unselected Memory Cells (MCs) during an erase operation. In various embodiments, during an erase operation, the first unselected bit line voltage may be about 0V, and the second unselected bit line voltage may be about 0V. For example, in FIG. 2, the unselected bit line voltages applied to the bit lines BL3-m may each be approximately 0V, such that the MC coupled to the bit line BL3-m may not be erased by the erase operation performed on the memory cell 100.
In a further embodiment, during a program operation, the select gate voltage VSG is about 0V and may be applied to the select gate SG. Word line voltage VWLSuch as a High Voltage (HV) and may be applied to the third well region (108 of fig. 1A). In some embodiments, HV may be, for example, in the range of about 7V to 10V, in the range of about 11V to 18V, in the range of about 7V to 18V, or another suitable value. Erase node voltage VENSuch as HV, and may be applied to the first well region (104 of fig. 1A). First bit line voltage VBL1For example, about 0V, and may be applied to a second storage source/drain region of the first storage transistor N3 (e.g., the first source/drain region 140 of fig. 1A). Second bit line voltage VBL2For example, about half HV (e.g., about HV/2) and may be applied to a second storage source/drain region (e.g., fourth source/drain region 146 of fig. 1A) of the second storage transistor N4. Source line voltage VSLIs about 0V and may be applied to the first select source/drain regions (e.g., the third source/drain region 144 and the sixth source/drain region 150 of fig. 1A) of the first select transistor N1 and the second select transistor N2. In some embodiments, bulk substrate voltage VBULKIs about 0V and may be applied to the bulk region of the substrate (102 of fig. 1A-1C). Under the above operating conditions, by applying a voltage to the first capacitor CENAnd a second capacitor CWLApplying HV and applying about 0V to first bit line BL1, a reversal of the erase operation occurs such that charge carriers (e.g., electrons) are injected into the floating gate FG from the second storage source/drain region of first storage transistor N3 through FN tunneling. In some embodiments, charge carriers can be injected from the bit line write region (112 of FIG. 1A) and/or the second well region (106 of FIG. 1A). This partially programs the data state of the floating gate FG, so that the floating gate FG is in a low resistance state. By programming the floating gate FG using FN tunneling, the power consumption and programming time (e.g., write time) of the circuit 300 may be reduced. In a further embodiment, power consumption and programming time may be increased if the floating gate FG is programmed, for example, with a Channel Hot Electrode (CHE) injection (not shown).
In a further embodiment, the second storage transistor N4 may not be selected during a program operation by applying about half of HV (e.g., about HV/2) to a second storage source/drain region (e.g., the fourth source/drain region 146 of fig. 1A) of the second storage transistor N4 during the program operation. This, in turn, eliminates and/or mitigates the injection of charge carriers into the floating gate FG from the second storage source/drain region of the second storage transistor N4. Thus, the section of the dielectric structure (134 of fig. 1B-1C) underlying the second floating gate FG2 may not be damaged by FN tunneling. This increases the number of erase, write and/or read operations that can be performed on the floating gate FG, thereby increasing the reliability and endurance of the circuit 300.
In a further embodiment, when the circuit diagram 300 of fig. 3 is arranged within an MC array, the unselected bit line voltages may be applied to one or more unselected MCs. The unselected bit line voltage may be, for example, about half of HV (e.g., about HV/2) such that the one or more unselected MCs are not programmed. For example, in FIG. 2 and during a program operation, the unselected bit line voltage may be applied to the bit line BL 3-m.
In still other embodiments, during a read operation, the select gate voltage VSGIs about 5V and may be applied to select gate SG. In some embodiments, the select gate voltage VSGFor example, may be about 2.5V, 3.3V, or another suitable voltage, such that the first select transistor N1 and/or the second select transistor N2 are each in an ON (ON) state. Word line voltage VWLE.g., about 1.5V, and may be applied to the third well region (108 of fig. 1A). Erase node voltage VENE.g., about 0V, and may be applied to the first well region (104 of fig. 1A). First bit line voltage VBL1For example, about 0V, and may be applied to a second storage source/drain region (e.g., first source/drain region 140 of fig. 1A) of the first storage transistor N3. Second bit line voltage VBL2For example, about 1.2V, and may be applied to a second storage source/drain region (e.g., fourth source/drain region 146 of fig. 1A) of the second storage transistor N4. In some embodiments, bulk substrate voltage VBULKIs about 0V and may be applied to the bulk region of the substrate (102 of fig. 1A-1C). Under the above operating conditions, the source electrode can beThe data state of the FG floating gate is read at line SL. Due to the second bit line voltage VBL2Significantly less than the voltage (e.g., HV) applied for the program operation, damage to the section of the dielectric structure (134 of fig. 1B-1C) underlying the second floating gate FG2 is eliminated and/or reduced during the read operation. By laterally offsetting the bit line write region (112 of FIG. 1A) relative to the bit line read region (114 of FIG. 1A), the read operation may be immune to FN tunneling used during program operations. This, in turn, reduces and/or eliminates many inaccurate read operations and increases the reliability and endurance of the circuit 300. In a further embodiment, the unselected bit line voltage applied to one or more unselected MCs may be about 0V, e.g., in FIG. 2, the unselected bit line voltage may be applied to bit line BL 3-m.
Fig. 5 illustrates a layout diagram of some embodiments of a memory cell 500 including a plurality of p-channel metal oxide semiconductor (pMOS) transistors, according to some alternative embodiments of the memory cell 500 of fig. 1A-1C.
In some embodiments, the first well region 104, the second well region 106, and the third well region 108 each comprise a second doping type (e.g., n-type). In a further embodiment, the first capacitor active region 110, the second capacitor active region 117, the bit line write region 112, and the bit line read region 114 each comprise a first doping type (e.g., p-type) opposite the second doping type. Accordingly, in some embodiments, the plurality of transistors N1 through N4 may be configured as p-channel metal oxide semiconductor (pMOS) transistors, respectively.
Fig. 6 illustrates a table 600 corresponding to some embodiments of some operating conditions of the memory cell 500 of fig. 5.
In some embodiments, table 600 represents various operating conditions for memory cell 500 of fig. 5, where transistors N1 through N4 are configured as pMOS transistors. In some embodiments, the erase operation and the program operation of table 600 may be the same as the erase operation and the program operation performed on circuit 300 of FIG. 3, for example, shown and described in table 400 of FIG. 4.
In some embodiments, during a read operation, the select gate voltage VSGAbout 0V, word line voltagePressure VWLAbout 3.5V, the erase node voltage VENAbout 5V, the first bit line voltage VBL1About 5V, the second bit line voltage VBL2About 3.8V, source line voltage VSLIs about 5V and bulk substrate voltage VBULKAbout 5V. Under the above operating conditions, the data state of the FG floating gate may be read at the second selection transistor N2. In a further embodiment, the unselected bit line voltage applied to one or more unselected MCs may be about 5V, e.g., in FIG. 2, the unselected bit line voltage may be applied to bit line BL 3-m.
Fig. 7A-11B illustrate a series of various views 700 a-1100B of some embodiments of a method of forming a memory cell including a floating gate overlying a first bit line active area and a second bit line active area. The diagram with suffix "a" shows the layout of the memory cell during various formation processes. The figures with the suffix "B" are taken along the cut line of the corresponding figures with the suffix "a". Although the various views 700 a-1100B shown in fig. 7A-11B are set forth with reference to one approach, it should be understood that the structure shown in fig. 7A-11B is not limited to, but may be independent of, that approach. While fig. 7A-11B are illustrated as a series of acts, it will be appreciated that the acts are not limited as the order of the acts may be varied in other embodiments and that the disclosed methods are applicable to other configurations. In other embodiments, some acts shown and/or described may be omitted, in whole or in part.
As shown in fig. 7A to 7B, a substrate 102 is provided, and an isolation structure 103 is formed in the substrate 102. In some embodiments, the substrate 102 may be or may include a bulk semiconductor substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate material, and/or may include a first doping type (e.g., p-type), for example. In some embodiments, the isolation structure 103 may be formed by: the substrate 102 is selectively etched to form trenches in the substrate 102 that extend from the front surface 102f of the substrate 102 into the substrate 102, and the trenches are subsequently filled with a dielectric material (e.g., by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, or another suitable deposition or growth process). In some embodiments, the dielectric material may be or include, for example, silicon dioxide, silicon carbide, silicon nitride, another suitable dielectric material, or a combination of the foregoing. In a further embodiment, the substrate 102 may be selectively etched by forming a masking layer (not shown) on the front side 102f and then exposing the substrate 102 to an etchant configured to selectively remove unmasked portions of the substrate 102. In some embodiments, the isolation structure 103 may be configured as, for example, a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, or another suitable isolation structure.
As shown in fig. 8A-8B, one or more selective ion implantation processes may be performed to form a first well region 104, a second well region 106, and a third well region 108 in the substrate 102. In some embodiments, the first well region 104 and the third well region 108 may each be discrete regions of the substrate 102 having a second doping type (e.g., n-type) opposite the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. In a further embodiment, the second well region 106 may be a discrete region of the substrate 102 having a first doping type (e.g., p-type) with a doping concentration greater than a doping concentration of the substrate 102. In some embodiments, the one or more selective ion implantation processes may each comprise: a masking layer (not shown) is formed over the front side 102f of the substrate 102 and ions are selectively implanted in the substrate 102 according to the masking layer. In some embodiments, prior to forming the first, second, and third well regions 104, 106, 108, one or more buried N-layers (NBLs) (not shown) and/or one or more deep N-wells (DNWs) (not shown) may be formed within the substrate 102 such that the NBLs and/or DNWs underlie the first, second, and/or third well regions 104, 106, 108. In further embodiments, after forming the one or more NBLs and/or DNWs, one or more input/output contact regions (not shown) may be formed within the substrate 102. In some embodiments, the one or more input/output contact regions may be doped regions of the substrate 102 configured to facilitate electrical connection with the substrate 102. In some embodiments, the one or more input/output contact regions may include a bulk substrate contact region configured to facilitate application of a bulk substrate voltage to the substrate 102.
As shown in fig. 9A-9B, a dielectric structure 134 and a select gate dielectric structure (152 of fig. 1C) (not shown) are formed over the front surface 102f of the substrate 102. In addition, Floating Gate (FG)120 and Select Gate (SG)116 are formed on dielectric structure 134 and select gate dielectric structure (152 of FIG. 1C), respectively. In some embodiments, the dielectric structure 134 and/or the select gate dielectric structure (152 of fig. 1C) may be deposited, for example, by CVD, PVD, ALD, thermal oxidation, or another suitable deposition or growth process, respectively. In still other embodiments, the dielectric structure 134 and/or the select gate dielectric structure (152 of fig. 1C) may be or may respectively comprise, for example, silicon dioxide, a high-k dielectric material, or another suitable dielectric material. Furthermore, FG120 may be deposited (e.g., by CVD, PVD, ALD, sputtering, or another suitable growth or deposition process) on dielectric structure 134, and SG 116 may be deposited (e.g., by CVD, PVD, ALD, sputtering, or another suitable growth or deposition process) on select gate dielectric structure (152 of fig. 1C). FG120, SG 116, dielectric structure 134, and select gate dielectric structure (152 of fig. 1C) may then be patterned according to a masking layer (not shown). In still other embodiments, FG120 and/or SG 116 may be or may respectively comprise, for example, polysilicon (e.g., intrinsic and/or doped polysilicon), aluminum, another suitable conductive material, or a combination of the foregoing, respectively.
As also shown in fig. 9A-9B, the FG120 is a continuous conductive structure that extends laterally from over the first well region 104 to over the third well region 108. In some embodiments, a first FG portion 122 of a FG120 overlying a first well region 104 may have a width w1, and a second FG portion 124 of the FG120 overlying a second well region 106 may have a width w2 that is greater than the width w1 of the first FG portion 122. Furthermore, the third FG portion 126 of the FG120 may have a width w3 larger than the width w2 of the second FG portion 124.
As shown in fig. 10A-10B, sidewall spacer structures 118 are formed along sidewalls of FG120 and sidewalls of SG 116. In some embodiments, the sidewall spacer structure 118 may be formed by: depositing (e.g., by CVD, PVD, ALD, thermal oxidation, etc.) sidewall spacer material over substrate 102 and along the sidewalls of FG120 and SG 116; and subsequently patterning the spacer material to remove the spacer material from the horizontal surfaces, thereby forming sidewall spacer structures 118. In some embodiments, the sidewall spacer structure 118 may be or may include, for example, silicon nitride, silicon carbide, or another suitable dielectric material. In some embodiments, lightly doped region 136 may be formed within substrate 102 prior to forming sidewall spacer structures 118, and lightly doped region 136 may be aligned with one or more sidewalls of SG 116 and one or more sidewalls of FG 120. Lightly doped region 136 may be formed, for example, by selectively implanting ions into substrate 102 according to a masking layer (not shown). In some embodiments, lightly doped region 136 may comprise a second doping type (e.g., n-type).
In addition, as shown in fig. 10A to 10B, a first capacitor active region 110, a bit line write region 112, a bit line read region 114, and a second capacitor active region 117 are formed within the substrate 102. A first capacitor active region 110 is formed on opposite sides of the first FG portion 122 and within the first well region 104. A bit line write region 112 and a bit line read region 114 are formed on opposite sides of the second FG portion 124 and on opposite sides of the SG 116 within the second well region 106, respectively. A second capacitor active region 117 is formed around the sidewall of the third FG portion 126 within the third well 108. In some embodiments, the first capacitor active region 110, the bit line write region 112, the bit line read region 114, and the second capacitor active region 117 may each be formed by a selective ion implantation process that utilizes a masking layer (not shown) disposed over the front surface 102f of the substrate 102 to selectively implant dopants into the substrate 102. In a further embodiment, the first capacitor active region 110, the bit line write region 112, the bit line read region 114, and the second capacitor active region 117 may each comprise a second doping type (e.g., n-type).This in turn defines a plurality of transistors N1-N4 and a plurality of capacitors CEN、CWL. In still other embodiments, the bit line write region 112 is laterally offset from the bit line read region 114 by a non-zero distance.
As shown in fig. 11A-11B, a plurality of vias 130 are formed over the substrate 102, and the plurality of vias 130 may contact conductive structures (e.g., SG 116) and/or doped regions of the substrate 102. In addition, an interconnect dielectric structure 132 is formed over the substrate 102. In some embodiments, the via 130 is not formed over the FG120 such that the interconnect dielectric structure 132 extends continuously along the upper surface of the FG 120. In some embodiments, the via 130 can be or can include, for example, aluminum, copper, tungsten, tantalum, another suitable conductive material, or a combination of the foregoing. In various embodiments, the via 130 may be formed by a single damascene process. The interconnect dielectric structure 132 may be or include a plurality of inter-level dielectric (ILD) layers. The ILD layers may each be or may each comprise, for example, silicon dioxide, a low dielectric constant dielectric material, a very low dielectric constant dielectric material, another suitable dielectric material, or a combination of the foregoing. In various embodiments, the interconnect dielectric structure 132 may be deposited, for example, by CVD, PVD, ALD, or another suitable deposition process. In still other embodiments, an additional via (not shown) and/or a plurality of conductive lines (not shown) may be formed over the via 130 by a single damascene process and/or a dual damascene process.
As shown in fig. 12, a flow diagram 1200 of some embodiments of a method of forming a memory cell including a floating gate overlying a first bitline active area and a second bitline active area. While the flow diagram 1200 of fig. 12 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more acts illustrated herein may be performed in one or more separate acts and/or phases.
In act 1202, an isolation structure is formed in a substrate. Fig. 7A and 7B illustrate various views 700a and 700B of some embodiments corresponding to act 1202.
In act 1204, a first well region, a second well region, and a third well region are formed within the substrate. The second well region is laterally located between the first well region and the third well region. Fig. 8A and 8B illustrate various views 800a and 800B of some embodiments corresponding to act 1204.
In act 1206, a first Floating Gate (FG) and Select Gate (SG) are formed over a substrate. The FG extends laterally continuously from the first well region to the third well region, and the SG overlies the second well region. Fig. 9A and 9B illustrate various views 900a and 900B of some embodiments corresponding to act 1206.
In act 1208, a first capacitor active region, a bit line write region, a bit line read region, and a second capacitor active region are formed within the substrate, defining a plurality of capacitors and a plurality of transistors. The bit line writing area and the bit line reading area are arranged in the second well area and are laterally offset from each other. Fig. 10A and 10B illustrate various views 1000A and 1000B of some embodiments corresponding to act 1208.
In act 1210, a via and interconnect dielectric structure are formed over a substrate. 11A and 11B illustrate various views 1100a and 1100B corresponding to some embodiments of act 1210.
Fig. 13A-13C illustrate various views of a memory cell 1300 according to some embodiments of the present disclosure. Memory cell 1300 may include some aspects of memory cell 100 of fig. 1-1C (and vice versa). Thus, the features and/or reference symbols described above with respect to fig. 1-1C may also apply to the memory cell 1300 of fig. 13A-13C. Fig. 13A illustrates a layout of some embodiments of a memory cell 1300 as viewed from the front side 102f of the substrate 102. Fig. 13B illustrates a cross-sectional view of memory cell 1300 of some embodiments taken along line a-a' of fig. 13A. FIG. 13C illustrates a cross-sectional view of memory cell 1300 of various embodiments taken along line B-B' of FIG. 13B.
The memory cell 100 includes an isolation structure 103 disposed within a substrate 102. The isolation structure 103 extends from the front surface 102f to a point below the front surface 102 f. The isolation structure 103 may, for example, be configured as a Shallow Trench Isolation (STI) structure or another suitable isolation structure. The isolation structure 103 may be or comprise, for example, silicon dioxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, other dielectric materials, or any combination of the foregoing. In addition, the isolation structure 103 is configured to partition a device region of the substrate 102, wherein the first well region 104, the second well region 106, and the third well region 108 are disposed within the device region of the substrate 102. Thus, the isolation structure 103 laterally surrounds the first well region 104, the second well region 106, and the third well region 108, and is configured to electrically isolate the first well region 104, the second well region 106, and the third well region 108 from one another. In some embodiments, the second well region 106 may be referred to as a middle well region, the first well region 104 may be referred to as a first outer well region, and the third well region 108 may be referred to as a second outer well region.
Further, the isolation structure 103 includes an intermediate isolation segment 103m disposed laterally between the first peripheral isolation segment 103p1 and the second peripheral isolation segment 103p 2. In various embodiments, the top surface of the intermediate isolation section 103m is disposed below the top surfaces of the first and second peripheral isolation sections 103p1, 103p 2. In a further embodiment, the bottom surface of the intermediate isolation section 103m is disposed above the bottom surfaces of the first and second peripheral isolation sections 103p1, 103p 2. An intermediate isolation section 103m is disposed in an intermediate region of the second well region 106. The floating gate 120 extends continuously from the first peripheral isolation segment 103p1 through the intermediate isolation segment 103m to the second peripheral isolation segment 103p2 of the isolation structure. In addition, the floating gate 120 extends continuously from the first sidewall 1302 of the middle isolation segment 103m along the top surface of the middle isolation segment 103m to the second sidewall 1304 of the middle isolation segment 103 m. The first floating gate FG1 and the second floating gate FG2 are disposed on opposite sides of the intermediate isolation segment 103 m. First and second select gates SG1 and SG2 are disposed at opposite sides of the middle isolation segment 103 m.
In addition, the dielectric structure 134 includes a first dielectric segment 134s1 and a second dielectric segment 134s 2. The first dielectric segment 134s1 is disposed between the first floating gate FG1 and the second well region 106, and is disposed along the first sidewall 1302 of the intermediate isolation segment 103 m. The second dielectric segment 134s2 is disposed between the second floating gate FG2 and the second well region 106, and along the second sidewall 1304 of the intermediate isolation segment 103 m. Thus, the first and second dielectric segments 134s1, 134s2 are laterally spaced apart from each other by a non-zero distance.
In some embodiments, the bit line write region 112 and the bit line read region 114 are disposed on opposite sides of the middle isolation segment 103m of the isolation structure 103. For example, the bit line write region 112 extends continuously along the first sidewall 1302 of the middle isolation segment 103m and the bit line read region 114 extends continuously along the second sidewall 1304 of the middle isolation segment 103 m. The middle isolation segment 103m of the isolation structure 103 is configured to electrically isolate the bit line write region 112 and the bit line read region 114 from each other. For example, during a programming operation performed on the memory cell 1300, charge carriers (e.g., electrons) may be injected into the floating gate 120 from the first source/drain region 140 of the bit line write region 112 by fowler-nordheim (FN) tunneling. In such embodiments, the programming operation may damage the first dielectric segment 134s1 of the dielectric structure 134 disposed between the first floating gate FG1 and the second well region 106 and/or the bit line write region 112. Furthermore, during a programming operation, the intermediate isolation segment 103m of the isolation structure 103 is configured to prevent charge carriers from passing through the second well region 106 to the bit line read region 114. Thus, the intermediate isolation segment 103m increases the electrical isolation between the bit line write region 112 and the bit line read region 114, thereby improving the performance of the memory cell 1300.
In a further embodiment, during a read operation performed on the memory cell 1300, the data state of the memory cell 1300 may be accessed at the sixth source/drain region 150 of the bit line read region 114 by the second memory transistor N4 and the second select transistor N2. In such embodiments, since the bit line write region 112 and the bit line read region 114 are disposed on opposite sides of the middle isolation segment 103m of the isolation structure 103, damage to the first dielectric segment 134s1 of the dielectric structure 134 by a programming operation may not adversely affect the read operation performed on the memory cell 1300. For example, by virtue of the intermediate isolation segment 103m of the isolation structure 103, the second dielectric segment 134s2 is laterally offset from the first dielectric segment 134s1 such that the second dielectric segment 134s2 may not be damaged by programming operations. This may mitigate inaccurate read operations, increase the number of program operations (i.e., erase and/or program operations) that may be performed on the memory cell 1300, and/or increase the reliability of the memory cell 1300.
Fig. 14 illustrates a cross-sectional view of some alternative embodiments of the memory cell 1300 taken along line a-a' of fig. 13A, wherein the top surface of the middle isolation segment 103m of the isolation structure 103 is vertically aligned with the top surfaces of the first and second peripheral isolation segments 103p1, 103p 2. In a further embodiment, the bottom surface of the middle isolation section 103m of the isolation structure 103 is vertically aligned with the bottom surfaces of the first and second peripheral isolation sections 103p1, 103p 2. This may in part further increase the electrical isolation between the bit line write region (112 of FIG. 13A) and the bit line read region (114 of FIG. 13A).
15A-19B illustrate a series of various views 1500a-1900B of some embodiments of a second method for forming a memory cell including a floating gate overlying a first bit line active area and a second bit line active area. The figures with the suffix "a" show the layout of the memory cell during various formation processes. The figures with the suffix "B" are taken along the section lines of the corresponding figures with the suffix "a". Although the various views 1500a-1900B shown in FIGS. 15A-19B are described with reference to the second method, it should be understood that the structure shown in FIGS. 15A-19B is not limited to the second method, but may be separated from the second method independently. While fig. 15A-19B are described as a series of acts, it is to be understood that the acts are not limited to acts that can change order in other embodiments and that the disclosed methods are applicable to other configurations. In other embodiments, some acts illustrated and/or described may be omitted, in whole or in part.
As illustrated in fig. 15A to 15B, a substrate 102 is provided, and an isolation structure 103 is formed in the substrate 102. In some embodiments, the isolation structure 103 extends into the front side 102f of the substrate 102 and is formed such that the isolation structure 103 demarcates a device region 1502 of the substrate 102. In various embodiments, the device region 1502 of the substrate 102 includes one or more polygonal regions such that the isolation structures 108 have one or more polygonal ring layouts.
In some embodiments, the substrate 102 may be or include, for example, a bulk semiconductor substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or other suitable substrate material and/or may include a first doping type (e.g., p-type). In some embodiments, the isolation structure 103 may be formed by selectively etching the substrate 102 to form a trench in the substrate 102 that extends from the front surface 102f of the substrate 102 into the substrate 102, and then filling (e.g., by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation, or other suitable deposition or growth process) the trench with a dielectric material. In some embodiments, the dielectric material may be or include, for example, silicon dioxide, silicon carbide, silicon nitride, other suitable dielectric materials, or combinations of the foregoing. In a further embodiment, the substrate 102 may be selectively etched by forming a mask layer (not shown) on the front surface 102f and then exposing the substrate 102 to an etchant configured to selectively remove unmasked portions of the substrate 102. In some embodiments, the isolation structure 103 may be configured, for example, as a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, or other suitable isolation structure. The isolation structure 103 includes a middle isolation section 103m disposed laterally between the first peripheral isolation section 103p1 and the second peripheral isolation section 103p 2. In various embodiments, the top surface of the intermediate isolation section 103m is disposed below the top surfaces of the first and second peripheral isolation sections 103p1, 103p 2. In still other embodiments, the bottom surface of the intermediate isolation section 103m is disposed above the bottom surfaces of the first and second peripheral isolation sections 103p1, 103p 2.
As shown in fig. 16A-16B, one or more selective ion implantation processes may be performed to form the first well region 104, the second well region 106, and the third well region 108 in the device region (1502 of fig. 15A-15B) of the substrate 102. In some embodiments, the first well region 104 and the third well region 108 may each be discrete regions of the substrate 102 having a second doping type (e.g., n-type) opposite the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. In other embodiments, the second well region 106 may be a discrete region of the substrate 102 having a first doping type (e.g., p-type) with a doping concentration greater than a doping concentration of the substrate 102. In some embodiments, the one or more selective ion implantation processes may each comprise: a mask layer (not shown) is formed on the front surface 102f of the substrate 102, and ions are selectively implanted into the substrate 102 according to the mask layer. In some embodiments, one or more buried N-layers (NBLs) (not shown) and/or one or more deep N-wells (DNWs) (not shown) may be formed within the substrate 102 prior to forming the first, second, and third well regions 104, 106, 108 such that the NBLs and/or DNWs are located below the first, second, and/or third well regions 104, 106, 108. In further embodiments, after forming one or more NBLs and/or DNWs, one or more input/output contact regions (not shown) may be formed within the substrate 102. In some embodiments, the one or more input/output contact regions may be doped regions of the substrate 102 configured to facilitate electrical connection with the substrate 102. In some embodiments, the one or more input/output contact regions may include a bulk substrate contact region configured to facilitate application of a bulk substrate voltage to the substrate 102.
In addition, as shown in the cross-sectional view 1600B of FIG. 16B, the middle isolation segment 103m of the isolation structure 103 is disposed in the middle region of the second well region 106. In some embodiments, the second well region 106 extends from a first sidewall of the middle isolation section 103m to a second sidewall of the middle isolation section 103m along the bottom surface of the middle isolation section 103 m. In addition, the second well region 106 extends continuously from the first peripheral isolation section 103p1 of the isolation structure 103 to the second peripheral isolation section 103p2 of the isolation structure 103.
As shown in fig. 17A-17B, a dielectric structure 134 and a select gate dielectric structure (152 of fig. 13C) (not shown) are formed over the front surface 102f of the substrate 102. In addition, Floating Gate (FG)120 and Select Gate (SG)116 are formed on dielectric structure 134 and select gate dielectric structure (152 of fig. 13C), respectively. In some embodiments, the dielectric structure 134 and/or the select gate dielectric structure (152 of fig. 13C) may be deposited, for example, by CVD, PVD, ALD, thermal oxidation, or other suitable deposition or growth process, respectively. In still other embodiments, the dielectric structure 134 and/or the select gate dielectric structure (152 of fig. 13C) may be or include, for example, silicon dioxide, a high-k dielectric material, or other suitable dielectric material, respectively. Furthermore, the floating gate 120 may be deposited (e.g., by CVD, PVD, ALD, sputtering, or other suitable growth or deposition process) on the dielectric structure 134, and the select gate 116 may be deposited (e.g., by CVD, PVD, ALD, sputtering, or other suitable growth or deposition process) on the select gate dielectric structure (152 of fig. 13C). Subsequently, the floating gate 120, the select gate 116, the dielectric structure 134, and the select gate dielectric structure (152 of fig. 13C) may be patterned according to a mask layer (not shown). In still other embodiments, the floating gate 120 and/or the select gate 116 may be or include, for example, intrinsic polysilicon and/or doped polysilicon, aluminum, other suitable conductive materials, or combinations of the foregoing, respectively.
As also shown in fig. 17A-17B, the floating gate 120 is a continuous conductive structure that extends laterally from over the first well region 104 to over the third well region 108. In some embodiments, the first FG portion 122 of the floating gate 120 overlying the first well region 104 may have a width w1, and the width w2 of the second FG portion 124 of the floating gate 120 overlying the second well region 106 may be greater than the width w1 of the first FG portion 122. Furthermore, the width w3 of the third FG portion 126 of the FG120 may be larger than the width w2 of the second FG portion 124. Furthermore, dielectric structures 134 are disposed along opposing sidewalls of the middle isolation segment 103m of the isolation structure 103. In some embodiments, the FG120 extends continuously from the first peripheral isolation segment 103p1 along the intermediate isolation segment 103m to the second peripheral isolation segment 103p2 of the isolation structure 103. Furthermore, a first height of the FG120 over the intermediate isolation segment 103m is smaller than a second height of the FG120 over the first peripheral isolation segment 103p1 and/or the second peripheral isolation segment 103p2 of the isolation structure 103. Furthermore, FG120 extends continuously from a first sidewall of the intermediate isolation segment 103m along the top surface of the intermediate isolation segment 103m to a second sidewall of the intermediate isolation segment 103 m. The dielectric structure 134 contacts a first sidewall of the intermediate isolation segment 103m and a second sidewall of the intermediate isolation segment 103 m.
As shown in fig. 18A-18B, sidewall spacer structures 118 are formed along sidewalls of FG120 and sidewalls of SG 116. In some embodiments, forming sidewall spacer structures 118 may be performed by depositing (e.g., by CVD, PVD, ALD, thermal oxidation, etc.) spacer material over substrate 102 and along sidewalls of FG120 and SG 116; the spacer material is then patterned to remove the spacer material from the horizontal surfaces, thereby forming sidewall spacer structures 118. In some embodiments, the sidewall spacer structure 118 may be or include, for example, silicon nitride, silicon carbide, or other suitable dielectric material. In some embodiments, lightly doped regions 136 may be formed within substrate 102 and may be aligned with one or more sidewalls of SG 116 and one or more sidewalls of FG120 prior to forming sidewall spacer structures 118. For example, lightly doped regions 136 may be formed by selectively implanting ions into substrate 102 according to a mask layer (not shown). In some embodiments, lightly doped region 136 may comprise a second doping type (e.g., n-type).
In addition, as shown in fig. 18A to 18B, a first capacitor active region 110, a bit line write region 112, a bit line read region 114, and a second capacitor active region 117 are formed in the substrate 102. First capacitor active regions 110 are formed on opposite sides of the first FG portion 122 and within the first well region 104. Bit line write region 112 and bit line read region 114 are formed on opposite sides of second FG portion 124 and on opposite sides of SG 116, respectively, and within second well region 106. A second capacitor active region 117 is formed around a sidewall of a third FG portion 126 within the third well 108. In some embodiments, the first capacitor active region 110, the bit line write region 112, the bit line read region 114, and the second capacitor active region 110 may each be formed by a selective ion implantation process that utilizes a mask layer (not shown) disposed over the front surface 102f of the substrate 102 to selectively implant dopants into the substrate 102. In other embodiments, the first capacitor active region 110, the bit line write region 112, the bit line read region 114, and the second capacitor active region 117 may each include a second doping type (e.g., n-type). This in turn forms a plurality of transistors N1-N4 and a plurality of capacitors CEN，CWL. In still other embodiments, the bit line write region 112 and the bit line read region 114 are laterally offset from each otherA distance of zero.
Further, as shown in fig. 18A, a bit line write region 112 and a bit line read region 114 are formed on opposite sides of the middle isolation segment 103m of the isolation structure 103. The middle isolation segment 103m of the isolation structure 103 is configured to electrically isolate the bit line write region 112 from the bit line read region 114. In a further embodiment, the sidewall spacer structure 118 directly overlies the intermediate isolation segment 103m of the isolation structure 103. Sidewall spacer structures 118 disposed along sidewalls of the FG120 extend continuously from the first peripheral isolation segment 103p1 along the intermediate isolation portion 103m to the second peripheral isolation segment 103p2 of the isolation structure 103. Spacer structures 118 disposed along sidewalls of SG 116 extend continuously from second peripheral isolation segment 103p2 to intermediate isolation segment 103m of isolation structure 103.
As shown in fig. 19A-19B, a plurality of conductive vias 130 are formed over the substrate 102 and may contact conductive structures (e.g., SG 116) and/or doped regions of the substrate 102. In addition, an interconnect dielectric structure 132 is formed over the substrate 102. In some embodiments, conductive vias 130 are not formed over FG120 such that interconnect dielectric structures 132 extend continuously along the upper surface of FG 120. In some embodiments, the conductive vias 130 may be or include, for example, aluminum, copper, tungsten, tantalum, other suitable conductive materials, or combinations of the foregoing. In various embodiments, conductive vias 130 may be formed by a single damascene process. The interconnect dielectric structure 132 may be or include a plurality of interlayer dielectric (ILD) layers. The ILD layers may, for example, each be or include silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, other suitable dielectric materials, or combinations of the foregoing. In various embodiments, the interconnect dielectric structure 132 may be deposited, for example, by CVD, PVD, ALD, or other suitable deposition process. In yet another embodiment, additional conductive vias (not shown) and/or multiple conductive lines (not shown) may be formed over conductive vias 130 by a single damascene process and/or a dual damascene process.
As shown in fig. 20, a flow diagram 2000 of some embodiments of a second method for forming a memory cell including a floating gate overlying a first bit line active region and a second bit line active region. Although the flow diagram 2000 of fig. 20 is depicted and described herein as a series of acts or events, it will be appreciated that the order of such acts or events in the drawings is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more acts described herein may be performed in one or more separate acts and/or phases.
In act 2002, an isolation structure is formed in a substrate such that the isolation structure includes an intermediate isolation segment laterally disposed between a first peripheral isolation segment and a second peripheral isolation segment. 15A and 15B illustrate various views 1500a and 1500B of some embodiments corresponding to act 2002.
In act 2004, a first well region, a second well region, and a third well region are formed within a substrate. The second well region is laterally located between the first well region and the third well region, and the intermediate isolation section of the isolation structure is disposed within the second well region. Fig. 16A and 16B illustrate various views 1600a and 1600B of some embodiments corresponding to act 2004.
In act 2006, a first Floating Gate (FG) and Select Gate (SG) are formed over a substrate. The FG extends laterally continuously from the first well region to the third well region. In addition, the SG overlies the second well region and the intermediate isolation segment of the isolation structure. Fig. 17A and 17B illustrate various views 1700a and 1700B of some embodiments corresponding to act 2006.
In act 2008, a first capacitor active region, a bit line write region, a bit line read region, and a second capacitor active region are formed within a substrate, thereby defining a plurality of capacitors and a plurality of transistors. A bit line write region and a bit line read region are disposed within the second well region and on opposite sides of the middle isolation segment of the isolation structure. Fig. 18A and 18B illustrate various views 1800a and 1800B corresponding to some embodiments of act 2008.
In act 2010, conductive vias and interconnect dielectric structures are formed over a substrate. Fig. 19A and 19B illustrate various views 1900a and 1900B of some embodiments corresponding to act 2010.
Accordingly, in some embodiments, the present disclosure relates to a memory cell comprising a plurality of capacitors and a plurality of transistors disposed above and/or within a substrate, wherein the memory cell is in a two-capacitor four-transistor (2C4T) configuration. The memory cell includes a bit line write region and a bit line read region disposed within the well region and laterally offset from each other. The isolation structure is disposed within the substrate such that the isolation structure includes an intermediate isolation segment disposed laterally between the bit line write region and the bit line read region.
In some embodiments, the present application provides an integrated chip comprising a first well region, a second well region, and a third well region disposed within a substrate, wherein the second well region is laterally spaced between the first well region and the third well region; an isolation structure is arranged in the front surface of the substrate, wherein the isolation structure transversely surrounds the first well region, the second well region and the third well region; a floating gate overlying the front surface of the substrate, wherein the floating gate continuously extends laterally from the first well region to the third well region; the dielectric structure is arranged between the substrate and the floating gate; a bit line write region disposed within the second well region, wherein the bit line write region includes source/drain regions disposed on opposite sides of the floating gate; a bit line read region is disposed within the second well region and laterally offset a non-zero distance from the bit line write region, wherein the bit line read region includes source/drain regions disposed on opposite sides of the floating gate. In some embodiments, the width of the bit line write region is less than the width of the bit line read region. In some embodiments, the floating gate has a first width over the first well region, the floating gate has a second width over the second well region, and the floating gate has a third width over the third well region, wherein the first width is less than the second width, and the second width is less than the third width. In some embodiments, the isolation structure includes an intermediate isolation segment disposed within the second well region, wherein the bit line write region is disposed along a first sidewall of the intermediate isolation segment and the bit line read region is disposed along a second sidewall of the intermediate isolation segment, wherein the first sidewall is opposite to the second sidewall. In some embodiments, the second well region extends continuously from the first sidewall to the second sidewall along a floor of the intermediate isolation segment. In some embodiments, the dielectric structure includes a first dielectric segment and a second dielectric segment laterally offset from each other by a non-zero distance, wherein the first dielectric segment is disposed along the first sidewall of the intermediate isolation segment and the second dielectric segment is disposed along the second sidewall of the intermediate isolation segment. In some embodiments, the isolation structure further comprises a first peripheral isolation segment and a second peripheral isolation segment, wherein the intermediate isolation segment is laterally disposed between the first peripheral isolation segment and the second peripheral isolation segment, wherein the floating gate extends laterally continuously from the first peripheral isolation segment to the second peripheral isolation segment along the intermediate isolation segment. In some embodiments, the height of the floating gate above the intermediate isolation segment is less than the height of the floating gate above the first peripheral isolation segment. In some embodiments, a bottom surface of the intermediate isolation segment is vertically above a bottom surface of the first peripheral isolation segment.
In some embodiments, the present application provides an integrated chip comprising a well region disposed within a substrate; an isolation structure disposed within the front surface of the substrate, wherein the isolation structure laterally surrounds the well region; a bit line writing region disposed in the well region; a bit line reading region disposed in the well region and laterally offset from the bit line writing region by a non-zero distance; a first memory transistor comprising a source/drain region disposed within the bit line write region and a first gate electrode comprising a first floating gate portion of the floating gate, wherein the source/drain region of the first memory transistor is disposed on opposite sides of the floating gate, wherein the floating gate overlies the well region of the substrate; and a second memory transistor including a source/drain region disposed within the bit line read region and a second gate electrode including a second floating gate portion of the floating gate, wherein the source/drain region of the second memory transistor is disposed on an opposite side of the floating gate. In some embodiments, the isolation structure includes a first peripheral isolation segment, a second peripheral isolation segment, and an intermediate isolation segment laterally disposed between the first peripheral isolation segment and the second peripheral isolation segment, wherein the source/drain region of the first memory transistor is disposed along a first sidewall of the intermediate isolation segment, and wherein the source/drain region of the second memory transistor is disposed along a second sidewall of the intermediate isolation segment, wherein the first sidewall is opposite the second sidewall. In some embodiments, a first height of the floating gate laterally disposed between the first peripheral isolation segment and the intermediate isolation segment is less than a second height of the floating gate above the intermediate isolation segment. In some embodiments, the intermediate isolation segment has a width less than a width of the first peripheral isolation segment, and the intermediate isolation segment has a width less than a width of the second peripheral isolation segment. In some embodiments, the well region extends continuously along a floor of the intermediate isolation segment from a sidewall of the first peripheral isolation segment to a sidewall of the second peripheral isolation segment. In some embodiments, the integrated chip further comprises: a first selector transistor including a source/drain region disposed within the bit line write region and a first select gate electrode including a first select gate portion of a select gate, wherein the first select transistor is disposed along the first sidewall of the intermediate isolation segment; and a second select transistor including a source/drain region disposed within the bit line read region and a second select gate electrode including a second select gate portion of the select gate, wherein the second select transistor is disposed along the second sidewall of the intermediate isolation segment. In some embodiments, the select gate extends laterally continuously from the second peripheral isolation segment to the intermediate isolation segment, wherein the select gate is laterally offset from the first peripheral isolation segment by a non-zero distance.
In some embodiments, the present application provides a method for forming a memory device, the method comprising forming an isolation structure in a substrate, wherein the isolation structure comprises inner sidewalls defining a device region of the substrate; doping the substrate to form a middle well region within a device region of the substrate; forming a floating gate on at least a portion of the middle well region and at least a portion of the isolation structure; and doping the substrate to form a bit line read region within a first portion of the middle well region and a bit line write region within a second portion of the middle well region, wherein the bit line read region includes source/drain regions on opposite sides of the floating gate and the bit line write region includes source/drain regions on opposite sides of the floating gate, wherein the first portion of the middle well region is laterally offset from the second portion of the middle well region by a non-zero value distance. In some embodiments, the isolation structure includes a first peripheral isolation section, a second peripheral isolation section, and an intermediate isolation section disposed between the first peripheral isolation section and the second peripheral isolation section, wherein the intermediate isolation section is laterally disposed between the first portion of the intermediate well region and the second portion of the intermediate well region. In some embodiments, the bit line write region is disposed along a first sidewall of the intermediate isolation segment, wherein the bit line read region is disposed along a second sidewall of the intermediate isolation segment, and wherein the first sidewall is opposite the second sidewall. In some embodiments, a dielectric structure is formed between the floating gate and the substrate such that the dielectric structure includes first and second dielectric segments disposed on opposite sides of the intermediate isolation segment.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
[ description of symbols ]
100. 500, 1300: memory cell
102: substrate
102 f: front side
103: isolation structure
103 m: intermediate isolation section
103p 1: a first peripheral isolation section
103p 2: second peripheral isolation section
104: the first well region
106: second well region
108: third well area
110 first capacitor active region
110a, 110 b: contact zone
112、BLW: bit line write area
114、BLR: bit line read region
116: selection grid
117: second capacitor active region
118: sidewall spacer structure
120. FG: floating gate
122: first FG section
124: second FG section
126: third FG section
130: conducting hole
1302: first side wall
1304: second side wall
132: interconnect dielectric structure
134: dielectric structure
134s 1: a first dielectric segment
134s 2: a second dielectric segment
136: lightly doped region
140: first source/drain region
142: second source/drain region
144: third source/drain region
146: fourth source/drain region
148: fifth source/drain region
150: sixth source/drain region
1502: device area
152: select gate dielectric structure
200: circuit arrangement
202: control unit
204: word Line (WL) decoder
206: bit Line (BL) decoder
300: circuit diagram/circuit
400. 600: watch (A)
700a, 700b, 800a, 800b, 900a, 900b, 1000a, 1000b, 1100a, 1100b, 1500a, 1500b, 1600a, 1600b, 1700a, 1700b, 1800a, 1800b, 1900a, 1900 b: view of the drawing
1200. 2000: flow chart
1202. 1204, 1206, 1208, 1210, 2002, 2004, 2006, 2008, 2010: movement of
A-A ', B-B': thread
BL, BL3, BL4, BL5, BL6, BL (m-1), BLm: bit line
BL 1: bit line/first bit line
BL 2: bit line/second bit line
CEN: capacitor/first capacitor
CWL: capacitor/second capacitor
EN: erase node
E1, E2, E3, En: erase line
FG 1: a first floating gate
FG 2: a second floating gate
HV: high voltage
MC: memory cell
N1: transistor/first selection transistor
N2: transistor/second selection transistor
N3: transistor/first storage transistor
N4: transistor/second storage transistor
S1, S2, S3, Sn: selector wire
SG: selection grid
SG 1: a first selection gate
SG 2: second selection grid
SL, SL1, SL2, SL3, SLn: source line
VBULK: bulk substrate voltage
VBL1: first bit line voltage
VBL2: second bit line voltage
VEN: erase node voltage
VWL: word line voltage
VSG: select gate voltage
VSL: source line voltage
WL, WL1, WL2, WL3, WLn: word line
w1, w2, w3, Wr, Ww: width of

Claims (10)

1. An integrated chip, comprising:
a first well region, a second well region, and a third well region disposed within a substrate, wherein the second well region is laterally spaced between the first well region and the third well region;
an isolation structure disposed within a front surface of the substrate, wherein the isolation structure laterally surrounds the first well region, the second well region, and the third well region;
a floating gate overlying the front surface of the substrate, wherein the floating gate extends laterally from the first well region to the third well region continuously;
a dielectric structure disposed between the substrate and the floating gate;
a bit line write region disposed within the second well region, wherein the bit line write region includes source/drain regions disposed on opposite sides of the floating gate; and
a bit line read region disposed within the second well region and laterally offset from the bit line write region by a non-zero distance, wherein the bit line read region includes source/drain regions disposed on the opposite sides of the floating gate.
2. The integrated chip of claim 1, wherein the floating gate has a first width over the first well region, a second width over the second well region, and a third width over the third well region, wherein the first width is less than the second width, and the second width is less than the third width.
3. The integrated chip of claim 1, wherein the isolation structure comprises an intermediate isolation segment disposed within the second well region, wherein the bit line write region is disposed along a first sidewall of the intermediate isolation segment and the bit line read region is disposed along a second sidewall of the intermediate isolation segment, wherein the first sidewall is opposite the second sidewall.
4. An integrated chip, comprising:
a well region disposed within a substrate;
an isolation structure disposed within a front surface of a substrate, wherein the isolation structure laterally surrounds the well region;
a bit line write region disposed within the well region;
a bit line read region disposed within the well region and laterally offset a non-zero distance from the bit line write region;
a first memory transistor comprising a source/drain region disposed within the bit line write region and a first gate electrode comprising a first floating gate portion of a floating gate, wherein the source/drain region of the first memory transistor is disposed on opposite sides of the floating gate, wherein the floating gate overlies the well region of the substrate; and
a second memory transistor including a source/drain region disposed within the bit line read region and a second gate electrode including a second floating gate portion of the floating gate, wherein the source/drain region of the second memory transistor is disposed on an opposite side of the floating gate.
5. The integrated chip of claim 4, wherein a first height of the floating gate disposed laterally between the first peripheral isolation segment and the intermediate isolation segment is less than a second height of the floating gate above the intermediate isolation segment.
6. The integrated chip of claim 4, wherein the width of the intermediate isolation segment is less than the width of the first peripheral isolation segment, and the width of the intermediate isolation segment is less than the width of the second peripheral isolation segment.
7. The integrated chip of claim 4, wherein the well region extends continuously along a floor of the intermediate isolation segment from a sidewall of the first peripheral isolation segment to a sidewall of the second peripheral isolation segment.
8. The integrated chip of claim 4, further comprising:
a first select transistor comprising a source/drain region disposed within the bit line write region and a first select gate electrode comprising a first select gate portion of a select gate, wherein the first select transistor is disposed along the first sidewall of the intermediate isolation segment; and
a second select transistor comprising a source/drain region disposed within the bit line read region and a second select gate electrode comprising a second select gate portion of the select gate, wherein the second select transistor is disposed along the second sidewall of the intermediate isolation segment.
9. A method of forming a memory device, the method comprising:
forming an isolation structure in a substrate, wherein the isolation structure comprises inner sidewalls that define a device region of the substrate;
doping the substrate to form a middle well region within the device region of the substrate;
forming a floating gate over at least a portion of the middle well region and at least a portion of the isolation structure; and
doping the substrate to form a bit line read region within a first portion of the middle well region and a bit line write region within a second portion of the middle well region, wherein the bit line read region includes source/drain regions on opposite sides of the floating gate and the bit line write region includes source/drain regions on the opposite sides of the floating gate, wherein the first portion of the middle well region is laterally offset from the second portion of the middle well region by a non-zero value distance.
10. The method of claim 9, wherein the isolation structure comprises a first peripheral isolation segment, a second peripheral isolation segment, and an intermediate isolation segment disposed between the first peripheral isolation segment and the second peripheral isolation segment, wherein the intermediate isolation segment is laterally disposed between the first portion of the intermediate well region and the second portion of the intermediate well region.
CN202110110471.8A 2020-03-03 2021-01-27 Integrated chip and method of forming memory device Pending CN113421883A (en)

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US11387242B2 (en) * 2020-03-03 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Non-volatile memory (NVM) cell structure to increase reliability
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