CN113419777B

CN113419777B - Instruction block conversion execution method and system of programmable switch

Info

Publication number: CN113419777B
Application number: CN202110500259.2A
Authority: CN
Inventors: 陈晓; 凌致远; 宋磊; 吴京洪
Original assignee: Zhongkehai Suzhou Network Technology Co ltd; Institute of Acoustics CAS
Current assignee: Zhongkehai Suzhou Network Technology Co ltd; Institute of Acoustics CAS
Priority date: 2021-05-08
Filing date: 2021-05-08
Publication date: 2023-07-18
Anticipated expiration: 2041-05-08
Also published as: CN113419777A

Abstract

The present invention relates to the field of communications technologies, and in particular, to a method and a system for executing instruction block conversion of a programmable switch. The method comprises the following steps: converting the instruction block information of the switch into intermediate codes and storing the intermediate codes, wherein the intermediate codes comprise operation codes, operands and field flag bits; taking out the intermediate code, and performing byte order pre-conversion on operands of the intermediate code meeting the pre-conversion requirement; the intermediate code after the byte order pre-conversion or the intermediate code which does not need to be subjected to byte order pre-conversion is interpreted as a CPU instruction and executed. The method can solve the problems of insufficient optimization of para data processing, multiple byte order conversion times, poor multi-platform expansibility and the like when the instruction block is directly interpreted and executed on the general CPU, thereby improving the forwarding efficiency of the programmable switch; the method supports bit processing of data, reduces a large amount of instruction conversion work, and greatly reduces byte order conversion times, thereby improving the overall forwarding performance of the switch.

Description

Instruction block conversion execution method and system of programmable switch

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and a system for executing instruction block conversion of a programmable switch.

Background

With the rapid development of the internet, internet data centers are also rapidly developing. And due to the development of cloud computing, more application processing is concentrated to the cloud, so that the scale of the cloud computing data center is promoted to be rapidly increased. Data center networks face a number of problems, such as centralized and efficient network management requirements, efficient and flexible networking requirements, virtual machine deployment and migration requirements, virtual multi-tenant service support requirements, and comprehensive data center IaaS requirements.

In this regard, the academy proposes the concept of a Software Defined Network (SDN). SDN has characteristics such as forwarding and control separation, control logic centralization, network virtualization, network capability openness. The SDN technology is thus well suited to the above-mentioned needs of data center networks. SDN-based cloud computing data center network schemes are a trend of future data center networks.

OpenFlow is implemented as the most widely-affected and open SDN interface, and aims at a switch with a fixed function, which can only identify a preset header field. To support new protocols, the OpenFlow specification needs to be continually extended. With the increasing of new protocols, the OpenFlow protocol will not be bloated and complicated. To address this problem, benmacackcrane et al propose OF-PI, a protocol independent intermediate layer, which enables a more flexible and programmable forwarding plane. The OF-PI is based on protocol unaware forwarding (POF) and programming protocol-independent message processors (P4). POF provides a set of protocol independent instruction sets as an important component thereof.

The POF technology provided by the hua realizes a basic protocol-agnostic forwarding function through a protocol-independent instruction set, but does not further optimize the storage and execution process of the instruction set. The instruction sets are packaged into functions, when the POF switch receives the data packet, table entry matching is carried out, and the execution of the action instructions is realized by calling the functions. Under this scheme, the storage space and execution speed of instructions are not dominant compared to other OpenFlow switches.

In the field of data plane programming, POF technology is classified into two types, compiled POF technology and interpreted POF technology. The compiling type POF compiles a program written in a high-level language into a binary file which can be identified by a target machine, and the executing speed is high, but the disadvantage is that cross-platform support is insufficient, and different compilers are needed to compile on different platforms; the interpreted POF converts the program of the control plane into an intermediate code, and further into CPU instructions for execution, and the intermediate code solves the problem of cross-platform. Muhammad Shahbaz and back fearster at the university of prinston propose an intermediate representation named NetASM that enables a compiler to optimize packet handlers written in high-level languages for different purposes. However, this approach ignores the optimization process of intermediate code conversion to CPU instruction execution and does not optimize byte order conversion, bit data processing.

In some other fields, interpreted languages have also been used. For example, a team of Zhejiang university proposes a method for interpreting and executing database instructions by using a hardware interpreter to reduce the interpretation cost of database management language. The interpretation of instructions by the programmable switch with respect to the database also takes into account other factors such as the processing of bit data and the conversion of byte order.

In a programmable switch, the interpretation and execution methods of instruction blocks have great influence on the forwarding performance of the switch, and if the instruction blocks are directly interpreted and executed on a general-purpose CPU, some problems occur: in the packet processing scenario, the offset and length of the data are mostly calculated in units of bits, and the general CPU instruction is usually executed in units of bytes, so that a large amount of conversion work is required when processing the packet; the byte sequence of the network data packet is different from the local byte sequence used by the CPU when the CPU processes the data, the byte sequence is required to be converted before each execution of the CPU instruction, and a large amount of operation resources are consumed; different target machine hardware deployed by the soft switch equipment is different, supported instruction sets are not completely consistent, and the instruction execution efficiency on some target machines is lower than the average level.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides an instruction block conversion execution method and system of a programmable switch.

In order to achieve the above object, the present invention provides a method for executing instruction block conversion of a programmable switch, the method comprising:

converting the instruction block information of the switch into intermediate codes and storing the intermediate codes, wherein the intermediate codes comprise operation codes, operands and field flag bits;

taking out the intermediate code, and performing byte order pre-conversion on operands of the intermediate code meeting the pre-conversion requirement;

the intermediate code after the byte order pre-conversion or the intermediate code which does not need to be subjected to byte order pre-conversion is interpreted as a CPU instruction and executed.

As an improvement of the above method, the instruction block message is an isolated instruction or a plurality of instructions related by context, the instructions comprise an instruction type and an instruction operand, and the object pointed by the instruction operand is a constant, a data packet field or a stream table number.

As an improvement of the above method, the instruction block message of the switch is converted into an intermediate code and stored; the method comprises the following steps:

for the isolated instruction, firstly analyzing to obtain the length of instruction operation, then inquiring a pre-established intermediate code execution time table according to the length of an instruction operand, selecting an intermediate code with the least occupied storage space and the shortest execution time for conversion, converting the instruction into a byte processing type intermediate code if the length of the operand is an integer multiple of 8, otherwise converting into a bit processing type intermediate code, and storing the bit processing type intermediate code in a specific storage space;

for the multiple instructions related to the context, firstly analyzing the functions of the instruction block, obtaining a plurality of feasible intermediate code combinations with the same functions according to analysis results, then inquiring a pre-established intermediate code execution schedule, calculating the total execution time of each feasible intermediate code combination, selecting the intermediate code combination with the shortest total execution time as the intermediate code of the instruction block message, and storing the intermediate code combination in a specific storage space.

As an improvement to the above-described method,

the operation code is obtained by converting the type of the instruction and is used for representing the functions of the instruction, including a logic operation instruction, a forwarding instruction, a jump instruction and a flow table instruction;

the operand and the field flag bit are obtained by converting the operand of the instruction; wherein:

the operand is used for representing an operation object of the instruction and consists of an offset address and a length in a specific storage space to which the operation object belongs;

the field flag bit is used for indicating a specific storage space to which an operand belongs, and comprises a data packet area, a data packet metadata area, a network stream metadata area and a global metadata area.

As an improvement of the method, the fetching of the intermediate code performs byte order pre-conversion on the operands of the intermediate code which meet the pre-conversion requirement; the method comprises the following steps: and taking out the intermediate code, and if the operand of the intermediate code is a data packet area, performing byte order pre-conversion on the operand of the intermediate code.

As an improvement of the above method, the intermediate code after the byte order pre-conversion or the intermediate code which does not need to be byte order pre-converted is interpreted as a CPU instruction and executed; the method comprises the following steps:

for byte processing type intermediate codes, acquiring the byte length of an instruction operand;

judging whether the byte length has the corresponding data type, if yes, interpreting the data type as a CPU instruction of the target machine, and executing the CPU instruction; if not, optimizing by using an acceleration instruction set supported by a CPU of the target machine, and executing;

for bit-processing type intermediate code, the acceleration instruction set supported by the target machine CPU is used for optimization and execution.

An instruction block translation execution system of a programmable switch, the system comprising: an intermediate code conversion module, a byte order pre-conversion module and an interpretation execution module, wherein,

the intermediate code conversion module is used for converting the instruction block message of the switch into intermediate codes and storing the intermediate codes, wherein the intermediate codes comprise operation codes, operands and field flag bits;

the byte order pre-conversion module is used for taking out the intermediate codes and performing byte order pre-conversion on operands of the intermediate codes meeting the pre-conversion requirement;

the interpretation and execution module is used for interpreting the intermediate code after the byte order pre-conversion or the intermediate code without the byte order pre-conversion into a CPU instruction and executing the CPU instruction.

Compared with the prior art, the invention has the advantages that:

1. the method can solve the problems of insufficient optimization of para data processing, multiple byte order conversion times, poor multi-platform expansibility and the like when the instruction block is directly interpreted and executed on the general CPU, thereby improving the forwarding efficiency of the programmable switch;

2. the invention provides a method for converting and executing flow table actions of a programmable switch, aiming at the problems that the programmable switch directly executes instruction blocks to consume extra resources when carrying out bit processing on data and the forwarding performance is affected due to excessive byte sequence conversion times when processing data packets;

3. the intermediate code provided by the invention is used as a transition instruction between the instruction block and the target machine CPU instruction, supports bit processing of data, reduces a large amount of instruction conversion work, and greatly reduces byte order conversion times, thereby improving the overall forwarding performance of the switch.

Drawings

Fig. 1 is a step diagram of a method for converting and executing instruction blocks of a programmable switch according to embodiment 1 of the present invention;

FIG. 2 is a detailed step diagram of the method shown in FIG. 1;

fig. 3 is a block diagram of a programmable switch and a conversion and execution flow chart of instruction blocks involved in embodiment 2 of the present invention.

Detailed Description

The invention provides a method for converting and executing instruction blocks of a programmable switch, which aims at solving the problems that when the programmable switch directly interprets the instruction blocks as CPU instructions, complex conversion is needed for bit data processing, the number of times of byte order conversion is too large and the like.

The data plane programming technique enables a new type of forwarding plane technique in a software defined network. In the data plane programming technology, the network behavior is completely defined by the control plane, all message forwarding services are completely controlled by the controller software, and the read-write access to the message data is executed by instructions.

The data plane programming technique may include: compiled and interpreted data plane programming techniques. The method of the embodiment of the invention adopts an interpretation type data plane programming technology. In the explained data plane programming technology, the switch instruction is converted into intermediate code to be stored locally, and then further interpreted into CPU instruction and executed when called. This has the advantage that it is more cross-platform. In the compiling type data plane programming technology, after developing a program in a high-level language, a compiler is required to compile the program into a machine language, namely, a binary file recognized by a computer. Because the binary files identified by different target machines are not identical, the high-level language program needs to be recompiled after being transplanted. While the intermediate code provided by the interpreted data plane programming technique solves the problem that it can be interpreted for execution in switches of different platforms.

The programmable switch in the embodiment of the invention has higher flexibility and programmability than other switches, and the instruction block conversion and execution method of the programmable switch provided by the invention is further described with reference to the drawings and the specific embodiment.

The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples.

Example 1

As shown in fig. 1, embodiment 1 of the present invention provides an instruction block conversion execution method of a programmable switch, which can be applied to a programmable switch device. The embodiment of the invention mainly comprises a method for interpreting the switch instruction into the intermediate code to be stored locally and a method for interpreting the switch process to interpret the intermediate code into the CPU instruction to be executed. The specific process is as follows:

when the programmable switch receives the switch instruction message issued by the controller, analyzing the type of the switch instruction in the message, and then determining the function type of the intermediate code after instruction conversion according to the analysis result.

The programmable switch parses a destination operand and a source operand of the switch instruction. First, it is determined whether the operand is an immediate or a field. If the field is a field, judging whether the offset and the length (in bits) of the field are integer multiples of 8, if so, indicating that the field can be represented by a plurality of complete bytes, and therefore, interpreting the instruction into byte processing intermediate code; if the offset or length of the field is not an integer multiple of 8, it is stated that the field cannot be represented by a number of complete bytes, and complex translation work is required when directly translating the CPU instruction, thus translating the instruction into bit-processing intermediate code.

The programmable switch optimizes when converting instructions or blocks of instructions into intermediate code. For orphaned instructions, the programmable switch parses the length of the instruction operand, which may be the length of the field operand or the length of the immediate operand. The programmable switch divides the instruction into long instructions or short instructions according to the length of the operands and then converts into corresponding long operand intermediate codes or short operand intermediate codes.

For an instruction block formed by a plurality of instructions, the programmable switch analyzes the functions of the instruction block, and various feasible intermediate code combinations with the same functions are obtained according to analysis results; then inquiring the intermediate code execution time table, calculating the total execution time of each feasible combination, and comparing; and finally, selecting the intermediate code combination with the shortest total execution time as a conversion result of the instruction block. Wherein, the execution time table of the intermediate code is pre-established and summarized after the execution time of the intermediate code is tested and verified

The programmable switch stores the converted intermediate code into a specific memory space to wait for calling.

The programmable switch invokes intermediate code to determine whether to perform the byte order conversion based on the source of the intermediate code operand. The source of the intermediate code operand is the unique attribute of the field operand, which indicates which memory area the operand belongs to, and is mainly divided into a data packet area, a data packet metadata area, a network stream metadata area and a global metadata area. If the operation field of the intermediate code comes from the data packet area, byte order conversion is needed before the instruction is executed, and byte order conversion is not needed when the intermediate code of the subsequent operation on the field is executed; if the operation field of the intermediate code is from other metadata areas, no byte order conversion is performed.

The programmable switch interprets the intermediate code into target machine CPU instruction execution. For byte processing intermediate codes, the programmable switch judges the byte length of an operand, and if the byte length of the intermediate codes has corresponding data types which can be directly described, the intermediate codes are directly interpreted as target machine CPU instruction execution; if the byte length of the data type (the data type includes but is not limited to the data type supported by the CPU, such as a structural body, etc.) can be directly described (such as an operand with 3 bytes), the data type needs to be optimized by using an acceleration instruction set supported by the CPU of the target machine when being converted into the CPU instruction of the target machine to execute, so that the execution efficiency is improved.

Fig. 2 is a flow chart of the method of fig. 1 in which the switch instructions are converted to intermediate code and interpreted as CPU instruction execution. Firstly, the programmable switch receives the instruction message issued by the controller, and after analyzing the instruction source code, the programmable switch knows that the instruction is SET_FIELD, and the programmable switch has the function of modifying the source mac address of the data packet into a new value. The instruction interpreter of the programmable switch starts to interpret the instruction block as an intermediate code, firstly, according to the function of SET_FIELD, the type of the intermediate code is determined to be a logic operation instruction, and sf and sfd are arranged corresponding to optional intermediate code instructions; then judging the attributes of the operands, namely 48-bit long data of the source operands, 0 of the offset of the destination operation field and 48 bits of length, wherein the attributes can be divided by 8, so that the instruction is interpreted as byte processing intermediate codes; since the length of the operand is 48 bits, and only instructions with the operand length not exceeding 32 bits belong to short instructions, the instruction can only be interpreted as long operand intermediate codes; the intermediate code is then stored locally. After the POF exchanger receives the data packet, the data packet queries the flow table and matches the table entry, the instruction block in the table entry is executed, and the POF exchanger calls the intermediate code stored locally in the steps to execute. Since the destination operation field is derived from the byte processing intermediate code, it is determined whether the operation field can be directly represented by the data type supported by the target machine, and the 48-bit data is not represented by the corresponding data type, so that the operation field needs to be executed by an acceleration instruction set supported by the target machine CPU (such as an SSE of x86, an AVX instruction set, or a NEON instruction set of ARM, etc.) to improve efficiency.

Example 2

Embodiment 2 of the present invention provides an instruction block conversion execution system of a programmable switch. The system comprises: an intermediate code conversion module, a byte order pre-conversion module and an interpretation execution module, wherein,

Referring to fig. 3, a block diagram of a programmable switch and a conversion and execution flow chart of instruction blocks are shown, and a specific processing method is the same as that of embodiment 1.

Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention and are not limiting. Although the present invention has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the appended claims.

Claims

1. A method of instruction block conversion execution for a programmable switch, the method comprising:

interpreting the intermediate code after byte order pre-conversion or the intermediate code without byte order pre-conversion into a CPU instruction and executing the CPU instruction;

the instruction block information of the switch is converted into intermediate codes and stored, and the instruction block information is an isolated instruction or a plurality of instructions related to the context; the method comprises the following steps:

2. The method of claim 1, wherein the instruction includes an instruction type and an instruction operand, the instruction operand referring to an object that is a constant, a packet field, or a flow table number.

3. The method of claim 2, wherein the instruction block conversion execution method of the programmable switch,

4. The method according to claim 3, wherein the fetching of intermediate codes performs byte order pre-conversion on operands of the intermediate codes that meet pre-conversion requirements; the method comprises the following steps: and taking out the intermediate code, and if the operand of the intermediate code is a data packet area, performing byte order pre-conversion on the operand of the intermediate code.

5. The method according to claim 4, wherein the intermediate code after the byte order pre-conversion or the intermediate code without byte order pre-conversion is interpreted as a CPU instruction and executed; the method comprises the following steps:

6. An instruction block translation execution system of a programmable switch, the system comprising: an intermediate code conversion module, a byte order pre-conversion module and an interpretation execution module, wherein,

the intermediate code conversion module is used for converting the instruction block information of the switch into intermediate codes and storing the intermediate codes, wherein the instruction block information is an isolated instruction or a plurality of instructions related to the context, and the intermediate codes comprise operation codes, operands and field flag bits;

the interpretation and execution module is used for interpreting the intermediate code after the byte order pre-conversion or the intermediate code without the byte order pre-conversion into a CPU instruction and executing the CPU instruction;

the processing procedure of the intermediate code conversion module is specifically as follows: