CN113410275A

CN113410275A - Display panel and display device

Info

Publication number: CN113410275A
Application number: CN202110668436.8A
Authority: CN
Inventors: 董向丹; 王蓉; 田东辉; 何帆
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-06-16
Filing date: 2021-06-16
Publication date: 2021-09-17

Abstract

The application discloses display panel and display device, wherein, a display panel, including display area and non-display area, the display area includes central display area and is located the fillet display area of the regional four corners position department of display still includes the gate drive circuit unit group, the gate drive circuit unit group is including being located the first gate drive circuit unit subgroup in non-display area and the second gate drive circuit unit subgroup that is located the display area, first gate drive circuit unit subgroup with second gate drive circuit unit subgroup electricity is connected. The display panel that this application embodiment provided places gate drive circuit subregion, places the gate drive circuit that the fillet district corresponds vertically in the display area, and the gate drive circuit of all the other vertical position still conventionally places in the vertical edge frame department in non-display area, realizes the function of buckling of four sides wide-angle, can improve the module and laminate the fold problem, promotes the product yield.

Description

Display panel and display device

Technical Field

The present application relates generally to the field of display technologies, and in particular, to a display panel and a display device.

Background

The AMOLED (Active-matrix organic light-emitting diode) has the advantages of self-luminescence, wide color gamut, high contrast, flexibility, high response, flexibility and the like, and has wide application prospect. Along with AMOLED display device's high-speed development, the customer also more and more high to whole machine effect and display effect requirement, so super narrow frame concept is proposed, and super narrow fillet firstly can realize the four sides wide-angle function of buckling, secondly can improve the module and laminate the fold problem, promotes the product yield, and this also proposes stricter requirement to Panel design.

Stress concentration when the reducible Panel four sides of narrow frame of super narrow fillet department are buckled promotes the crooked product yield of four sides, because of the restriction of characteristics such as the easy absorption of water of OLED product organic film layer, the encapsulation that certain area need be guaranteed in super narrow fillet department of product is protected, GOA (Gate Driver on Array, Array substrate line drive) technique is the most commonly used grid drive circuit technique in the display Panel at present, for reducing super narrow fillet department frame, Gate drive circuit can't be put again to fillet department frame.

Disclosure of Invention

In view of the above-mentioned drawbacks and deficiencies of the prior art, it is desirable to provide a display panel and a display device, which can achieve GOA partition placement of ultra-narrow rounded corners of an OLED display panel.

The display panel comprises a display area and a non-display area, wherein the display area comprises a central display area and fillet display areas positioned at four corners of the display area, the display area further comprises a grid driving circuit unit group, the grid driving circuit unit group comprises a first grid driving circuit unit subgroup positioned in the non-display area and a second grid driving circuit unit subgroup positioned in the display area, and the first grid driving circuit unit subgroup and the second grid driving circuit unit subgroup are electrically connected.

Further, the pixel units of the display area comprise pixel rows arranged in a first direction x and pixel columns arranged in a second direction, and the gate driving circuit unit group is used for driving the pixel rows.

Further, the pixel row and the pixel column include a plurality of sub-pixels, each of the sub-pixels includes a driving circuit unit pixel circuit unit and a light emitting element, the pixel row further includes a signal line connected to the driving circuit unit pixel circuit unit of each sub-pixel in the pixel row, and the gate driving circuit unit group is connected to a corresponding signal line to supply a driving signal to each of the sub-pixels.

Furthermore, the number of the second gate driving circuit unit subgroups is two, and the two second gate driving circuit unit subgroups are respectively located at two ends of the first gate driving circuit unit subgroup in the second direction, and one second gate driving circuit unit subgroup is located in one fillet display area at the same side as the position of the first gate driving circuit unit subgroup.

Furthermore, the central display area includes a first sub-display area and second sub-display areas respectively located at two sides of the first sub-display area, the first gate driving circuit unit subgroup drives pixel rows in the first sub-display area, and the second gate driving circuit unit subgroup drives pixel rows in the second sub-display area at corresponding positions and pixel rows in two of the corner areas at corresponding positions.

Further, the fillet display area provided with the second gate driving circuit unit subgroup comprises a compression area, a first adjacent area adjacent to the first sub display area and a second adjacent area adjacent to the second sub display area, and the density of the pixel circuit units in the compression area is greater than that of the pixel circuit units in the fillet display area not provided with the second gate driving circuit unit subgroup.

Furthermore, the compression region is used for arranging all the pixel circuit units of the sub-pixels in the fillet display region, the pixel circuit units are not arranged in the first and second adjacent regions, and the first adjacent region is used for arranging the second gate drive circuit unit subgroup.

Further, the first border area is used for arranging a first routing between the first gate driving circuit unit subgroup and the second gate driving circuit unit subgroup and a second routing between the pixel column in the fillet display area and the pixel column in the first sub-display area, and the second routing is a data signal routing.

Further, the second border area is further configured to set a third trace between the second gate driving circuit unit subgroup and the pixel row in the fillet display area, and a fourth trace between the second gate driving circuit unit subgroup and the pixel row in the second sub-display area.

Further, the light emitting elements of the sub-pixels in the rounded corner display area are uniformly arranged, and the density of the light emitting elements in the rounded corner display area provided with the second gate driving circuit unit subgroup is the same as the density of the light emitting elements in the display area not provided with the second gate driving circuit unit subgroup.

Furthermore, each pixel circuit unit in the compression area is electrically connected with the corresponding light-emitting element in the fillet display area through a fifth wire and a via hole, and the fifth wire is an ITO wire.

In a second aspect, the present application proposes a display device comprising a display panel as described in any of the above.

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

the display panel provided by the embodiment of the application places the gate drive circuit units in a partition manner, vertically places the gate drive circuit units corresponding to the fillet area in the display area, and still conventionally places the gate drive circuit units at the rest vertical positions in the vertical frame of the non-display area, so that the four-side large-angle bending function is realized, the problem of module attaching folds can be improved, and the product yield is improved.

Drawings

The features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments thereof, made with reference to the following drawings:

fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a rounded corner display area provided in an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a location of a display area division according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a shift register circuit according to an embodiment of the present application;

fig. 5 is a schematic connection diagram of traces in a display panel according to an embodiment of the present disclosure;

FIG. 6 is an enlarged schematic view of a first bordered area provided by an embodiment of the present application;

FIG. 7 is an enlarged schematic view of a second bordered area provided by an embodiment of the present application;

fig. 8 is a schematic layout diagram of a sub-pixel provided in an embodiment of the present application;

fig. 9 is a schematic arrangement diagram of a light emitting element provided in an embodiment of the present application;

100. a first GOA unit subgroup; 200. a pixel circuit unit; 300. a light emitting element; 410. a first wire; 420. a second routing; 430. a third wire routing; 440. a fourth wire; 500. a second subset of GOA cells.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

Referring to fig. 1-2 in detail, a display panel includes a display region and a non-display region, the display region includes a central display region D and rounded corner display regions Y located at four corners of the display region, and further includes a gate driving circuit unit group, the gate driving circuit unit group includes a first gate driving circuit unit subgroup 100 located in the non-display region and a second gate driving circuit unit subgroup 500 located in the display region, and the first gate driving circuit unit subgroup 100 is electrically connected to the second gate driving circuit unit subgroup 500.

In the embodiment of the present invention, the display panel is a special-shaped display panel, that is, the display area of the display panel is designed to be a shape other than a regular rectangle. The specific shape of the display area is not limited. The edges of the display area have rounded corners. In other embodiments of the present invention, the edge of the display region may have at least one of a chamfer, a notch, a cut, or a curved edge. The rounded display area Y in the embodiment of the present application does not limit the specific shape of the display area.

In the embodiment of the invention, the specific shape of the non-display area is not limited, and can be matched with the shape of the display area, the display area is provided with a round angle, and the non-display area is also provided with a round angle at the corresponding part; in addition, the shape of the non-display area may not match the shape of the display area, for example, the display area has a gap, and the non-display area has a regular continuous rectangular shape.

The pixel units of the display area comprise pixel rows arranged in a first direction x and pixel columns arranged in a second direction y, and the grid drive circuit unit group is used for driving the pixel rows. The pixel row and the pixel column include a plurality of sub-pixels, each of which includes a pixel circuit unit 200 and a light emitting element 300, the pixel row further includes a signal line connected to the pixel circuit unit 200 of each sub-pixel in the pixel row, and the gate driving circuit unit group is connected to the corresponding signal line to supply a driving signal to each of the sub-pixels.

In the embodiment of the present application, the row direction and the column direction may be perpendicular to each other, or may be close to perpendicular, and the present application does not limit the specific directions of the row direction and the column direction. Of course, in other embodiments, the first direction x and the second direction y may be interchanged, the first direction x may be a column direction in which all pixel units are arranged, and the second direction y may be a row direction in which all pixel units are arranged.

Illustratively, the number of the second gate driving circuit unit subgroups 500 is two, and the two second gate driving circuit unit subgroups 500 are respectively located at two ends of the first gate driving circuit unit subgroup 100 in the second direction Y, and one second gate driving circuit unit subgroup 500 is located in one rounded corner display region Y on the same side as the first gate driving circuit unit subgroup 100.

In the embodiment of the present application, the gate driving circuit unit groups at two ends of the gate driving circuit unit group driving the pixel rows at the ultra-narrow corners are disposed in the display area, and the gate driving circuit unit groups corresponding to the pixel rows at the non-ultra-narrow corners in the display area are disposed at the vertical frame positions in the non-display area according to the arrangement manner in the prior art.

It should be noted that, the number of the gate driving circuit unit groups is not limited in the present application, in some embodiments, two gate driving circuit unit groups may be respectively located in the non-display regions on the left and right sides of the display region, and the two gate driving circuit unit groups may simultaneously or alternately provide the control signals for the row pixels.

In the field of display technology, the light emitting elements 300 in the same row are controlled by the driving signal lines in the same row, and the light emitting elements 300 in the same column are controlled by the data signal lines in the same column. And, the driving signal line and the data signal line each include a signal line main body portion for being connected to the corresponding control unit, respectively, and a signal line extension portion for being connected to the corresponding pixel circuit, respectively, to transmit the corresponding control signal to the corresponding sub-pixel.

As shown in fig. 1, the central display region D includes a first sub-display region D1 and second sub-display regions D2 respectively located at two sides of the first sub-display region D1, the first gate driving circuit unit subgroup 100 drives a pixel row in the first sub-display region D1, and the second gate driving circuit unit subgroup 500 drives a pixel row in the second sub-display region D2 at a corresponding position and a pixel row in two of the corner regions at corresponding positions.

On the display panel, four fillet display areas Y are included altogether, first fillet display area Y1, second fillet display area Y2 on first fillet display area Y1 along first direction x, third fillet display area Y3 on first fillet display area Y1 along second direction Y, fourth fillet display area Y4 in first fillet display area Y1 diagonal direction. The first rounded corner display area Y1 and the third rounded corner display area Y3 are respectively located at two ends of the gate driving circuit unit group.

As shown in fig. 3, the second sub display region D2 includes a second upper display region D01 and a second lower display region D02, the second upper display region D01 is located between the first rounded corner display region Y1 and the second rounded corner display region Y2, and the second lower display region D02 is located between the third rounded corner display region Y3 and the fourth rounded corner display region Y4.

Correspondingly, the second gate driving circuit unit subgroup 500 is arranged to include a second upper gate driving circuit unit group 510 and a second lower gate driving circuit unit group 520, wherein the second upper gate driving circuit unit group 510 is located in the first rounded corner display area Y1 and is used for driving pixel rows in the first rounded corner display area Y1, the second upper display area D01 and the second rounded corner display area Y2; the second lower gate driving circuit unit group 520 is located in the third rounded corner display area Y3 and is used to drive the pixel rows in the third rounded corner display area Y3, the second lower display area D02 and the fourth rounded corner display area Y4.

In the embodiment of the present application, the pixel circuit unit may be a specific pixel driving circuit such as 2T1C, 3T1C, 6T1C, 7T1C, and the like. The GOA (Gate Driver on Array) technology is a Gate driving circuit technology that is most commonly used in the display panel at present, and the Gate driving circuit is directly integrated on the Array substrate of the display panel through a photolithography process. In the embodiment of the present application, a preparation method of the gate driving circuit may adopt a scheme in the prior art, and details of the preparation method are not repeated herein.

In the display process, grid scanning signals are output through a grid driving circuit, each pixel unit is scanned and accessed line by line (or line by line or in other preset modes), the grid driving circuit is used for generating the grid scanning signals of the pixel units, each grid driving circuit unit serves as a shifting register to sequentially transmit the grid scanning signals to the next grid driving circuit unit, and TFT switches are turned on line by line to complete data signal input of the pixel units.

As shown in fig. 4, a shift register circuit includes a first INPUT terminal INPUT1, a second INPUT terminal INPUT2, a gate output terminal GOUT, an enable output terminal EOUT, a first signal terminal GCK, a second signal terminal GCB, a third signal terminal ECK, a fourth signal terminal ECB, a first power source terminal VGH, and a second power source terminal VGL. The first signal terminal GCK, the second signal terminal GCB, the third signal terminal ECK, and the fourth signal terminal ECB of the shift register circuit are respectively connected to the first clock signal line GCK, the second clock signal line GCB, the third clock signal line ECK, and the fourth clock signal line ECB in sequence. The first power supply terminal VGH and the second power supply terminal VGL of the shift register circuit are sequentially connected to the first power supply line VGH and the second power supply line VGL, respectively.

In the first direction x, in two adjacent sub-display regions, the pixel circuit units 200 of the pixel rows in the first rounded corner display region Y1 are arranged in a staggered manner with the pixel circuit units 200 of the pixel rows in the second upper display region D01; in the second direction Y, the pixel circuit units 200 of the pixel columns in the two adjacent sub-display regions, that is, the rounded corner display region Y, are arranged in a staggered manner from the pixel circuit units 200 of the pixel columns in the first sub-display region D1.

The rounded display area Y in which the second gate driving circuit cell subgroup 500 is disposed (i.e., the first rounded display area Y1 and the third rounded display area Y3 in the embodiment of the present application) includes a compression area PT, a first neighboring area P1 adjacent to the first sub-display area D1, and a second neighboring area P2 adjacent to the second sub-display area D2, the compression area PT is used for disposing all the pixel circuit cells 200 of the sub-pixels in the rounded display area Y, the pixel circuit cells 200 are not disposed in the first neighboring area P1 and the second neighboring area P2, and the first neighboring area P1 is used for disposing the second gate driving circuit cell subgroup 500.

As shown in fig. 5, in the embodiment of the present application, the density of the pixel circuit units 200 in the compression region PT where the second GOA cell subgroup 500 is disposed is greater than the density of the pixel circuit units 200 in the display region where the second GOA cell subgroup 500 is not disposed. In the embodiment of the present application, the density of the pixel circuit units 200 in the first rounded corner display area Y1 and the third rounded corner display area Y3 is the same, the density of the pixel circuit units 200 in the second rounded corner display area Y2 and the fourth rounded corner display area Y4 is the same as the density of the driving units in the first sub-display area D1 and the second sub-display area D2, and the density of the pixel circuit units in the first rounded corner display area Y1 is greater than the density in the second rounded corner display area Y2.

In the present embodiment, the term "density" refers to the number of components per unit area, the density of the driver circuit unit refers to the number of pixel circuit units provided per unit area, and the density of the light-emitting elements refers to the number of light-emitting elements provided per unit area. When the density of the components in different areas is controlled, the center distance between the components can be controlled, or the sizes of the components can be changed. It is within the scope of the present application to achieve density adjustment in either manner.

The density value reflects the number of components in a unit area or the size of the area space occupied by each component. The density of the pixel circuit cells in the first rounded display area Y1 is greater than the density in the second rounded display area Y2, which can be expressed as the center-to-center distance between the pixel circuit cells in the first rounded display area Y1 is less than the center-to-center distance between the pixel circuit cells in the second rounded display area Y2; it can also be expressed that the distribution area of the pixel circuit cells within the first rounded display area Y1 is smaller than the distribution area of the pixel circuit cells within the second rounded display area Y2.

As shown in fig. 6, the first border area P1 is used to arrange a first trace 410 between the first gate driving circuit unit subgroup 100 and the second gate driving circuit unit subgroup 500, and a second trace 420 between the pixel column in the circular corner display area Y and the pixel column in the first sub-display area D1, where the second trace 420 is a data signal trace.

It should be noted that the first traces 410 include connecting traces between the gate driving circuits, such as GCK, GCB, ECK, ECB, GCK, GCB, ECK, ECB signal lines, etc., and the second traces 420 extend along the second direction Y, i.e. the direction of the pixel columns, for transmitting the data signals to the corresponding pixel columns of the first rounded corner display area Y1 through the pixel columns of the first sub-display area D1, or for transmitting the data signals to the corresponding pixel columns of the first sub-display area D1 through the pixel columns of the third rounded corner display area Y3.

It should be noted that, in order to reduce the occupied area of the traces, the first trace 410 may be implemented by a layer-skipping trace, and the first trace 410 may be distributed in one layer, two layers, or multiple layers. Alternatively, in some embodiments, the first trace 410 and the second trace 420 may be arranged in layers to save trace area. Specifically, the first trace 410 may be located above the second trace 420 or the first trace 410 may be located below the second trace 420. The invention is not limited to the embodiments, and any embodiment that can achieve the gist of the invention is within the scope of the invention.

The embodiment of the application shows an exemplary structure of a thin film transistor TFT adopted by a pixel circuit unit, which includes an active layer Act, a first Gate insulating layer GI1, a first Gate metal layer Gate1, a second Gate insulating layer GI2, a second Gate metal layer Gate2, an interlayer dielectric layer ILD, a first source-drain metal layer SD1, a first planarization layer PLN1, a second source-drain metal layer SD2, and a second planarization layer PLN2, which are sequentially arranged along a direction away from a substrate. It should be noted that other embodiments of the pixel circuit unit that meet the spirit of the present invention are within the scope of the present invention, and are not described herein again.

In a specific arrangement, the first source-drain metal layer SD1 forms the second trace 420 through a patterning process. The second source-drain metal layer SD2 forms the first traces 410 through a patterning process.

In the field of display technology, the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, ink-jetting, etc.; the photolithography process refers to a process of forming a pattern by using a photoresist, a mask plate, an exposure machine, and the like, including processes of film formation, exposure, development, and the like. The corresponding patterning process may be selected according to the structure formed in the present invention.

As shown in fig. 7, the second border region P2 is further configured to dispose a third trace 430 between the second upper gate driving circuit unit group 510 and the pixel row in the rounded corner display region Y, and a fourth trace 440 between the second upper gate driving circuit unit group 510 and the pixel row in the second sub-display region D2.

It should be noted that the third trace 430 extends along the first direction x, i.e. the direction of the pixel row, and is used for transmitting the scanning driving signal of the second upper gate driving circuit unit group 510 to the corresponding pixel row in the first rounded corner display area Y1, and the third trace 430 is connected to the signal line main body portion of the corresponding pixel row in the first rounded corner display area Y1. The fourth routing line 440 extends along the first direction x, i.e., the direction of the pixel row, and is used for transmitting the scanning driving signal of the second upper gate driving circuit unit group 510 to the pixel rows in the second upper display area D01 and the second circular bead display area Y2, and the fourth routing line 440 is connected to the signal line main body portions of the corresponding pixel rows in the first sub-display area D1 and the second circular bead display area Y2.

It is to be noted that the gate driving circuit unit group is not disposed in the second rounded display region Y2, and thus, the pixel circuit units 200 and the light emitting elements 300 in the second rounded display region Y2 are disposed in the same manner as the pixel units in the related art, and thus, the pixel rows in the second upper display region D01 and the second rounded display region Y2 share the same driving signal line.

The light emitting elements 300 of the sub-pixels in the rounded corner display area Y are uniformly arranged, and the density of the light emitting elements 300 in the rounded corner display area Y provided with the second gate driving circuit unit subgroup 500 is the same as the density of the light emitting elements 300 in the display area without the second gate driving circuit unit subgroup 500, that is, the density of the light emitting elements 300 in each rounded corner display area Y and each sub-display area is the same, as shown in fig. 8.

In the first direction x, the light emitting elements 300 of the pixel rows in two adjacent sub-display regions, i.e., the rounded corner display region Y, are aligned with the light emitting elements 300 of the pixel rows in the second upper display region D01; in the second direction Y, the light emitting elements 300 of the pixel columns in the two adjacent sub-display regions, i.e., the rounded corner display region Y, are aligned with the light emitting elements 300 of the pixel columns in the first sub-display region D1.

Note that in the present embodiment, the density of light emitting elements refers to the number of light emitting elements per unit area; the density of the light emitting elements in each region is the same, and the distance between the center of the light emitting element and the center of the light emitting element in each region can be regarded as the same.

The light emitting element 300 generally comprises: the light emitting device comprises an anode layer, a pixel definition layer arranged on the anode, a plurality of light emitting units formed in a pixel area defined by the pixel definition layer, and a cathode layer covering the light emitting units. The light emitting unit may be a red sub-light emitting unit or a green sub-light emitting unit or a blue sub-light emitting unit. The luminescent material of the luminescent unit can adopt organic luminescent material or quantum dot organic luminescent material. The arrangement of the light emitting device 300 can refer to the prior art, and is not described herein.

In the embodiment of the present application, the structure of each light emitting element 300 is not limited, and in some embodiments, the sub-pixel may be a single light emitting element 300 with a single color, or may be a plurality of light emitting elements 300 with the same color, the plurality of light emitting elements 300 may be connected to each other, or the plurality of light emitting elements 300 may be separated from each other. In addition, the shape of the light emitting area of the light emitting element 300 is not limited in the present application, and the sub-pixel units may be triangular, circular, fan-shaped, oval, rectangular with rounded corners, polygonal, and the like.

Each pixel circuit unit 200 in the compression region PT is electrically connected to the corresponding light emitting element 300 in the fillet display region Y through a fifth wire (not shown in the figure) and a via hole, where the fifth wire may be made of ITO (indium tin oxide).

It should be noted that, in the present embodiment, as shown in fig. 9, the light emitting elements 300 and the pixel circuit units 200 in the rounded corner display area Y are physically separated, the pixel circuit units 200 are disposed in the compression area PT, and the light emitting elements 300 are still uniformly distributed in the rounded corner display area Y according to the arrangement in the prior art. The light emitting device 300 and the pixel circuit unit 200 are connected by a connecting trace, and the pixel circuit unit 200 drives the light emitting device 300 to emit light through the connecting trace. The material for forming the connection trace may include an ITO (Indium Tin Oxide) transparent conductive material. The transparent wire can improve the light transmittance of the display area. In order to reduce the occupied area of the routing, the fifth routing can be realized by a layer-skipping routing mode, and the fifth routing can be distributed on one layer, two layers or multiple layers.

In the embodiment of the application, through in compression area PT, carry out the differentiation setting with other pixel drive circuit in pixel drive circuit and the whole display panel, on guaranteeing the normal basis of the demonstration function in the fillet display area Y, compression pixel drive circuit's area occupied places for the grid drive circuit unit group provides the guarantee in the display area.

In the embodiment of the present application, the light emitting elements 300 and the anode metal corresponding to the driving circuit are both normally arranged and not compressed, so as to ensure a normal image display function, and simultaneously improve the transmittance of the display area of the AMOLED display panel to the maximum extent, thereby improving the display quality of the display panel.

The application of the display device is not particularly limited, and the display device can be any product or component with a display function, such as a television, a notebook computer, a tablet computer, a wearable display device, a mobile phone, a vehicle-mounted display, a navigation, an electronic book, a digital photo frame, an advertising lamp box and the like.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, as used herein, refer to an orientation or positional relationship indicated in the drawings that is solely for the purpose of facilitating the description and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and is therefore not to be construed as limiting the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Terms such as "disposed" and the like, as used herein, may refer to one element being directly attached to another element or one element being attached to another element through intervening elements. Features described herein in one embodiment may be applied to another embodiment, either alone or in combination with the features, unless the feature is not applicable or otherwise stated in the other embodiment.

The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the scope of the described embodiments. It will be appreciated by those skilled in the art that many variations and modifications may be made to the teachings of the invention, which fall within the scope of the invention as claimed.

Claims

1. The display panel is characterized by comprising a display area and a non-display area, wherein the display area comprises a central display area and fillet display areas positioned at four corners of the display area, the display panel further comprises a gate driving circuit unit group, the gate driving circuit unit group comprises a first gate driving circuit unit subgroup positioned in the non-display area and a second gate driving circuit unit subgroup positioned in the display area, and the first gate driving circuit unit subgroup and the second gate driving circuit unit subgroup are electrically connected.

2. The display panel according to claim 1, wherein the pixel units of the display region include pixel rows arranged in a first direction and pixel columns arranged in a second direction, and the gate driver circuit unit group is configured to drive the pixel rows.

3. The display panel according to claim 2, wherein the pixel row and the pixel column include a plurality of sub-pixels, each of the sub-pixels includes a pixel circuit unit and a light emitting element, the pixel row further includes a signal line connected to the pixel circuit unit of each of the sub-pixels in the pixel row, and the gate driver circuit unit group is connected to a corresponding signal line to supply a drive signal to each of the sub-pixels.

4. The display panel according to claim 3, wherein the number of the second gate driving circuit unit subgroups is two, and the two second gate driving circuit unit subgroups are respectively located at two ends of the first gate driving circuit unit subgroup in the second direction, and one second gate driving circuit unit subgroup is located in one rounded corner display region on the same side as the first gate driving circuit unit subgroup.

5. The display panel according to claim 3, wherein the central display region comprises a first sub-display region and second sub-display regions respectively located at two sides of the first sub-display region, the first sub-group of gate driving circuit units drives the pixel rows in the first sub-display region, and the second sub-group of gate driving circuit units drives the pixel rows in the second sub-display region at the corresponding positions and the pixel rows in the two rounded regions at the corresponding positions.

6. The display panel according to claim 5, wherein the rounded display regions where the second subset of gate driving circuit cells are disposed comprise a compressed region, a first bordering region adjacent to the first sub-display region, and a second bordering region adjacent to the second sub-display region, and a density of pixel circuit cells in the compressed region is greater than a density of pixel circuit cells in the rounded display regions where the second subset of gate driving circuit cells are not disposed.

7. The display panel of claim 6, wherein the compression region is used to set all of the pixel circuit units of each sub-pixel in the rounded corner display region, and none of the pixel circuit units are set in the first and second neighboring regions, and the first neighboring region is used to set the second subset of gate driving circuit units.

8. The display panel according to claim 7, wherein the first border area is used for disposing a first trace between a first gate driving circuit unit subgroup and a second gate driving circuit unit subgroup, and a second trace between a pixel column in the circular corner display area and a pixel column in the first sub-display area, and the second trace is a data signal trace.

9. The display panel according to claim 7, wherein the second border region is further configured to dispose a third trace between the second subset of gate driving circuit units and the pixel row in the corner display region, and a fourth trace between the second subset of gate driving circuit units and the pixel row in the second sub-display region.

10. The display panel according to claim 7, wherein the light emitting elements of the sub-pixels in the rounded display regions are uniformly arranged, and the density of the light emitting elements in the rounded display regions provided with the second gate driver circuit unit subgroup is the same as the density of the light emitting elements in the display regions not provided with the second gate driver circuit unit subgroup.

11. The display panel according to claim 10, wherein each pixel circuit unit in the compression region is electrically connected to the corresponding light emitting element in the fillet display region through a fifth trace and a via.

12. A display device comprising the display panel according to any one of claims 1 to 11.