CN113394838B

CN113394838B - Terminal device and charging circuit

Info

Publication number: CN113394838B
Application number: CN202110498452.7A
Authority: CN
Inventors: 王方哲; 童尉
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2021-05-08
Filing date: 2021-05-08
Publication date: 2022-04-22
Anticipated expiration: 2041-05-08
Also published as: CN113394838A

Abstract

The embodiment of the application provides terminal equipment and a charging circuit, and relates to the technical field of terminals. The reason that the terminal equipment cannot be normally charged is found in the embodiment of the application: when a charger chip of the terminal equipment returns data to the SOC of the terminal equipment through an I2C bus, clutter interference exists, the SOC obtains wrong charging conditions, and the wrong control terminal equipment does not perform charging. Therefore, in the embodiment of the application, the filter circuit is connected to the I2C path of the charge chip and the SOC, and the noise generated by the charge chip in the serial data line of the I2C bus is filtered by the filter circuit, so that the phenomenon that the terminal equipment cannot be normally charged due to noise interference can be effectively improved.

Description

Terminal device and charging circuit

Technical Field

The embodiment of the application relates to the technical field of terminals, in particular to a terminal device and a charging circuit.

Background

With the development of terminal technology, terminal devices are increasingly used. The terminal device is typically configured with a battery, and power is provided to the terminal device based on the battery to maintain operation of the terminal device. When the battery is low in power, the terminal device can charge the battery based on wireless charging or wired charging.

In a wireless charging or wired charging scenario, a charging abnormality may occur, for example, after a battery is connected to a charging device, the battery cannot be charged normally. Among the possible processes, if the battery cannot be normally charged, the process is performed by replacing the battery or replacing the charging interface.

However, after the battery and the charging interface are replaced, the battery and the charging interface still cannot be charged normally, and a user can only abandon the terminal equipment, so that resource waste is caused.

Disclosure of Invention

The embodiment of the application provides a terminal device and a charging circuit, so that the phenomenon that the terminal device cannot be normally charged due to clutter interference is effectively improved.

In a first aspect, an embodiment of the present application provides a terminal device, including: the system comprises a charger charge chip, a system-on-chip SOC, a filter circuit, a battery, a power management unit, a voltage stabilizer and an amplifier.

A filter circuit is arranged on a bus path of an internal integrated circuit I2C between the charge chip and the SOC. The charger chip is used for receiving charging input from a power supply, charging the battery, receiving discharging of the battery and providing power for a power consumption device of the terminal equipment. And the filter circuit is used for filtering noise generated in the serial data line in the I2C bus by the charge chip. And the SOC is used for obtaining the charging condition of the battery from the charger chip and controlling the battery to be charged or stop charging according to the charging condition. And the power supply management unit is used for receiving the input of the battery and/or the charger chip and managing the state of the battery. And the voltage stabilizer is used for stabilizing voltage when power is supplied to the power consumption device of the terminal equipment. An amplifier for amplifying power when supplying power to a power consuming device of the terminal device. The filter circuit comprises a resistor and a capacitor, one end of the resistor is connected with an interface used for transmitting the SDA signal in the charge chip, and the other end of the resistor is connected with an interface used for transmitting the SDA signal in the SOC; one end of the capacitor is connected with an interface used for SDA signal transmission in the SOC, and the other end of the capacitor is grounded; the resistance value of the resistor is any value from 0 omega to 300 omega, and the value of the capacitor is any value from 0pF to 400 pF.

The reason that the terminal equipment cannot be normally charged is found in the embodiment of the application: when a charger (charger) chip of a terminal device returns data to a System On Chip (SOC) of the terminal device through an inter-integrated circuit (I2C or IIC) bus, noise interference exists, so that the SOC obtains an erroneous charging condition, and the erroneous control terminal device does not perform charging. According to the embodiment of the application, the filter circuit is connected to the I2C path of the charge chip and the SOC, and the clutter generated by the charge chip in the serial data line of the I2C bus is filtered by the filter circuit, so that the phenomenon that the terminal equipment cannot be normally charged due to clutter interference can be effectively improved.

In one possible design, the resistor has a value of 47 Ω and the capacitor has a value of 56 pF. Therefore, the condition that the terminal equipment cannot be normal can be effectively improved, and the work of the I2C bus can be ensured.

In one possible design, the SOC is specifically configured to obtain a charging condition of the battery from the charger chip, and when the charging condition is that the electric quantity is fully charged, the SOC writes a command for instructing to stop charging in a register of the charger chip; and the charge chip is also used for stopping charging the battery when a command for instructing the stop of charging is written in a register for determining the charge chip. Thus, the SOC can control the charge chip to stop charging.

In one possible design, the SOC is specifically configured to obtain a charging condition of the battery from the charger chip, and when the charging condition is that the electric quantity is not fully charged, the SOC writes a command for instructing charging in a register of the charger chip; and the charge chip is also used for charging the battery when the instruction for instructing the charging is written in the register of the charge chip. In this way, the SOC can control the charger chip to charge the battery.

In one possible design, the terminal device is charged using a fast charge protocol FCP9V buck circuit mode.

In a second aspect, an embodiment of the present application provides a charging circuit, including: charger charge chip, system level chip SOC, filter circuit and battery.

A filter circuit is arranged on an internal integrated circuit I2C bus path between the charge chip and the SOC; the charging chip is used for receiving charging input from a power supply, charging the battery, receiving discharging of the battery and providing power for a power consumption device of the terminal equipment; the filter circuit is used for filtering clutter generated in a serial data line in an I2C bus by a charge chip; the SOC is used for obtaining the charging condition of the battery from the charger chip and controlling the battery to be charged or stop charging according to the charging condition; the filter circuit comprises a resistor and a capacitor; one end of the resistor is connected with an interface used for transmitting the SDA signal in the charge chip, and the other end of the resistor is connected with an interface used for transmitting the SDA signal in the SOC; one end of the capacitor is connected with an interface used for SDA signal transmission in the SOC, and the other end of the capacitor is grounded; the resistance value of the resistor is any value from 0 omega to 300 omega, and the value of the capacitor is any value from 0pF to 400 pF.

In one possible design, the resistor has a value of 47 Ω and the capacitor has a value of 56 pF.

In one possible design, the SOC is specifically configured to obtain a charging condition of the battery from the charger chip, and when the charging condition is that the electric quantity is fully charged, the SOC writes a command for instructing to stop charging in a register of the charger chip; and the charge chip is also used for stopping charging the battery when a command for instructing the stop of charging is written in a register for determining the charge chip.

In one possible design, the SOC is specifically configured to obtain a charging condition of the battery from the charger chip, and when the charging condition is that the electric quantity is not fully charged, the SOC writes a command for instructing charging in a register of the charger chip; and the charge chip is also used for charging the battery when the instruction for instructing the charging is written in the register of the charge chip.

In one possible design, the charger chip is charged using a fast charge protocol FCP9V buck circuit mode.

In the second aspect and the possible design of the second aspect, the effect is similar to that in the first aspect and the possible design of the second aspect, and is not described again here.

Drawings

Fig. 1 is a schematic view of a charging scenario provided in an embodiment of the present application;

fig. 2 is a schematic view of a test interface provided in an embodiment of the present application;

FIG. 3 is a schematic view of another test interface provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present application;

fig. 5 is a schematic diagram of a charging circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic view of a test interface according to an embodiment of the present disclosure.

Detailed Description

The term "plurality" herein means two or more. The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship; in the formula, the character "/" indicates that the preceding and following related objects are in a relationship of "division".

It is to be understood that the various numerical references referred to in the embodiments of the present application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of the present application.

It should be understood that, in the embodiment of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiment of the present application.

When the electric quantity of the terminal equipment is insufficient, the terminal equipment can charge the battery based on wireless charging or wired charging.

Fig. 1 is a schematic diagram of wired charging of a terminal device according to an embodiment of the present disclosure, and as shown in fig. 1, when the terminal device needs to be charged, one end of a charger may be connected to a power supply, and the other end of the charger may be connected to the terminal device.

During the charging process, if the screen of the terminal device is lit, the current charging condition, such as the current power level, a charging mode (not shown in the figure), and the like, may be displayed on the screen, where the charging mode may include a super fast charging mode, a normal charging mode, and the like. And if the charger is unplugged or the battery is fully charged to 100%, the terminal equipment stops charging.

It can be understood that the terminal device may also be charged wirelessly, and the terminal device is disposed on the wireless charging device to charge the terminal device.

In a possible scenario, the following may occur: when a user charges the terminal equipment, the terminal equipment is connected with a power supply, but cannot be charged. Or, the terminal device may be charged normally after being connected to the power supply, or may not be charged, that is, the charging is unstable.

In general understanding, if the terminal device cannot be charged normally, it may be that the battery of the terminal device fails and cannot be charged. Or the interface of the terminal equipment is failed and cannot be charged. Or the charger fails and cannot be charged. Or the software system of the terminal equipment fails and charging cannot be carried out. Therefore, when the terminal device cannot be normally charged, the adopted means can be to replace the battery of the terminal device, the charging interface or the charger of the terminal device, or reinstall the software system of the terminal device.

However, the above-mentioned method of replacing hardware or reinstalling software on the terminal device may not be effective. Detecting hardware or software of the terminal device which cannot be normally charged, and finding that a battery of the terminal device, a charging interface of the terminal device and a software system of the terminal device are normal and have no fault.

Based on this, the reason that the terminal device without hardware or software failure cannot be normally charged is further analyzed in the embodiment of the present application, and it is found that the reason that the terminal device cannot be normally charged is: when a charger (charger) chip of a terminal device returns data to a System On Chip (SOC) of the terminal device through an inter-integrated circuit (I2C or IIC) bus, noise interference exists, so that the SOC gets an erroneous charging condition.

For example, during charging, the SOC may periodically obtain the state of charge from the charger chip. The SOC analyzes the high-level signal to obtain information that charging is completed, and writes a command to stop charging in a register of the charger chip to stop charging, so that the charger chip stops charging. However, the power of the terminal device is not fully charged, but the SOC obtains an error signal due to the interference of the noise, and issues an error command, so that the terminal device cannot be charged normally.

Specifically, for example, when the terminal device is charged in a Fast Charge Protocol (FCP) 9-volt (v) BUCK circuit (BUCK) mode, the waveform of I2C during charging is tested, and it is found that the quality of serial data line (SDA) signals in the I2C bus is poor and noise exists during charging.

For example, fig. 2 shows a waveform diagram of test I2C. Wherein SCLK is the clock signal, SDA is the data signal, BIT is the signal of resolving out. The lower waveform containing the noise is the waveform on the SDA path of I2C in the actual communication process. As shown in fig. 2, the SOC may periodically read the data of the charge chip according to SCLK and analyze the data to obtain a BIT signal, but when the data is transmitted from the charge chip through the SDA, noise exists.

The spur appears at a frequency of about 1.5 megahertz (Mhz) and is the same as the BUCK operating frequency of the charge chip, i.e., the spur is introduced when returning data from the charge chip to the SOC.

Thus, when the SOC periodically reads data from the charge chip, an abnormal situation of a read error may occur. For example, if there is clutter in the SDA return data that exceeds the SOC low receive threshold, the SOC will read high, causing an I2C read exception. In some scenarios, the threshold of the SOC determination low level is 0.35 × VDD — 0.3 × 1.8 — 0.63V. It can be understood that, due to the interference of the noise, the SOC may also misread the high level signal of the charge chip as the low level signal, resulting in an abnormal situation with a wrong degree.

For example, fig. 3 shows a schematic diagram of SOC read errors due to clutter interference. As shown in fig. 3, when the SOC reads data through the SDA at time a, the following waveform shows a high level, but the SOC misreads the high level as a low level. At time b, when the SOC reads data through the SDA, the lower waveform shows a low level, but the SOC misreads the low level as a high level.

In summary, in the above-described abnormal situation, when the battery is not fully charged and the SOC may obtain error information that the battery is fully charged, the SOC writes a command to stop charging into the register of the charge chip during the write operation, and after the charge chip obtains the command to stop charging, the charge chip may enter a high impedance state (HIZ), which may be understood as a state in which the charging path in the charge chip is open and the battery stops charging. The phenomenon that the terminal equipment cannot be charged after being connected with the power supply is caused. It should be noted that the HIZ state is a commonly understood high-impedance state, and other english translations are possible in practical applications, which are not limited herein.

In view of this, in the embodiment of the present application, the filter circuit is connected to the charge chip and the I2C path of the SOC, and the noise generated by the charge chip in the serial data line of the I2C bus is filtered by the filter circuit, so that the phenomenon that the terminal device cannot be normally charged due to noise interference can be effectively improved.

For example, fig. 4 provides a schematic structural diagram of a terminal device according to an embodiment of the present application.

As shown in fig. 4, the terminal device 300 includes: the system comprises a charge chip 310, an SOC320, a filter circuit 330 disposed on an IIC path of the charge chip 310 and the SOC320, a battery 340, a Power Management Unit (PMU) 350, an external low dropout regulator (LDO) 360, a micro amplifier (smart PA)370, an external amplifier RT-PA380, a Liquid Crystal Display (LCD) 3901, a camera 3902, and one or more voice processing units (spakers) 3903.

It is to be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation to the terminal device 300. In other embodiments of the present application, terminal device 300 may include more or fewer components than shown, or some components may be combined, some components may be split, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The Charger chip 310 can also be understood as a charging management module for receiving charging input from a Charger (or adapter). The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charger chip 310 may receive a charging input from a wired charger via a USB interface. In some wireless charging embodiments, the charger chip 310 may receive a wireless charging input through a wireless charging coil of the terminal device. While the charger chip 310 charges the battery 340, power can be supplied to the terminal device through the PMU 350.

Where SOC320 may be a processor, SOC320 may include one or more processing units, such as: SOC320 may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), among others. The different processing units may be separate devices or may be integrated into one or more processors.

The controller can generate an operation control signal according to the instruction operation code and the timing signal to complete the control of instruction fetching and instruction execution.

A memory may also be provided in SOC320 for storing instructions and data. In some embodiments, the memory in SOC320 is a cache memory. The memory may hold instructions or data that have just been used or recycled by SOC 320. If SOC320 needs to reuse the instruction or data, it may be called directly from the memory. Avoiding repeated accesses reduces the latency of the SOC320, thereby increasing the efficiency of the system.

In some embodiments, SOC320 may include one or more interfaces. The interface may include an integrated circuit (I2C) interface, an integrated circuit built-in audio (I2S) interface, a Pulse Code Modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a Mobile Industry Processor Interface (MIPI), a general-purpose input/output (GPIO) interface, a Subscriber Identity Module (SIM) interface, and/or a Universal Serial Bus (USB) interface, etc.

The I2C interface is a bi-directional synchronous serial bus that includes a serial data line SDA and a Serial Clock Line (SCL). In some embodiments, SOC320 may include multiple sets of I2C buses. The SOC320 may couple the touch sensor, the charger, the flash, the camera, etc. through different I2C bus interfaces, respectively. For example: the SOC320 may couple the touch sensor through an I2C interface, so that the SOC320 and the touch sensor communicate through an I2C bus interface, thereby implementing the touch function of the terminal device 300.

The I2S interface may be used for audio communication. In some embodiments, SOC320 may include multiple sets of I2S buses. SOC320 may be coupled with voice processing unit 3903 via an I2S bus, enabling communication between SOC320 and voice processing unit 3903. In some embodiments, the voice processing unit 3903 can communicate audio signals to the wireless communication module via the I2S interface to enable answering a call via a bluetooth headset.

The PCM interface may also be used for audio communication, sampling, quantizing and encoding analog signals. In some embodiments, the voice processing unit 3903 and the wireless communication module may be coupled by a PCM bus interface. In some embodiments, the voice processing unit 3903 can also deliver audio signals to the wireless communication module through the PCM interface to implement a function of answering a call through a bluetooth headset. Both the I2S interface and the PCM interface may be used for audio communication.

The UART interface is a universal serial data bus used for asynchronous communications. The bus may be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, a UART interface is generally used to connect SOC320 with a wireless communication module. For example: the SOC320 communicates with a bluetooth module in the wireless communication module through a UART interface to implement a bluetooth function. In some embodiments, the voice processing unit 3903 can transmit the audio signal to the wireless communication module through the UART interface, so as to implement the function of playing music through the bluetooth headset.

The MIPI interface may be used to connect SOC320 with peripheral devices such as a display screen, a camera, and the like. The MIPI interface includes a Camera Serial Interface (CSI), a Display Serial Interface (DSI), and the like. In some embodiments, SOC320 and camera 3902 communicate over a CSI interface, enabling the capture functionality of terminal device 300. The SOC320 and the display screen communicate via a DSI interface, and the display function of the terminal device 300 is realized.

The GPIO interface may be configured by software. The GPIO interface may be configured as a control signal and may also be configured as a data signal. In some embodiments, a GPIO interface may be used to connect SOC320 with camera 3902, a display screen, a wireless communication module, voice processing unit 3903, a sensor module, and the like. The GPIO interface may also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, and the like.

The USB interface is an interface which accords with the USB standard specification, and specifically can be a Mini USB interface, a Micro USB interface, a USB Type C interface and the like. The USB interface may be used to connect a charger to charge the terminal device 300, and may also be used to transmit data between the terminal device 300 and a peripheral device. And the earphone can also be used for connecting an earphone and playing audio through the earphone. The interface may also be used to connect other terminal devices, such as AR devices and the like.

It should be understood that the interface connection relationship between the modules illustrated in the embodiment of the present application is only an exemplary illustration, and does not constitute a limitation on the structure of the terminal device 300. In other embodiments of the present application, the terminal device 300 may also adopt different interface connection manners or a combination of multiple interface connection manners in the above embodiments.

PMU350, which may also be referred to as a power management module, is used to couple battery 340, charger chip 310, and SOC 320. The PMU350 receives input from the battery 340 and/or the charger chip 310, and provides power to the SOC320, the internal memory, the display, the camera 3902, and the wireless communication module. The PMU350 can also be used to monitor parameters such as battery capacity, battery cycle number, battery state of health (leakage, impedance), etc. In other embodiments, the PMU350 may also be placed in the SOC 320. In other embodiments, PMU350 and charge chip 310 may be located in the same device.

It should be noted that, in the embodiment of the present application, the filter circuit 330 is disposed on the IIC path between the charge chip 310 and the SOC320, and the filter circuit 330 may filter the SDA signal noise from the charge chip 310 to the SOC320, so as to improve the accuracy of the information acquired by the SOC320 from the charge chip 310 and improve the battery charging performance.

The external LDO360 is used for voltage stabilization of the terminal device, so that each power consuming device of the terminal device 300 obtains a stable voltage.

SmartPA370 and RT-PA380 are used for power amplification to provide operating power for the various power consuming devices of terminal device 300.

The display screen is used for displaying images, videos and the like. The display screen includes a display panel. The display panel may employ a Liquid Crystal Display (LCD) 3901, an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED), a flexible light-emitting diode (FLED), a miniature, a Micro-led, a quantum dot light-emitting diode (QLED), or the like. In some embodiments, the terminal device 300 may include 1 or N display screens, N being a positive integer greater than 1.

The terminal device 300 may implement a shooting function through the ISP, the camera 3902, the video codec, the GPU, the display screen, the application processor, and the like.

The ISP is used to process data fed back by the camera 3902. For example, when a photo is taken, the shutter is opened, light is transmitted to the camera photosensitive element through the lens, the optical signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing and converting into an image visible to naked eyes. The ISP can also carry out algorithm optimization on the noise, brightness and skin color of the image. The ISP can also optimize parameters such as exposure, color temperature and the like of a shooting scene. In some embodiments, the ISP may be provided in the camera 3902.

The camera 3902 is used to capture still images or video. The object generates an optical image through the lens and projects the optical image to the photosensitive element. The photosensitive element may be a Charge Coupled Device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The light sensing element converts the optical signal into an electrical signal, which is then passed to the ISP where it is converted into a digital image signal. And the ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into image signal in standard RGB, YUV and other formats. In some embodiments, the terminal device 300 may include 1 or N cameras 3902, N being a positive integer greater than 1.

The digital signal processor is used for processing digital signals, and can process digital image signals and other digital signals. For example, when the terminal device 300 selects a frequency point, the digital signal processor is used to perform fourier transform or the like on the frequency point energy.

Video codecs are used to compress or decompress digital video. The terminal device 300 may support one or more video codecs. In this way, the terminal device 300 can play or record video in a plurality of encoding formats, such as: moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, and the like.

The NPU is a neural-network (NN) computing processor that processes input information quickly by using a biological neural network structure, for example, by using a transfer mode between neurons of a human brain, and can also learn by itself continuously. The NPU can implement applications such as intelligent recognition of the terminal device 300, for example: image recognition, face recognition, speech recognition, text understanding, and the like.

The external memory interface may be used to connect an external memory card, such as a Micro SD card, to extend the storage capability of the terminal device 300. The external memory card communicates with the SOC320 through an external memory interface to implement a data storage function. For example, files such as music, video, etc. are saved in an external memory card.

The internal memory may be used to store computer-executable program code, which includes instructions. The internal memory may include a program storage area and a data storage area. The storage program area may store an operating system, an application program (such as a sound playing function, an image playing function, etc.) required by at least one function, and the like. The storage data area may store data (such as audio data, a phonebook, etc.) created during use of the terminal device 300, and the like. In addition, the internal memory may include a high-speed random access memory, and may further include a nonvolatile memory, such as at least one of a magnetic disk storage device, a flash memory device, a universal flash memory (UFS), and the like. The SOC320 executes various functional applications of the terminal device 300 and data processing by executing instructions stored in an internal memory and/or instructions stored in a memory provided in the processor.

The terminal device 300 may implement an audio function through the voice processing unit 3903, a speaker, a receiver, a microphone, an earphone interface, and an application processor. Such as music playing, recording, etc.

The speech processing unit 3903 is used to convert digital audio information into an analog audio signal output and also to convert an analog audio input into a digital audio signal. The speech processing unit 3903 may also be used to encode and decode audio signals. In some embodiments, the speech processing unit 3903 may be disposed in the SOC320, or portions of the functional modules of the speech processing unit 3903 may be disposed in the SOC 320.

The terminal device 300 may further include various sensors (not shown in the drawings) and the like. The embodiment of the present application does not limit the specific structure of the terminal device 300.

In summary, in the embodiment of the present application, the filter circuit 330 is disposed on the IIC path between the charge chip 310 and the SOC320, and the filter circuit 330 may filter the SDA signal noise from the charge chip 310 to the SOC320, so as to improve the accuracy of the information acquired by the SOC320 from the charge chip 310 and improve the battery charging performance.

The filter circuit 330 disposed in the IIC path of the charge chip 310 and the SOC320 will be described in detail with reference to fig. 5. For example, fig. 5 shows a charging circuit provided in an embodiment of the present application.

As shown in fig. 5, a filter circuit 330 is provided in the SDA path between the charge chip 310 and the SOC320, and noise generated in the serial data line of the I2C bus by the charge chip can be filtered by the filter circuit 330.

In a possible design, the filter circuit 330 may be a resistor-capacitor (RC) filter circuit, and the filter circuit 330 includes a resistor 3301 and a capacitor 3302. One end of the resistor 3301 is connected to an interface for SDA signal transmission in the charge chip 310, the other end of the resistor 3301 is connected to an interface for SDA signal transmission in the SOC320, one end of the capacitor 3302 is connected to an interface for SDA signal transmission in the SOC320, and the other end of the capacitor 3302 is grounded.

It is understood that there is also a serial clock line SCL (or SCK) path between the charger chip 310 and the SOC320 in fig. 5, and SCL is responsible for generating synchronous clock pulses for I2C operation.

It can be understood that the filter circuit in the embodiment of the present application can be used in the terminal device maintenance in the later period, and the filter circuit is added to the main board of the terminal device, or the filter circuit can also be used in the terminal device production and manufacturing process, and when the terminal device is manufactured, the filter circuit is integrated in the main board of the terminal device, so that the charging instability of the terminal device is improved. The filter circuit 330 may be any other filter circuit, such as one or more combinations of resistive filtering, capacitive filtering, inductive filtering, and RC filtering, and the embodiments of the present application are not limited in particular.

Since the RC filter circuit has the effects of low cost and high performance, the RC filter circuit may be adopted in the embodiment of the present application, and the RC filter circuit in fig. 5 is taken as an example.

The resistance R can be any value from 0 omega to 300 omega, and the capacitance C can be any value from 0pF to 400 pF.

It will be appreciated that the smaller the product of RC, the faster the circuit responds, but the circuit is susceptible to oscillation. The larger the product of RC, the more stable the circuit, but the slower the circuit response. And the larger the value of R is, the longer the voltage climbing time is, and the longer the required charging time is, so that the value of RC also relates to the performance of the terminal equipment.

The clutter amplitude comparison for several filter circuits is illustrated below as table 1.

TABLE 1

Therefore, before modification, clutter amplitude is large and reaches 718mV, RC combination is 47 omega +220pF clutter amplitude and is minimum, but the I2C bus is affected by overlarge capacitance, so that the value of R is 47 omega, and the value of C is 56pF in possible implementation, the condition that terminal equipment cannot be normal can be effectively improved, and the work of the I2C bus can also be guaranteed.

For example, table 2 shows the test results for I2C when R is 47 Ω and C is 56 pF.

TABLE 2

Therefore, an RC filter circuit with the R value of 47 omega and the C value of 56pF is added in the terminal equipment, so that the I2C communication quality is not influenced, and the signal quality meets the protocol requirement.

For example, table 3 shows the comparison of the clutter signal amplitudes of several products when R is 47 Ω and C is 56 pF.

TABLE 3

Charging IC	Before 9V change	After 9V change	Before 5V change	After 5V change
					Product A	718mV	425mV	564mV	412mV
Product A	656mV	398mV	568mV	358mV
					Product C	382mV	254mV	422mV	294mV

For example, fig. 6 shows a schematic diagram of comparing the amplitude of the clutter with the filter circuit on the SDA path (after modification) and without the filter circuit (before modification). As shown in fig. 6, the amplitude of the modified spur is significantly smaller than the amplitude of the spur before modification.

Therefore, an RC filter circuit with the R value of 47 omega and the C value of 56pF is added in the terminal equipment, so that clutter signals are obviously inhibited. For example, the comparison between the data before 9V modification and the data after 9V modification shows that the clutter amplitude after modification is obviously smaller than that before modification, thereby achieving obvious inhibition effect and improving the signal-to-noise ratio of the signal. And through testing, after an RC filter circuit with the R value of 47 omega and the C value of 56pF is added in the terminal equipment, the problem that the terminal equipment cannot be normally charged is greatly improved.

It should be noted that the charger chip in the embodiment of the present application may also be replaced by any other chip for realizing charging, and the SOC may be replaced by any other chip for managing charging.

The terminal device of the embodiment of the application may be a device based on battery charging, for example, a handheld device, an in-vehicle device, and the like having a wireless connection function. Currently, some examples of terminals are: a mobile phone (mobile phone), a tablet computer, a notebook computer, a palm computer, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an Augmented Reality (AR) device, a wireless terminal in industrial control (industrial control), a wireless terminal in self driving (self driving), a wireless terminal in remote operation (remote local supply), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation security (transportation safety), a wireless terminal in city (city), a wireless terminal in smart home (smart home), a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a wireless local loop (wireless local) phone, a personal digital assistant (WLL) station, a handheld personal communication device with wireless communication function, a wireless terminal in industrial control (industrial control), a wireless terminal in transportation security (personal control), a wireless terminal in city (smart home), a wireless terminal in smart home (smart home), a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a wireless local loop (personal digital assistant (PDA) phone, a wireless local communication device with wireless communication function, a wireless communication device, a, A computing device or other processing device connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a 5G network, or a terminal device in a Public Land Mobile Network (PLMN) for future evolution, and the like, which are not limited in this embodiment of the present application.

By way of example and not limitation, in the embodiments of the present application, the terminal device may also be a wearable device. Wearable equipment can also be called wearable intelligent equipment, is the general term of applying wearable technique to carry out intelligent design, develop the equipment that can dress to daily wearing, like glasses, gloves, wrist-watch, dress and shoes etc.. A wearable device is a portable device that is worn directly on the body or integrated into the clothing or accessories of the user. The wearable device is not only a hardware device, but also realizes powerful functions through software support, data interaction and cloud interaction. The generalized wearable smart device includes full functionality, large size, and can implement full or partial functionality without relying on a smart phone, such as: smart watches or smart glasses and the like, and only focus on a certain type of application functions, and need to be used in cooperation with other devices such as smart phones, such as various smart bracelets for physical sign monitoring, smart jewelry and the like.

In addition, in the embodiment of the present application, the terminal device may also be a terminal device in an internet of things (IoT) system, where IoT is an important component of future information technology development, and a main technical feature of the present application is to connect an article with a network through a communication technology, so as to implement an intelligent network with interconnected human-computer and interconnected objects.

The terminal device in the embodiment of the present application may also be referred to as: user Equipment (UE), Mobile Station (MS), Mobile Terminal (MT), access terminal, subscriber unit, subscriber station, mobile station, remote terminal, mobile device, user terminal, wireless communication device, user agent, or user device, etc.

In the embodiment of the present application, the terminal device or each network device includes a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer. The hardware layer includes hardware such as a Central Processing Unit (CPU), a Memory Management Unit (MMU), and a memory (also referred to as a main memory). The operating system may be any one or more computer operating systems that implement business processing through processes (processes), such as a Linux operating system, a Unix operating system, an Android operating system, an iOS operating system, or a windows operating system. The application layer comprises applications such as a browser, an address list, word processing software, instant messaging software and the like.

The above embodiments, structural diagrams or simulation diagrams are only schematic illustrations of the technical solutions of the present application, and the dimensional ratios thereof do not limit the scope of the technical solutions, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the above embodiments should be included in the scope of the technical solutions.

Claims

1. A terminal device, comprising: the system comprises a charger charge chip, a system-on-chip SOC, a filter circuit, a battery, a power management unit, a voltage stabilizer and an amplifier;

the filter circuit is arranged on an I2C bus path of the internal integrated circuit between the charger chip and the system level chip SOC;

the charger charge chip is used for receiving charging input from a power supply, charging the battery, receiving discharging of the battery and providing power for a power consumption device of the terminal equipment;

the filter circuit is used for filtering noise waves generated by the charger charge chip in a serial data line in the I2C bus;

the system level chip SOC is used for obtaining the charging condition of the battery from the charger charge chip and controlling the battery to be charged or stop charging according to the charging condition;

the power supply management unit is used for receiving the input of the battery and/or the charger charge chip and managing the state of the battery;

the voltage stabilizer is used for stabilizing voltage when power is supplied to a power consumption device of the terminal equipment;

the amplifier is used for amplifying power when power is supplied to a power consumption device of the terminal equipment;

wherein the filter circuit comprises a resistor and a capacitor;

one end of the resistor is connected with an interface for transmitting SDA signals in the charger charge chip, and the other end of the resistor is connected with an interface for transmitting SDA signals in the system-on-chip SOC;

one end of the capacitor is connected with an interface used for SDA signal transmission in the system-on-chip SOC, and the other end of the capacitor is grounded;

the resistance value of the resistor is any value from 0 omega to 300 omega, and the value of the capacitor is any value from 0pF to 400 pF.

2. The terminal device of claim 1, wherein the resistor has a value of 47 Ω and the capacitor has a value of 56 pF.

3. The terminal device according to claim 1 or 2, wherein the SOC is specifically configured to obtain a charging condition of the battery from the charger charge chip, and when the charging condition is that the battery is fully charged, the SOC writes an instruction for instructing to stop charging in a register of the charger charge chip;

the charger chip is further configured to stop charging the battery when it is determined that an instruction for instructing to stop charging is written in a register of the charger chip.

4. The terminal device according to claim 1 or 2, wherein the SOC is specifically configured to obtain a charging condition of the battery from the charger charge chip, and when the charging condition is that the battery is not fully charged, the SOC writes a command indicating charging in a register of the charger charge chip;

the charger chip is further configured to charge the battery when it is determined that an instruction for instructing charging is written in a register of the charger chip.

5. The terminal device according to claim 1 or 2, characterized in that the terminal device is charged using a fast charging protocol FCP9V buck circuit mode.

6. A charging circuit, comprising: the charger comprises a charger charge chip, a system-on-chip SOC, a filter circuit and a battery;

wherein the filter circuit comprises a resistor and a capacitor;

7. The charging circuit of claim 6, wherein the resistor has a value of 47 Ω and the capacitor has a value of 56 pF.

8. The charging circuit according to claim 6 or 7, wherein the SOC is specifically configured to obtain a charging condition of the battery from the charger charge chip, and when the charging condition is that the battery is fully charged, the SOC writes an instruction indicating to stop charging in a register of the charger charge chip;

9. The charging circuit according to claim 6 or 7, wherein the SOC is specifically configured to obtain a charging condition of the battery from the charger charge chip, and when the charging condition is an insufficient charge, the SOC writes a command indicating charging in a register of the charger charge chip;

10. The charging circuit of claim 6 or 7, wherein the charger-charger chip is charged in a fast charging protocol FCP9V buck mode.