CN113394316A - Deep ultraviolet light-emitting element and preparation method thereof - Google Patents
Deep ultraviolet light-emitting element and preparation method thereof Download PDFInfo
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- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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Abstract
The invention provides a deep ultraviolet light-emitting element and a preparation method thereof, wherein the deep ultraviolet light-emitting element sequentially comprises the following components from bottom to top: the semiconductor device comprises a substrate, multiple buffer layers, a merging layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer, wherein the multiple buffer layers comprise a first buffer layer and a second buffer layer positioned on the first buffer layer, the second buffer layer comprises at least two layers of structures with gradient growth temperatures, and the growth temperature of the second buffer layer is 900-1200 ℃. According to the deep ultraviolet light-emitting element, the multiple buffer layer structure is formed, so that lattice mismatch stress and thermal stress between the merging layer and the substrate can be effectively released, the defects and dislocation density of the deep ultraviolet light-emitting element are reduced, and the light-emitting efficiency of the deep ultraviolet light-emitting element is improved to 5% -10%.
Description
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a deep ultraviolet light-emitting element and a preparation method thereof.
Background
The deep ultraviolet light emitting element has the wavelength range of 200-300 nm, can interrupt DNA or RNA of viruses and bacteria by the emitted deep ultraviolet light, directly kills the viruses and the bacteria, and can be widely applied to the sterilization and disinfection fields of air purification, tap water sterilization, household air conditioner sterilization, automobile air conditioner sterilization and the like.
Deep ultraviolet light emitting elements generally adopt AlGaN-based materials to carry out epitaxial growth on a sapphire substrate; due to the fact that lattice mismatch and thermal mismatch exist between AlGaN and sapphire, when AlGaN-based materials are epitaxially grown, the problems that more dislocations, defects, cracks and the like are generated under the action of substrate mismatch stress are solved. The existing epitaxial growth AlGaN material adopts a low-temperature AlN buffer layer technology to release stress, but the growth temperature of the low-temperature AlN buffer layer is low, so that the low-temperature AlN buffer layer has a large amount of dislocation and defects, and the dislocation and the defects can continuously extend and climb upwards in the epitaxial growth process, so that the AlN and AlGaN materials epitaxially grown above the low-temperature AlN buffer layer also have higher dislocation density, and the crystal quality is deviated, so that the luminous efficiency of a deep ultraviolet light emitting element is generally lower than 5%.
Disclosure of Invention
The invention aims to provide a deep ultraviolet light-emitting element and a preparation method thereof, which aim to reduce lattice mismatch of the deep ultraviolet light-emitting element, reduce dislocation and defect density of the deep ultraviolet light-emitting element, improve crystal quality and further improve light-emitting efficiency of the deep ultraviolet light-emitting element.
In order to achieve the above and other related objects, the present invention provides a deep ultraviolet light emitting device, which comprises, from bottom to top: the semiconductor device comprises a substrate, multiple buffer layers, a merging layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer, wherein the multiple buffer layers comprise a first buffer layer and a second buffer layer positioned on the first buffer layer, the second buffer layer comprises at least two layers of structures with gradient growth temperatures, and the growth temperature of the second buffer layer is 900-1200 ℃.
Optionally, in the deep ultraviolet light emitting element, the second buffer layer includes an intermediate buffer layer and a high temperature buffer layer located on the intermediate buffer layer, and a growth temperature of the high temperature buffer layer is higher than a growth temperature of the intermediate buffer layer.
Optionally, in the deep ultraviolet light emitting element, the growth temperature of the medium-temperature buffer layer is 900 ℃ to 1100 ℃.
Optionally, in the deep ultraviolet light emitting element, the growth temperature of the high temperature buffer layer is 1100 ℃ to 1200 ℃.
Optionally, in the deep ultraviolet light emitting element, the thickness of the medium-temperature buffer layer is 5nm to 100 nm.
Optionally, in the deep ultraviolet light emitting element, the high temperature buffer layer has a thickness of 50nm to 500 nm.
Optionally, in the deep ultraviolet light emitting element, the material of the first buffer layer and the second buffer layer includes AlN.
Optionally, in the deep ultraviolet light emitting element, the thickness of the first buffer layer is 5nm to 20 nm.
Optionally, in the deep ultraviolet light emitting element, the merging layer merges the dispersed crystals of the multiple buffer layers by a two-dimensional lateral growth manner to obtain a flat surface.
Optionally, in the deep ultraviolet light emitting device, a material of the merging layer includes AlN.
Optionally, in the deep ultraviolet light emitting element, the growth temperature of the merged layer is 1200 to 1400 ℃.
In order to achieve the above objects and other related objects, the present invention also provides a method for manufacturing a deep ultraviolet light emitting device, including:
providing a substrate;
forming multiple buffer layers on the substrate, wherein the multiple buffer layers comprise a first buffer layer and a second buffer layer positioned on the first buffer layer, the second buffer layer comprises at least two layers of structures with gradient growth temperature, and the growth temperature of the second buffer layer is 900-1200 ℃;
forming a merged layer on the multiple buffer layers;
and sequentially forming an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer on the combined layer.
Optionally, in the preparation method of the deep ultraviolet light emitting element, the second buffer layer includes an intermediate temperature buffer layer and a high temperature buffer layer located on the intermediate temperature buffer layer, and a growth temperature of the high temperature buffer layer is higher than a growth temperature of the intermediate temperature buffer layer.
Optionally, in the preparation method of the deep ultraviolet light emitting element, the growth temperature of the medium-temperature buffer layer is 900 ℃ to 1100 ℃.
Optionally, in the preparation method of the deep ultraviolet light emitting element, the growth temperature of the high-temperature buffer layer is 1100 ℃ to 1200 ℃.
Optionally, in the preparation method of the deep ultraviolet light emitting element, the thickness of the medium-temperature buffer layer is 5nm to 100 nm.
Optionally, in the preparation method of the deep ultraviolet light emitting element, the thickness of the high temperature buffer layer is 50nm to 500 nm.
Optionally, in the preparation method of the deep ultraviolet light emitting element, the material of the first buffer layer and the second buffer layer includes AlN.
Optionally, in the method for manufacturing the deep ultraviolet light emitting element, the thickness of the first buffer layer is 5nm to 20 nm.
Optionally, in the method for manufacturing a deep ultraviolet light emitting device, the merged layer merges the dispersed crystals of the multiple buffer layers by a two-dimensional lateral growth manner to obtain a flat surface.
Optionally, in the preparation method of the deep ultraviolet light emitting device, a material of the merging layer includes AlN.
Optionally, in the method for manufacturing the deep ultraviolet light emitting element, the growth temperature of the merged layer is 1200 ℃ to 1400 ℃.
Optionally, in the method for manufacturing a deep ultraviolet light emitting device, a process of forming the first buffer layer includes a PVD process.
Optionally, in the method for manufacturing the deep ultraviolet light emitting element, a process of forming the second buffer layer includes an MOCVD process.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
by adopting the multiple buffer layer structure with higher growth temperature, the lattice mismatch stress and thermal stress between the merging layer and the substrate can be effectively released, the surface problems of surface cracks, roughness, non-growth and the like of the deep ultraviolet light-emitting element are reduced, the defects and dislocation density of the multiple buffer layers and the merging layer are reduced, and the light-emitting efficiency of the deep ultraviolet light-emitting element is further improved to 5-10%.
Drawings
Fig. 1 is a schematic structural diagram of a deep ultraviolet light emitting device in an embodiment of the invention;
FIG. 2 is a flow chart of a method for fabricating a deep ultraviolet light emitting device in an embodiment of the present invention;
in FIGS. 1-2, the first and second electrodes are shown,
100-substrate, 101-multiple buffer layer, 1011-first buffer layer, 1012-medium temperature buffer layer, 1013-high temperature buffer layer, 102-merging layer, 103-n type semiconductor layer, 104-quantum well layer, 105-p type semiconductor layer, 1051-p type electron barrier layer, 1052-p type contact layer.
Detailed Description
In the existing deep ultraviolet light-emitting element, a low-temperature AlN buffer layer technology is generally adopted to release stress, but the growth temperature (500 ℃ -900 ℃) of the low-temperature AlN buffer layer is low, so that the low-temperature AlN buffer layer has a large number of dislocations and defects, and the dislocations and the defects can continuously extend and climb upwards in the epitaxial growth process, so that AlN and AlGaN materials epitaxially grown above the low-temperature AlN buffer layer have higher dislocation density and crystal quality deviation, and further the light-emitting efficiency of the deep ultraviolet light-emitting element is generally lower than 5%.
In order to reduce lattice mismatch, reduce dislocation and defect density of the deep ultraviolet light-emitting element and further improve the light-emitting efficiency of the deep ultraviolet light-emitting element, the invention provides an ultraviolet semiconductor light-emitting element and a preparation method thereof.
Before describing embodiments according to the present invention, the following description will be made in advance. First, in the present specification, the Al composition ratio is not explicitly given, and when only "AlGaN" is given, it means that the chemical composition ratio of the group III element (the sum of Al and Ga) to N is 1: 1, any compound having an unfixed ratio of the group III element Al to Ga. Note that, when only denoted by "AlN" or "GaN", Ga and Al are not included in the composition ratio, but are not excluded by the mere designation of "AlGaN". The value of the Al composition ratio can be measured by photoluminescence measurement, X-ray diffraction measurement, or the like.
In this specification, a layer that electrically functions as a p-type layer is referred to as a p-type layer, and a layer that electrically functions as an n-type layer is referred to as an n-type layer. On the other hand, when a specific impurity such as Mg or Si is not particularly added and does not electrically function as a p-type or an n-type, it is referred to as "i-type" or "undoped". The undoped layer may be mixed with impurities inevitable in the manufacturing process, and specifically, when the carrier density is small (for example, less than 4 × 10/cm), it is referred to as "undoped" in the present specification. The values of the concentrations of impurities such as Mg and Si were obtained by SIMS analysis.
The deep ultraviolet light emitting device and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, the deep ultraviolet light emitting device provided by the present invention may sequentially include, from bottom to top: the semiconductor device comprises a substrate 100, a multiple buffer layer 101, a combined layer 102, an n-type semiconductor layer 103, a quantum well layer 104 and a p-type semiconductor layer 105, wherein the multiple buffer layer 101 comprises a first buffer layer 1011 and a second buffer layer located on the first buffer layer 1011, the second buffer layer comprises at least two layers of structures with gradient growth temperature, and the growth temperature of the second buffer layer is 900-1200 ℃.
As the substrate 100, a substrate that can transmit light emitted from the quantum well layer 104 is preferably used, and for example, a sapphire substrate, a single crystal AlN substrate, or the like can be used.
A first buffer layer 1011 is deposited on the substrate 100, and preferably, the first buffer layer 1011 is deposited using a PVD (Physical Vapor Deposition) process. The material of the first buffer layer 1011 is preferably AlN, but is not limited thereto. Compared with the first buffer layer 1011 formed by an MOCVD (Metal Organic Chemical Vapor Deposition) process, the first buffer layer 1011 formed by the PVD process has smaller and more uniform AlN particles and better C-axis orientation, and therefore, the first buffer layer 1011 formed by the PVD process can better reduce lattice mismatch between the substrate and the epitaxial layer (e.g., a merged layer), and obtain more excellent crystal quality and surface morphology.
The thickness of the first buffer layer 1011 is within the critical thickness of the first buffer layer 1011, and is preferably 5nm to 20 nm. The critical thickness of the first buffer layer 1011 is 30nm, and when the thickness of the first buffer layer 1011 exceeds the critical thickness, the mismatch stress between the substrate 100 (e.g., sapphire) and the first buffer layer 1011 gathers to cause surface cracks, which increases defects, thereby affecting the performance of the deep ultraviolet light emitting device, such as the light emitting efficiency.
A second buffer layer is deposited on the first buffer layer 1011, the second buffer layer comprising at least a two-layer structure with a gradient in growth temperature. Furthermore, the growth temperature of the structural layer in the second buffer layer from bottom to top increases progressively. For example, the second buffer layer may include a two-layer structure, specifically, an intermediate-temperature buffer layer 1012 on the first buffer layer 1011 and a high-temperature buffer layer 1013 on the intermediate-temperature buffer layer 1012, and a growth temperature of the high-temperature buffer layer 1013 is higher than a growth temperature of the intermediate-temperature buffer layer 1012, see fig. 1. For another example, the second buffer layer may include three structural layers, that is, a structural layer with a higher growth temperature is disposed on the high-temperature buffer layer. Of course, the second buffer layer may further include four structural layers, five structural layers, and the like, which are not described herein again.
The growth temperature of the second buffer layer is preferably 900-1200 ℃. Compared with the low-temperature AlN buffer layer technology in the prior art, the temperature for growing the second buffer layer in the embodiment is higher, so that the dislocation and defect density can be better reduced to 5E7cm-2The following.
The growth temperature of the structural layer in the second buffer layer can be reasonably divided according to 900-1200 ℃. For example, when the second buffer layer includes the intermediate-temperature buffer layer 1012 and the high-temperature buffer layer 1013 on the intermediate-temperature buffer layer 1012, the growth temperature of the intermediate-temperature buffer layer 1012 is preferably 900 to 1100 ℃, and the growth temperature of the high-temperature buffer layer 1013 is preferably 1100 to 1200 ℃.
Since the thicknesses of the middle temperature buffer layer 1012 and the high temperature buffer layer 1013 are too thin, the merged layer 102 cannot be merged in length and cracked, and too thick, the defect density is increased, and the light emitting efficiency is decreased. Therefore, the thickness of the medium-temperature buffer layer 1012 is preferably 5nm to 100nm, and the thickness of the high-temperature buffer layer 1013 is preferably 50nm to 500 nm.
The formation process of the second buffer layer is preferably an MOCVD process, but is not limited thereto. For example, the middle temperature buffer layer 1012 is deposited on the first buffer layer 1011 by using an MOCVD process at 1000 ℃; and then depositing the high temperature buffer layer 1013 on the medium temperature buffer layer 1012 at 1150 ℃.
The material of the second buffer layer is preferably AlN, but is not limited thereto. That is, the medium temperature buffer layer 1012 and the high temperature buffer layer 1013 are made of the same material, and are preferably AlN. The growth of the second buffer layer is mainly 3D island-shaped growth, and stress is released. Because the second buffer layer is the structural layer that growth temperature is gradient change, consequently, be in the formation thermal stress and lattice mismatch stress are released gradually in the process of second buffer layer, and the second buffer layer that growth temperature is gradient change more is favorable to the release of stress, and is favorable to reducing surface defects such as crackle for the crystal quality of the buffer layer that finally obtains is higher, and surface morphology is better.
In this embodiment, the multiple buffer layer 101 replaces the low temperature buffer layer (process temperature is 500 ℃ to 900 ℃) in the prior art with the first buffer layer 1011 and the second buffer layer. The first buffer layer 1011 is generated by a PVD process, the second buffer layer is a structural layer with gradient growth temperature, and the process temperature is 900-1200 ℃. The second buffer layer is a structural layer with gradient growth temperature, so that stress release is facilitated; in addition, the temperature for growing the multiple buffer layers in the embodiment is higher, so that the dislocation and defect density can be better reduced to 5E7cm-2The following. That is, the deep ultraviolet light emitting device of the embodiment can effectively release lattice mismatch stress and thermal stress between the merged layer 102 and the substrate 100, reduce surface problems of surface cracks, roughness, non-growth and the like of the deep ultraviolet light emitting device, reduce defects and dislocation density of the buffer layer and the merged layer, and further improve the light emitting efficiency of the deep ultraviolet light emitting device to 5% -10%.
The merged layer 102 is formed on the second buffer layer, and the material of the merged layer 102 is preferably AlN, but is not limited thereto. The formation process of the combined layer 102 is preferably MOCVD, but not limited thereto, and the growth temperature of the combined layer 102 is preferably 1200 to 1400 ℃. The merged layer 102 is an undoped AlN layer, and mainly uses 2D growth, that is, mainly uses two-dimensional lateral growth, and can merge the dispersed crystals of the multiple buffer layer 101 and grow a flat surface. That is, the merged layer 102 may have a flat surface by a two-dimensional lateral growth.
An n-type semiconductor layer 103, a quantum well layer 104, and a p-type semiconductor layer 105 are sequentially deposited on the merged layer 102.
The n-type semiconductor layer 103 is disposed on the merged layer 102. The n-type semiconductor layer 103 may be a conventional n-type semiconductor layerThe layer may be made of n-AlGaN, for example. The n-type semiconductor layer 103 functions as an n-type layer by doping an n-type dopant, and specific examples of the n-type dopant include silicon (Si), germanium (Ge), tin (Sn), sulfur (S), oxygen (O), titanium (Ti), zirconium (Zr), and the like. The dopant concentration of the n-type dopant is not particularly limited as long as the n-type semiconductor layer 103 can function as an n-type layer. Further, the n-type dopant in the n-type semiconductor layer 103 is preferably Si, and the doping concentration of Si is preferably 1E18cm-3～5E19cm-3. The n-type semiconductor layer 103 preferably has a band gap wider than that of the quantum well layer 104 (a well layer in the case of a multiple quantum well structure) and has a transmittance for deep ultraviolet light to be emitted. The n-type semiconductor layer 103 may have a single-layer structure or a multi-layer structure, or may have a superlattice structure.
The quantum well layer 104 is disposed on the n-type semiconductor layer 103. The quantum well layer 104 may have a single-layer structure, and preferably has a multi-quantum well (MQW) structure in which a well layer and a barrier layer made of AlGaN having different Al composition ratios are stacked. When the quantum well layer 104 has a single-layer structure, the layer emitting deep ultraviolet light is the quantum well layer itself; in the case where the quantum well layer 104 has a multiple quantum well structure, the layer emitting deep ultraviolet light is a well layer. The quantum well layer 104 is a conventional structure and will not be described herein.
A p-type semiconductor layer 105 disposed on the quantum well layer 104, which may include a p-type electron blocking layer 1051 and a p-type contact layer 1052. The p-type electron blocking layer 1051 is used to block electrons, prevent the electrons from overflowing to the p-type contact layer 1052, and further inject the electrons into the quantum well layer 104 (well layer in the case of a multiple quantum well structure), thereby reducing the occurrence of nonradiative recombination.
The material of the p-type electron blocking layer 1051 is preferably AlGaN, but is not limited thereto. The thickness of the p-type electron blocking layer 1051 is not particularly limited. The thickness of the p-type electron blocking layer 1051 is preferably greater than the thickness of the barrier layer. Examples of the p-type dopant doped into the p-type electron blocking layer 1051 include magnesium (Mg), zinc (Zn), calcium (Ca), beryllium (Be), manganese (Mn), and the like, and Mg is generally used. The dopant concentration of the p-type electron blocking layer is not particularly limited as long as it is a dopant concentration that can function as a p-type semiconductor layer.
The p-type contact layer 1052 is disposed on the p-type electron blocking layer 1051. The p-type contact layer 1052 is a structure layer for reducing contact resistance between the p-side electrode disposed directly above it and the p-type electron blocking layer 1051.
As the p-type contact layer of the deep ultraviolet light emitting element, a p-type GaN layer which is easy to increase the hole concentration is generally used, and a p-type AlGaN layer may be used, and although the hole concentration may be slightly decreased in the AlGaN layer compared to the GaN layer, the deep ultraviolet light emitted from the light emitting layer can transmit through the p-type AlGaN layer, so that the light extraction efficiency of the whole deep ultraviolet light emitting element is improved, and the light emission output of the deep ultraviolet light emitting element can be improved.
In addition, the present invention further provides a method for manufacturing the deep ultraviolet light emitting device, referring to fig. 2, which specifically includes:
step S1: providing a substrate;
step S2: forming multiple buffer layers on the substrate, wherein the multiple buffer layers comprise a first buffer layer and a second buffer layer positioned on the first buffer layer, the second buffer layer comprises at least two layers of structures with gradient growth temperature, and the growth temperature of the second buffer layer is 900-1200 ℃;
step S3: forming a merged layer on the multiple buffer layers;
step S4: an n-type semiconductor layer 103, a quantum well layer 104, and a p-type semiconductor layer 105 are formed on the combined layer.
In step S1, as the substrate 100, a substrate that can transmit light emitted from the quantum well layer 104 is preferably used, and for example, a sapphire substrate, a single crystal AlN substrate, or the like can be used.
In step S2, a first buffer layer 1011 is deposited on the substrate 100, and preferably, the first buffer layer 1011 is deposited by a PVD process. The material of the first buffer layer 1011 is preferably AlN, but is not limited thereto. Compared with the first buffer layer 1011 formed by the MOCVD process, the first buffer layer 1011 formed by the PVD process has smaller and more uniform AlN particles and better C-axis orientation, so that the lattice mismatch between the foreign substrate and the epitaxial layer can be better reduced by the first buffer layer 1011 formed by the PVD process, and more excellent crystal quality and surface morphology are obtained.
The second buffer layer comprises at least two layers of structures with gradient growth temperature, and preferably, the growth temperature of the structural layer in the second buffer layer increases progressively from bottom to top. For example, the second buffer layer includes two structural layers, specifically, an intermediate temperature buffer layer 1012 on the first buffer layer 1011 and a high temperature buffer layer 1013 on the intermediate temperature buffer layer 1012, and a growth temperature of the high temperature buffer layer 1013 is higher than a growth temperature of the intermediate temperature buffer layer 1012. For another example, the second buffer layer includes three structural layers, that is, a structural layer with a higher growth temperature is disposed on the high-temperature buffer layer. Of course, the second buffer layer may further include four structural layers, five structural layers, and the like, which are not described herein again.
In step S3, a merged layer 102 is formed on the second buffer layer, and the material of the merged layer 102 is preferably AlN, but is not limited thereto. The formation process of the combined layer 102 is preferably MOCVD, but not limited thereto, and the growth temperature of the combined layer 102 is preferably 1200 to 1400 ℃. The merged layer 102 is an undoped AlN layer, and mainly uses 2D growth, that is, mainly uses two-dimensional lateral growth, and can merge the dispersed crystals of the multiple buffer layer 101 and grow a flat surface.
The n-type semiconductor layer 103, the quantum well layer 104, and the p-type semiconductor layer 105 may be formed by a known thin film growth method such as a Metal Organic Chemical Vapor Deposition (MOCVD) process, a Molecular Beam Epitaxy (MBE) method, a Hydride Vapor Phase Epitaxy (HVPE) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and a sputtering process, and preferably, the n-type semiconductor layer 103, the quantum well layer 104, and the p-type semiconductor layer 105 are formed by a MOCVD method.
Compared with the existing deep ultraviolet light-emitting element and the preparation method thereof, the multiple buffer layers 101 are the first buffer layer 1011 and the second buffer layer, the first buffer layer 1011 is generated by adopting a PVD process, the second buffer layer is generated by adopting an MOCVD process, and the process temperature is selected to be 900-1200 ℃, so that the deep ultraviolet light-emitting element can effectively release lattice mismatch stress and thermal stress between the merging layer 102 and the substrate 100, reduce the surface problems of surface cracks, roughness, non-length and flatness and the like of the deep ultraviolet light-emitting element, reduce the defects and dislocation density of the buffer layers and the merging layer, and further improve the light-emitting efficiency of the deep ultraviolet light-emitting element to 5-10%.
In addition, it is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.
Claims (24)
1. A deep ultraviolet light-emitting element is characterized by comprising the following components in sequence from bottom to top: the semiconductor device comprises a substrate, multiple buffer layers, a merging layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer, wherein the multiple buffer layers comprise a first buffer layer and a second buffer layer positioned on the first buffer layer, the second buffer layer comprises at least two layers of structures with gradient growth temperatures, and the growth temperature of the second buffer layer is 900-1200 ℃.
2. The deep ultraviolet light emitting element according to claim 1, wherein the second buffer layer comprises a medium-temperature buffer layer and a high-temperature buffer layer on the medium-temperature buffer layer, and a growth temperature of the high-temperature buffer layer is higher than a growth temperature of the medium-temperature buffer layer.
3. The deep ultraviolet light emitting element according to claim 2, wherein the medium-temperature buffer layer is grown at a temperature of 900 to 1100 ℃.
4. The deep ultraviolet light emitting device of claim 2, wherein the high temperature buffer layer is grown at a temperature of 1100 ℃ to 1200 ℃.
5. The deep ultraviolet light emitting element according to claim 2, wherein the thickness of the medium-temperature buffer layer is 5nm to 100 nm.
6. The deep ultraviolet light emitting element according to claim 2, wherein the high temperature buffer layer has a thickness of 50nm to 500 nm.
7. The deep ultraviolet light emitting element of claim 1, wherein the first buffer layer and the second buffer layer are made of AlN.
8. The deep ultraviolet light emitting element according to claim 1, wherein a thickness of the first buffer layer is 5nm to 20 nm.
9. The deep ultraviolet light emitting element according to claim 1, wherein the merged layer merges the dispersed crystals of the multiple buffer layers by a two-dimensional lateral growth manner to obtain a flat surface.
10. The deep ultraviolet light emitting device of claim 1, wherein the merged layer comprises ain.
11. The deep ultraviolet light emitting element according to claim 1, wherein the growth temperature of the combined layer is 1200 ℃ to 1400 ℃.
12. A method for manufacturing a deep ultraviolet light-emitting element is characterized by comprising the following steps:
providing a substrate;
forming multiple buffer layers on the substrate, wherein the multiple buffer layers comprise a first buffer layer and a second buffer layer positioned on the first buffer layer, the second buffer layer comprises at least two layers of structures with gradient growth temperature, and the growth temperature of the second buffer layer is 900-1200 ℃;
forming a merged layer on the multiple buffer layers;
and sequentially forming an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer on the combined layer.
13. The method of claim 12, wherein the second buffer layer comprises a middle-temperature buffer layer and a high-temperature buffer layer on the middle-temperature buffer layer, and the growth temperature of the high-temperature buffer layer is higher than that of the middle-temperature buffer layer.
14. The method of claim 13, wherein the medium temperature buffer layer is grown at 900-1100 ℃.
15. The method according to claim 13, wherein the growth temperature of the high temperature buffer layer is 1100 ℃ to 1200 ℃.
16. The method of claim 13, wherein the thickness of the medium-temperature buffer layer is 5nm to 100 nm.
17. The method of claim 13, wherein the high temperature buffer layer has a thickness of 50nm to 500 nm.
18. The method according to claim 12, wherein the first buffer layer and the second buffer layer are made of AlN.
19. The method of claim 12, wherein the first buffer layer has a thickness of 5nm to 20 nm.
20. The method of manufacturing a deep ultraviolet light emitting element according to claim 12, wherein the merged layer merges the dispersed crystals of the multiple buffer layers by two-dimensional lateral growth to obtain a flat surface.
21. The method according to claim 12, wherein the merged layer comprises AlN.
22. The method according to claim 12, wherein the growth temperature of the merged layer is 1200 ℃ to 1400 ℃.
23. The method according to claim 12, wherein the process for forming the first buffer layer comprises a PVD process.
24. The method according to claim 12, wherein the process for forming the second buffer layer comprises an MOCVD process.
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