CN113394288A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113394288A
CN113394288A CN202010177583.0A CN202010177583A CN113394288A CN 113394288 A CN113394288 A CN 113394288A CN 202010177583 A CN202010177583 A CN 202010177583A CN 113394288 A CN113394288 A CN 113394288A
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layer
ions
forming
stress
semiconductor structure
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the surface of the substrate is provided with a pseudo gate structure; forming source and drain openings in the substrate at two sides of the dummy gate structure respectively; forming a first stress layer in the source drain opening, wherein first ions are doped in the first stress layer; forming an initial layer on the surface of the first stress layer, doping second ions in the initial layer, wherein the conductivity types of the first ions and the second ions are the same; and carrying out oxidation treatment on the initial layer to form an oxidation layer on the initial layer. The method is beneficial to improving the performance of the formed semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operation speed of the whole integrated circuit can be effectively increased.
In very large scale integrated circuits, the drive current of a transistor is typically increased by creating stress on the transistor, thereby increasing the carrier mobility of the transistor.
However, the performance of the semiconductor devices formed by the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the surface of the substrate is provided with a pseudo gate structure; source and drain openings respectively located in the substrate at two sides of the dummy gate structure; the first stress layer is positioned in the source drain opening, and first ions are doped in the first stress layer; and the oxide layer is positioned on the surface of the first stress layer, second ions are doped in the oxide layer, and the conductivity types of the first ions and the second ions are the same.
Optionally, when the semiconductor to be formed is a P-type device, the oxide layer includes: a silicon germanium oxide; when the semiconductor to be formed is an N-type device, the oxide layer comprises the following materials: carbon silicon oxide.
Optionally, the doping concentration of the second ions is less than the doping concentration of the first ions.
Optionally, the first ion and the second ion are the same or different.
Optionally, the first ion and the second ion are N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include: boron ion, indium ion, or BF2 +.
Optionally, the method further includes: and the first stress layer is positioned on the surface of the second stress layer and fills the source-drain opening.
Optionally, the second stress layer is doped with third ions, and the conductivity type of the third ions is the same as that of the first ions.
Optionally, the third ion is the same as or different from the first ion; the third ion is the same or different from the second ion; the doping concentration of the third ions is less than that of the first ions.
Optionally, when the semiconductor to be formed is a P-type device, the materials of the first stress layer and the second stress layer include: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the first stress layer and the second stress layer include: carbon and silicon.
Optionally, the oxide layer is further doped with stress enhancement ions, and when the semiconductor to be formed is a P-type device, the method includes: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method includes: a carbon ion.
Optionally, the interface between the bottom of the oxide layer and the top of the first stress layer is further doped with resistance-reducing ions, including: gallium ions.
Optionally, the method further includes: the stop barrier layer is positioned on the surface of the oxidation layer and the surface of the side wall of the pseudo gate structure; the dielectric layer is positioned on the surface of the stop barrier layer, and the top surface of the dielectric layer is higher than or flush with the top surface of the dummy gate structure; and the bottom of the conductive plug is positioned in the first stress layer.
Optionally, the dummy gate structure includes: the gate structure comprises a pseudo gate dielectric layer positioned on the surface of a substrate, a pseudo gate electrode layer positioned on the surface of the pseudo gate dielectric layer, and side walls positioned on the side wall surfaces of the pseudo gate dielectric layer and the pseudo gate electrode layer.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the surface of the substrate is provided with a pseudo gate structure; forming source and drain openings in the substrate at two sides of the dummy gate structure respectively; forming a first stress layer in the source drain opening, wherein first ions are doped in the first stress layer; forming an initial layer on the surface of the first stress layer, doping second ions in the initial layer, wherein the conductivity types of the first ions and the second ions are the same; and carrying out oxidation treatment on the initial layer to form an oxidation layer on the initial layer.
Optionally, the forming process of the initial layer includes: a selective epitaxial growth process; and doping second ions in the initial layer by adopting an in-situ ion doping process.
Optionally, when the semiconductor to be formed is a P-type device, the material of the initial layer includes: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the initial layers include: carbon germanium.
Optionally, the parameters of the oxidation treatment include: the temperature range is 600 ℃ to 800 ℃, the treatment time is 20 minutes to 60 minutes, and the oxygen atmosphere comprises the following gases: oxygen or ozone.
Optionally, the forming process of the first stress layer includes: a selective epitaxial growth process; and doping first ions in the first stress layer by adopting an in-situ ion doping process.
Optionally, the method further includes: after the source and drain openings are formed and before the first stress layer is formed, forming second stress layers on the surface of the side wall and the surface of the bottom of the source and drain opening; and after the second stress layer is formed, forming the first stress layer on the surface of the second stress layer, wherein the source and drain openings are filled with the first stress layer.
Optionally, the forming process of the second stress layer includes: a selective epitaxial growth process; and doping third ions in the second stress layer by adopting an in-situ ion doping process.
Optionally, the method further includes: doping stress enhancement ions in the oxide layer, wherein when the semiconductor to be formed is a P-type device, the method comprises the following steps: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method includes: a carbon ion.
Optionally, the method further includes: doping resistance reducing ions at an interface of the bottom of the oxide layer and a top surface of the first stress layer, comprising: gallium ions.
Optionally, the method for forming the source/drain opening includes: and etching the substrate by taking the pseudo gate structure as a mask to form the source and drain openings.
Optionally, the method further includes: forming a stop barrier layer on the surface of the oxidation layer and the surface of the side wall of the pseudo gate structure; forming a dielectric layer on the surface of the stop barrier layer, wherein the top surface of the dielectric layer is higher than or flush with the top surface of the dummy gate structure; and forming a conductive plug in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, wherein the bottom of the conductive plug is positioned in the first stress layer.
Optionally, the forming method of the conductive plug includes: forming a through hole in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, wherein the bottom of the through hole is exposed out of the first stress layer; forming a conductive material film in the through hole and on the surface of the dielectric layer; and flattening the conductive material film until the surface of the dielectric layer is exposed to form the conductive plug.
Optionally, the method for forming the dummy gate structure includes: forming a pseudo gate dielectric film on the surface of the substrate; forming a pseudo gate electrode film on the surface of the pseudo gate dielectric film; patterning the pseudo gate dielectric film and the pseudo gate electrode film until the surface of the substrate is exposed, so that the pseudo gate dielectric film forms a pseudo gate dielectric layer, and the pseudo gate electrode film forms a pseudo gate electrode; forming a side wall material film on the top surface and the side wall surface of the pseudo gate electrode layer and the side wall surface of the pseudo gate dielectric layer; and etching the side wall material film back until the surface of the substrate is exposed, and forming side walls on the side wall surfaces of the pseudo gate dielectric layer and the pseudo gate electrode layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the initial layer is oxidized to form an oxide layer. On one hand, the oxide layer formed after the oxidation treatment can still effectively protect the first stress layer, so that the stress of the first stress layer is not released in the subsequent heat treatment process. On the other hand, the second ions are not easy to diffuse in the oxidation layer and further are not easy to diffuse into a channel below the pseudo gate structure, so that the short channel effect is effectively improved, and the performance of the formed semiconductor structure is better.
Further, doping stress enhancement ions in the oxide layer, when the semiconductor to be formed is a P-type device, includes: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method includes: a carbon ion. By doping the stress enhancing ions, the stress of the oxide layer can be increased, namely, the stress of the oxide layer on a channel is increased, so that the driving current of the semiconductor structure is improved, and the formed semiconductor structure has better performance.
Further, resistance reducing ions are doped at the interface of the bottom of the oxide layer and the top surface of the first stress layer. Due to the doping of the resistance reducing ions, ohmic contact can be formed between the subsequently formed conductive plug and the first stress layer positioned in the source drain opening, so that the contact resistance between the first stress layer and the conductive plug is reduced, and the performance of the formed semiconductor structure is improved.
Drawings
FIGS. 1-4 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 5 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of existing semiconductor structures is poor.
The reason for the poor performance of the semiconductor structure will be described in detail below with reference to the accompanying drawings, and fig. 1 to 4 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, wherein a dummy gate structure 110 is disposed on a surface of the substrate 100, and spacers 120 are disposed on two sides of the dummy gate structure 110.
Referring to fig. 2, source-drain openings 130 are formed in the substrate 100 at two sides of the dummy gate structure 110 and the sidewall spacers 120.
Referring to fig. 3, a first stress layer 140 is formed on the bottom and sidewall surfaces of the source/drain opening 130; and forming a second stress layer 150 on the surface of the first stress layer 140.
Referring to fig. 4, a protection layer 160 is formed on the surface of the second stress layer 150.
In the above method, the first stress layer 140 and the second stress layer 150 together form a source-drain doped region. The protective layer 160 on the surface of the second stress layer 150 can effectively reduce the release of stress caused by heating the source/drain doped region, especially the second stress layer 150, in the subsequent thermal process. Therefore, the protection layer 160 is beneficial to maintain the stress of the source and drain doped regions.
However, the formation process of the protection layer 160 is a selective epitaxial growth process, and ions are doped in the protection layer 160 using an in-situ ion doping process. Specifically, the material of the protection layer 160 is formed of silicon germanium, and the concentration of germanium in the silicon germanium material is low, so that doped ions are easily diffused in the protection layer 160 with low germanium concentration, and further easily diffused into a channel below the dummy gate structure 110, thereby causing a short channel effect, and making the performance of the semiconductor structure poor.
The concentration of germanium in the silicon germanium material refers to the ratio of the amount of germanium species to the amount of silicon species.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which an initial layer is formed on a surface of a first stressed layer, and second ions are doped in the initial layer, and conductivity types of the first ions and the second ions are the same; and carrying out oxidation treatment on the initial layer to form an oxidation layer on the initial layer. The second ions are not easy to diffuse in the oxide layer, so that the performance of the formed semiconductor structure is better.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 5, a substrate 200 is provided, and a dummy gate structure 210 is formed on a surface of the substrate 200.
In this embodiment, the substrate 200 includes a substrate and a fin portion located on a surface of the substrate, and the dummy gate structure 210 crosses the fin portion and covers a portion of a top surface and a sidewall surface of the fin portion.
In other embodiments, the substrate does not have fins thereon.
In this embodiment, the method for forming the substrate 200 includes: providing an initial substrate (not shown); the initial substrate is provided with a first patterning layer, and the first patterning layer exposes a part of the surface of the initial substrate; and etching the initial substrate by taking the first patterning layer as a mask to form the substrate 201 and the fin part positioned on the surface of the substrate.
In this embodiment, the material of the initial substrate is silicon. Correspondingly, the material of the substrate and the fin portion is silicon.
In other embodiments, the material of the initial substrate comprises: germanium, silicon on insulator or germanium on insulator. Accordingly, the material of the substrate comprises: germanium, silicon on insulator or germanium on insulator. The material of the fin portion includes: germanium, silicon on insulator or germanium on insulator.
In this embodiment, the dummy gate structure 210 includes: the gate structure comprises a dummy gate dielectric layer 211 positioned on the surface of the substrate 200, a dummy gate electrode layer 212 positioned on the surface of the dummy gate dielectric layer 211, and side walls 213 positioned on the side wall surfaces of the dummy gate dielectric layer 211 and the dummy gate electrode layer 212.
In other embodiments, the dummy gate structure does not include the sidewall.
The method for forming the dummy gate structure 210 includes: forming a pseudo gate dielectric film (not shown in the figure) on the surface of the substrate; forming a dummy gate electrode film (not shown in the figure) on the surface of the dummy gate dielectric film; patterning the pseudo gate dielectric film and the pseudo gate electrode film until the surface of the substrate is exposed, so that the pseudo gate dielectric film forms a pseudo gate dielectric layer 211, and the pseudo gate electrode film forms a pseudo gate electrode 212; forming a side wall material film on the top surface and the side wall surface of the dummy gate electrode layer 212 and the side wall surface of the dummy gate dielectric layer 211; and etching the side wall material film back until the surface of the substrate is exposed, and forming side walls 213 on the side wall surfaces of the pseudo gate dielectric layer 211 and the pseudo gate electrode layer 212.
In this embodiment, the method for forming a semiconductor structure further includes: a barrier layer (not shown) is formed on the top surface of the dummy gate structure 210.
The barrier layer is used to protect the surface of the dummy gate structure 210 from the process in the subsequent process steps, thereby maintaining a good profile.
Referring to fig. 6, source-drain openings 220 are formed in the substrate 200 at two sides of the dummy gate structure 210, respectively.
The source-drain opening 220 provides a space for the subsequent formation of a first stress layer and a second stress layer.
Specifically, in this embodiment, the source/drain openings 220 are located in the fin portions on two sides of the dummy gate structure 210.
The method for forming the source/drain opening 220 includes: and etching the substrate by taking the pseudo gate structure as a mask to form the source-drain opening 200.
In this embodiment, the process of etching the substrate 200 includes: and (5) anisotropic dry etching.
Referring to fig. 7, a second stress layer 230 is formed on the sidewall surface and the bottom surface of the source/drain opening 220.
The forming process of the second stress layer 230 includes: a selective epitaxial growth process; and doping third ions in the second stress layer 230 by using an in-situ ion doping process.
When the semiconductor to be formed is a P-type device, the materials of the second stress layer 230 include: silicon germanium; when the semiconductor to be formed is an N-type device, the second stress layer 230 comprises: carbon germanium.
The third ions are N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include: boron ion, indium ion or BF2+。
In this embodiment, the semiconductor to be formed is a P-type device, the material forming the second stress layer 230 is silicon germanium, the doped third ions are boron, the concentration of germanium in the silicon germanium material is 0.1-0.3, and the concentration of boron ions is 1e18 atm/cm3～1e19atm/cm3。
Because the concentration of germanium in the silicon germanium material is low, the stress of the second stress layer 230 is low, and a good buffer effect can be achieved between the substrate 200 and the first stress layer with a larger size formed later.
Referring to fig. 8, after the second stress layer 230 is formed, a first stress layer 240 is formed on the surface of the second stress layer 230, and the source/drain openings 220 (shown in fig. 6) are filled with the first stress layer 240.
The first stress layer 240 and the second stress layer 230 are used together as a source-drain doped region.
The formation process of the first stress layer 240 includes: a selective epitaxial growth process; first ions are doped in the first stress layer 240 using an in-situ ion doping process.
When the semiconductor to be formed is a P-type device, the materials of the first stress layer 240 include: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the first stress layer 240 include: carbon germanium.
The first and third ions have the same conductivity type.
The first ions are N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include: boron ion, indium ion or BF2+。
The first and third ions may be the same or different. In this embodiment, the first ions and the third ions are the same and are boron ions.
In this embodiment, the material of the first stressor layer 240 is silicon germanium, the doped first ions are boron ions, the concentration of germanium in the silicon germanium material is 0.4-0.6, and the concentration of boron ions is 1e20atm/cm3～1e21atm/cm3。
The germanium concentration in the silicon germanium material of the first stress layer 240 is high, the first stress layer 240 occupies the main volume of the source/drain opening 220, and the first stress layer 240 has high stress on the channel, so that the first stress layer 240 and the second stress layer 230 in the source/drain opening 220 are jointly used as a source/drain doping region, and have high stress on the channel, which is beneficial to enhancing the migration rate of carriers, improving the driving current of a semiconductor device, and improving the response speed of a circuit.
Referring to fig. 9, an initial layer 250 is formed on the surface of the first stress layer 240, and the initial layer 250 is doped with second ions, wherein the first ions and the second ions have the same conductivity type.
The initiation layer 250 can protect the first stressor layer 240 located at the bottom of the initiation layer 250, and effectively prevent the first stressor layer 240 from stress release caused by heating in a subsequent thermal process.
When the semiconductor to be formed is a P-type device, the materials of the initial layer 250 include: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the initial layer 250 include: carbon germanium.
In the present embodiment, the material of the initiation layer 250 is silicon germanium.
The second ions are N-type ions or P-type ions.
The N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include: boron ion, indium ion or BF2+。
The second ion and the first ion are the same or different.
In this embodiment, the first ions and the second ions are the same and are boron ions.
In the embodiment, the material in the initiation layer 250 is silicon germanium, the doped first ions are boron ions, the concentration of germanium in the silicon germanium material is 0.1-0.2, and the concentration of boron ions is 5e19atm/cm3～5e20atm/cm3。
The doping concentration of the second ions is less than that of the first ions.
Referring to fig. 10, the initial layer 250 is oxidized to form an oxide layer 260 on the initial layer 250.
The parameters of the oxidation treatment include: the temperature range is 600 ℃ to 800 ℃, the treatment time is 20 minutes to 60 minutes, and the oxygen atmosphere comprises the following gases: oxygen or ozone.
By the oxidation treatment, the material of the initial layer 250 is oxidized.
When the semiconductor to be formed is a P-type device, the oxide layer comprises the following materials: a silicon germanium oxide; when the semiconductor to be formed is an N-type device, the oxide layer comprises the following materials: carbon silicon oxide.
In this embodiment, the material of the oxide layer 260 is silicon germanium oxide, and the oxide layer 260 is doped with second ions, boron ions.
The initial layer 250 is oxidized to form an oxide layer 260 on the initial layer 250. On one hand, the oxide layer 260 formed after the oxidation treatment can still effectively protect the first stress layer 240, so that the stress of the first stress layer 240 is not released in the subsequent thermal treatment process. On the other hand, the second ions are not easy to diffuse in the oxide layer 260, and further are not easy to diffuse into the channel below the dummy gate structure 210, so that the short channel effect is effectively improved, and the performance of the formed semiconductor structure is better.
Referring to fig. 11, the oxide layer 260 is doped with stress enhancing ions, and when the semiconductor to be formed is a P-type device, the method includes: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method includes: a carbon ion; doping resistance reducing ions at the interface of the bottom of the oxide layer 260 and the top surface of the first stress layer, including: gallium ions.
By doping the stress enhancing ions, the stress of the oxide layer 260 can be increased, that is, the stress of the oxide layer 260 on a channel is increased, so that the driving current of the semiconductor structure is increased, and the performance of the formed semiconductor structure is better.
The interface between the bottom of the oxide layer 260 and the top surface of the first stress layer 240 is doped with resistance reducing ions. Due to the doping of the resistance reducing ions, ohmic contact can be formed between the subsequently formed conductive plug and the first stress layer 240 positioned in the source-drain opening, so that the contact resistance between the first stress layer 240 and the conductive plug is reduced, and the performance of the formed semiconductor structure is improved.
In this embodiment, the process of doping the stress enhancing ions and the process of doping the resistance reducing ions are implemented by simultaneously performing an ion implantation process.
In this embodiment, after doping the stress enhancing ions and doping the resistance reducing ions, the method further includes: and (6) heat treatment. By means of the heat treatment, on the one hand, for activating the stress-enhancing ions and the resistance-reducing ions and, on the other hand, for repairing lattice damage.
Referring to fig. 12, a stop barrier layer 271 is formed on the surface of the oxide layer 260 and the surface of the sidewall of the dummy gate structure 210; a dielectric layer 272 is formed on the surface of the stop barrier layer 271, and the top surface of the dielectric layer 272 is higher than or flush with the top surface of the dummy gate structure 210.
The stop barrier 271 is used as a stop layer for subsequent etching.
The dielectric layer 272 is used to provide support for subsequently formed devices.
The material of the stop barrier 271 is different from the material of the dielectric layer 272. In this embodiment, the stop barrier layer 271 is made of silicon nitride; the dielectric layer 272 is made of silicon oxide.
Referring to fig. 13, a conductive plug 280 is formed in the dielectric layer 272, the stop barrier layer 271, the oxide layer 260 and the first stress layer 250, and the bottom of the conductive plug 280 is located in the first stress layer 250.
The conductive plug 280 is used to electrically connect the source-drain doped region with a peripheral circuit.
The method for forming the conductive plug 280 includes: forming a via (not shown) in the dielectric layer 272, the stop barrier layer 271, the oxide layer 260 and the first stress layer 240, and exposing the first stress layer 240 at the bottom of the via; forming a conductive material film (not shown) in the through hole and on the surface of the dielectric layer 272; the conductive material film is planarized until the surface of the dielectric layer 272 is exposed, forming the conductive plug 280.
Because the interface between the bottom of the oxide layer 260 and the top surface of the first stress layer 240 is doped with the resistance reducing ions, ohmic resistance is formed between the contact surfaces of the conductive plug 280 and the first stress layer 240 as well as the oxide layer 260, the contact resistance is effectively reduced, and the formed semiconductor structure has better performance.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 13, including: the substrate 200, the surface of the substrate 200 has a dummy gate structure 210; source and drain openings 220 (shown in fig. 6) in the substrate 200 respectively located at two sides of the dummy gate structure 210; a first stress layer 240 located in the source-drain opening 220, wherein first ions are doped in the first stress layer 240; the oxide layer 250 is located on the surface of the first stress layer 240, and the oxide layer 250 is doped with second ions, where the first ions and the second ions have the same conductivity type.
The following detailed description is made with reference to the accompanying drawings.
In this embodiment, the substrate 200 includes a substrate and a fin portion located on a surface of the substrate, and the dummy gate structure 210 crosses the fin portion and covers a portion of a top surface and a sidewall surface of the fin portion.
In other embodiments, the substrate does not have fins thereon.
In this embodiment, the dummy gate structure 210 includes: the gate structure comprises a dummy gate dielectric layer 211 positioned on the surface of the substrate 200, a dummy gate electrode layer 212 positioned on the surface of the dummy gate dielectric layer 211, and side walls 213 positioned on the side wall surfaces of the dummy gate dielectric layer 211 and the dummy gate electrode layer 212.
When the semiconductor to be formed is a P-type device, the oxide layer 260 comprises the following materials: a silicon germanium oxide; when the semiconductor to be formed is an N-type device, the oxide layer 260 comprises the following materials: carbon silicon oxide.
The doping concentration of the second ions is less than that of the first ions.
The first and second ions are the same or different.
The first ions and the second ions are N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include: boron ion, indium ion or BF2+。
In this embodiment, the first ion and the second ion are the same and both are boron ions.
The semiconductor structure further includes: and the second stress layer 230 is positioned on the surface of the sidewall and the surface of the bottom of the source-drain opening 220, and the first stress layer 240 is positioned on the surface of the second stress layer 230 and is filled in the source-drain opening 220.
The second stress layer 230 is doped with third ions, and the conductivity type of the third ions is the same as that of the first ions.
The third ion is the same or different from the first ion; the third ion is the same or different from the second ion; the doping concentration of the third ions is less than that of the first ions.
When the semiconductor to be formed is a P-type device, the materials of the first stress layer 240 and the second stress layer 230 include: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the first stress layer 240 and the second stress layer 230 include: carbon and silicon.
The oxide layer 260 is further doped with stress enhancing ions, and when the semiconductor to be formed is a P-type device, the method includes: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method includes: a carbon ion.
The interface between the bottom of the oxide layer 260 and the top of the first stress layer 240 is further doped with resistance reducing ions, including: gallium ions.
The semiconductor structure further includes: a stop barrier layer 271 located on the surface of the oxide layer 260 and the surface of the sidewall of the dummy gate structure 210; the dielectric layer 272 is positioned on the surface of the stop barrier layer 271, and the top surface of the dielectric layer 272 is higher than or flush with the top surface of the dummy gate structure 210; the conductive plug 280 is located in the dielectric layer 272, the stop barrier layer 271, the oxide layer 260 and the first stress layer 240, and the bottom of the conductive plug 280 is located in the first stress layer 240.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (26)

1. A semiconductor structure, comprising:
the surface of the substrate is provided with a pseudo gate structure;
source and drain openings respectively located in the substrate at two sides of the dummy gate structure;
the first stress layer is positioned in the source drain opening, and first ions are doped in the first stress layer;
and the oxide layer is positioned on the surface of the first stress layer, second ions are doped in the oxide layer, and the conductivity types of the first ions and the second ions are the same.
2. The semiconductor structure of claim 1, wherein when the semiconductor to be formed is a P-type device, the oxide layer comprises: a silicon germanium oxide; when the semiconductor to be formed is an N-type device, the oxide layer comprises the following materials: carbon silicon oxide.
3. The semiconductor structure of claim 1, wherein the second ions have a doping concentration less than the doping concentration of the first ions.
4. The semiconductor structure of claim 1, wherein the first ions and the second ions are the same or different.
5. The semiconductor structure of claim 1, wherein the first and second ions are N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include: boron ion, indium ion or BF2+。
6. The semiconductor structure of claim 1, further comprising: and the first stress layer is positioned on the surface of the second stress layer and fills the source-drain opening.
7. The semiconductor structure of claim 6, wherein the second stressed layer is doped with third ions having a conductivity type that is the same as the first ions.
8. The semiconductor structure of claim 6, wherein the third ions are the same or different from the first ions; the third ion is the same or different from the second ion; the doping concentration of the third ions is less than that of the first ions.
9. The semiconductor structure of claim 6, wherein when the semiconductor to be formed is a P-type device, the materials of the first stress layer and the second stress layer comprise: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the first stress layer and the second stress layer include: carbon and silicon.
10. The semiconductor structure of claim 1, wherein the oxide layer is further doped with stress enhancing ions, and when the semiconductor to be formed is a P-type device, the method comprises: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method includes: a carbon ion.
11. The semiconductor structure of claim 1, wherein an interface between a bottom of the oxide layer and a top of the first stress layer is further doped with resistance-reducing ions, comprising: gallium ions.
12. The semiconductor structure of claim 1, further comprising: the stop barrier layer is positioned on the surface of the oxidation layer and the surface of the side wall of the pseudo gate structure; the dielectric layer is positioned on the surface of the stop barrier layer, and the top surface of the dielectric layer is higher than or flush with the top surface of the dummy gate structure; and the bottom of the conductive plug is positioned in the first stress layer.
13. The semiconductor structure of claim 1, wherein the dummy gate structure comprises: the gate structure comprises a pseudo gate dielectric layer positioned on the surface of a substrate, a pseudo gate electrode layer positioned on the surface of the pseudo gate dielectric layer, and side walls positioned on the side wall surfaces of the pseudo gate dielectric layer and the pseudo gate electrode layer.
14. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the surface of the substrate is provided with a pseudo gate structure;
forming source and drain openings in the substrate at two sides of the dummy gate structure respectively;
forming a first stress layer in the source drain opening, wherein first ions are doped in the first stress layer;
forming an initial layer on the surface of the first stress layer, doping second ions in the initial layer, wherein the conductivity types of the first ions and the second ions are the same;
and carrying out oxidation treatment on the initial layer to form an oxidation layer on the initial layer.
15. The method of forming a semiconductor structure of claim 14, wherein the forming of the initiation layer comprises: a selective epitaxial growth process; and doping second ions in the initial layer by adopting an in-situ ion doping process.
16. The method of claim 14, wherein when the semiconductor to be formed is a P-type device, the initial layer comprises: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the initial layers include: carbon germanium.
17. The method of forming a semiconductor structure of claim 14, wherein the parameters of the oxidation process comprise: the temperature range is 600 ℃ to 800 ℃, the treatment time is 20 minutes to 60 minutes, and the oxygen atmosphere comprises the following gases: oxygen or ozone.
18. The method of forming a semiconductor structure of claim 14, wherein the forming of the first stress layer comprises: a selective epitaxial growth process; and doping first ions in the first stress layer by adopting an in-situ ion doping process.
19. The method of forming a semiconductor structure of claim 14, further comprising: after the source and drain openings are formed and before the first stress layer is formed, forming second stress layers on the surface of the side wall and the surface of the bottom of the source and drain opening; and after the second stress layer is formed, forming the first stress layer on the surface of the second stress layer, wherein the source and drain openings are filled with the first stress layer.
20. The method for forming the semiconductor structure according to claim 19, wherein the forming process of the second stress layer comprises: a selective epitaxial growth process; and doping third ions in the second stress layer by adopting an in-situ ion doping process.
21. The method of forming a semiconductor structure of claim 14, further comprising: doping stress enhancement ions in the oxide layer, wherein when the semiconductor to be formed is a P-type device, the method comprises the following steps: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method includes: a carbon ion.
22. The method of forming a semiconductor structure of claim 14, further comprising: doping resistance reducing ions at an interface of the bottom of the oxide layer and a top surface of the first stress layer, comprising: gallium ions.
23. The method for forming the semiconductor structure according to claim 14, wherein the method for forming the source and drain openings comprises: and etching the substrate by taking the pseudo gate structure as a mask to form the source and drain openings.
24. The method of forming a semiconductor structure of claim 14, further comprising: forming a stop barrier layer on the surface of the oxidation layer and the surface of the side wall of the pseudo gate structure; forming a dielectric layer on the surface of the stop barrier layer, wherein the top surface of the dielectric layer is higher than or flush with the top surface of the dummy gate structure; and forming a conductive plug in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, wherein the bottom of the conductive plug is positioned in the first stress layer.
25. The method of forming a semiconductor structure of claim 24, wherein the method of forming the conductive plug comprises: forming a through hole in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, wherein the bottom of the through hole is exposed out of the first stress layer; forming a conductive material film in the through hole and on the surface of the dielectric layer; and flattening the conductive material film until the surface of the dielectric layer is exposed to form the conductive plug.
26. The method of forming a semiconductor structure of claim 14, wherein the method of forming the dummy gate structure comprises: forming a pseudo gate dielectric film on the surface of the substrate; forming a pseudo gate electrode film on the surface of the pseudo gate dielectric film; patterning the pseudo gate dielectric film and the pseudo gate electrode film until the surface of the substrate is exposed, so that the pseudo gate dielectric film forms a pseudo gate dielectric layer, and the pseudo gate electrode film forms a pseudo gate electrode; forming a side wall material film on the top surface and the side wall surface of the pseudo gate electrode layer and the side wall surface of the pseudo gate dielectric layer; and etching the side wall material film back until the surface of the substrate is exposed, and forming side walls on the side wall surfaces of the pseudo gate dielectric layer and the pseudo gate electrode layer.
CN202010177583.0A 2020-03-13 2020-03-13 Semiconductor structure and forming method thereof Pending CN113394288A (en)

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US20130207166A1 (en) * 2012-02-10 2013-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition
CN105280492A (en) * 2014-07-21 2016-01-27 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure
CN108074820A (en) * 2016-11-10 2018-05-25 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN110534433A (en) * 2018-05-25 2019-12-03 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130207166A1 (en) * 2012-02-10 2013-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Doped SiGe Source/Drain Stressor Deposition
CN105280492A (en) * 2014-07-21 2016-01-27 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure
CN108074820A (en) * 2016-11-10 2018-05-25 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN110534433A (en) * 2018-05-25 2019-12-03 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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