CN113394215A - Fin formula field effect transistor standard cell structure - Google Patents

Fin formula field effect transistor standard cell structure Download PDF

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Publication number
CN113394215A
CN113394215A CN202110600440.0A CN202110600440A CN113394215A CN 113394215 A CN113394215 A CN 113394215A CN 202110600440 A CN202110600440 A CN 202110600440A CN 113394215 A CN113394215 A CN 113394215A
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China
Prior art keywords
fins
fin
dummy
standard cell
cell structure
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CN202110600440.0A
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Chinese (zh)
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202110600440.0A priority Critical patent/CN113394215A/en
Publication of CN113394215A publication Critical patent/CN113394215A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention relates to a fin field effect transistor standard unit structure, which relates to a semiconductor integrated circuit structure and comprises a plurality of effective fin areas, wherein each effective fin area comprises a plurality of effective fins which are arranged in the same direction; at least one dummy fin region, the dummy fin region including a plurality of dummy fins arranged in the same direction, the dummy fin region separating two adjacent effective fin regions; the polycrystalline silicon is arranged in the same direction and is intersected with the effective fins and the virtual fins, and the intersection regions of the polycrystalline silicon and the effective fins form gate regions of the fin field effect transistors; the space between two adjacent effective fins is a, the space between two adjacent dummy fins is b, and b is smaller than a, so as to reduce the area of the standard unit of the fin field effect transistor.

Description

Fin formula field effect transistor standard cell structure
Technical Field
The present invention relates to semiconductor integrated circuit fabrication technologies, and more particularly, to a fin field effect transistor standard cell structure and device.
Background
The finfet is a new cmos transistor named because the shape of the transistor is similar to a fin. By using this fin-like design, circuit control is improved, leakage current of the transistor is reduced, and the gate length of the transistor is shortened.
Referring to fig. 1, fig. 1 shows a schematic top view of a norfly fin field Effect Transistor (FinFET) standard cell. As shown in fig. 1, it may have a multi-layer structure, which includes, from bottom to top, a fin including an Active fin area and a dummy fin area, the dummy fin area separating two adjacent Active fin areas, wherein the Active fin area includes an Active fin 11(Active Fins), and the dummy fin area includes a dummy fin 12(dummy Fins). The finfet standard cell further includes a metal 0 layer, where the metal 0 layer further includes M0A14 and M0P 15, the active fins 11 of the active fin area are connected together with M0A14, and the M0a14 is connected to the metal layer 15 through a contact level layer. The area a of the finfet standard cell is cell. With the development of semiconductor technology, device miniaturization is a development trend in the industry. In order to reduce the area of the standard cell of the fin field effect transistor, at present, a Double Diffusion Break (DDB) process is mainly adopted to be changed into a Single Diffusion Break (SDB) process, so as to reduce the size of the effective fin 11 or the dummy fin 12. Fig. 2 shows a schematic top view of a nadnreflash finfet standard cell. Fig. 3 shows a schematic top view of an Inverter (Inverter) finfet standard cell. The standard cells shown in fig. 2 and 3 are the same as those shown in fig. 1 and will not be described again.
Disclosure of Invention
The invention provides a fin field effect transistor standard unit structure, which comprises: a plurality of active fin regions, each active fin region comprising a plurality of active fins arranged in a same direction; at least one dummy fin region, the dummy fin region including a plurality of dummy fins arranged in the same direction, the dummy fin region separating two adjacent effective fin regions; the polycrystalline silicon is arranged in the same direction and is intersected with the effective fins and the virtual fins, and the intersection regions of the polycrystalline silicon and the effective fins form gate regions of the fin field effect transistors; the distance between two adjacent effective fins is a, the distance between two adjacent dummy fins is b, and b is smaller than a.
Furthermore, the spacing a between two adjacent effective fins is the standard fin spacing.
Furthermore, the distance b between two adjacent dummy fins is any value between 1nm and 30 nm.
Further, the distance a between two adjacent effective fins is made larger than the distance b between two adjacent dummy fins by setting the size of the mandrels for forming the inter-dummy fin space smaller than the size of the mandrels for forming the effective inter-fin space.
Further, each dummy fin region includes two dummy fins.
Furthermore, it is characterized in that a plurality of effective fins are arranged in parallel; a plurality of dummy fins are arranged in parallel; and a plurality of polysilicon strips are arranged in parallel.
Furthermore, the finfet standard cell structure further includes: a metal 0 layer, the metal 0 layer including M0A, the active fins of the active fin region connected together with M0A.
Further, the M0A is connected to the metal layer through a contact hole layer.
Furthermore, the FinFET standard cell is used to form NORFlash, an inverter or NADNFlash.
Drawings
Fig. 1 shows a schematic top view of a norfly fin field Effect Transistor (FinFET) standard cell.
Fig. 2 shows a schematic top view of a nadnreflash finfet standard cell.
Fig. 3 shows a schematic top view of an Inverter (Inverter) finfet standard cell.
Fig. 4 is a top view of a finfet standard cell structure according to an embodiment of the invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the standard cell shown in fig. 1, 2 and 3, the dummy Fin region between two adjacent active Fin regions includes two dummy fins 12, and the spacing between two adjacent dummy fins 12 is equal to the spacing between two adjacent active fins 11, both being a, which is a standard Fin pitch (standard Fin pitch), such as 48nm,33nm and 24nm etc., and is set according to the critical dimension of the device. The distance of the dummy fin region formed by the two dummy fins 12 can satisfy the gate connection (gate contact plating) and the size of the gate-wrapped fin in the gate direction. The number of dummy fins 12 can be reduced from two to 1 in order to reduce the finfet standard cell size, but if only one dummy fin 12 is included, the dummy fin area distance cannot meet the device requirements.
The application provides a fin field effect transistor standard cell structure. Fig. 4 is a schematic top view of a finfet standard cell structure according to an embodiment of the invention. The method comprises the following steps:
a plurality of active fin regions 200, each active fin region 200 comprising a plurality of active fins 21, the plurality of active fins 21 being arranged in the same direction;
at least one dummy fin region 300, the dummy fin region 300 comprising a plurality of dummy fins 22, the plurality of dummy fins 22 being arranged in a same direction, and the dummy fin region 300 separating two adjacent active fin regions 200;
a plurality of polysilicon 23, the plurality of polysilicon 23 being arranged in the same direction and crossing the active fin 21 and the dummy fin 22, wherein the crossing region of the polysilicon 23 and the active fin 21 forms a gate region of the finfet; wherein
The spacing between two adjacent effective fins 21 is a, the spacing between two adjacent dummy fins 22 is b, and b is smaller than a.
Thus, without changing the finfet standard cell structure, the cell.h value can be reduced relative to the finfet standard cell structure of the prior art shown in fig. 1, thereby correspondingly reducing the area of the finfet standard cell. And has little influence on the manufacturing process of the standard unit of the fin field effect transistor.
Specifically, in one embodiment, the spacing a between two adjacent effective fins 21 is a standard Fin pitch (standard Fin pitch), such as 48nm,33nm, and 24nm etc., which is set according to the critical dimension of the device. And, the spacing b between two adjacent dummy fins 22 is smaller than the standard fin spacing. Specifically, in one embodiment, the distance b between two adjacent dummy fins 22 is any value between 1nm and 30 nm.
In one embodiment, the distance a between two adjacent effective fins 21 is larger than the distance b between two adjacent dummy fins 22 by setting the size of the Mandrel (Mandrel) for forming the space between the dummy fins 22 to be smaller than the size of the Mandrel (Mandrel) for forming the space between the effective fins 21. The Mandrel (Mandrel) used to form the spacing between the active fins 21 is still a standard dimension that is set by the critical dimensions of the device. Therefore, the performance of the FinFET standard cell device is not affected. The effect of reducing the area of the fin field effect transistor standard unit is achieved, and the trend of miniaturization of devices is complied with.
In one embodiment, each dummy fin region 300 includes two dummy fins 22, as shown in fig. 4.
In one embodiment, a plurality of active fins 21 are arranged in parallel; a plurality of dummy fins 22 are arranged in parallel; and a plurality of polysilicon 23 are arranged in parallel.
Further, in one embodiment, the finfet standard cell structure further comprises: a metal 0 layer, the metal 0 layer including M0A24, the active fins 21 of the active fin region connected together with M0A 24. And the M0a24 is connected to metal layer 25 through a contact hole layer.
In one embodiment, the finfet standard cell described above is used to form NORFlash. In one embodiment, the finfet standard cell described above is used to form an Inverter (Inverter). In an embodiment, the finfet standard cell is used to form nadnreflash. Or the finfet standard cell described above, may be used to form any other IP cell.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A fin field effect transistor standard cell structure, comprising:
a plurality of active fin regions, each active fin region comprising a plurality of active fins arranged in a same direction;
at least one dummy fin region, the dummy fin region including a plurality of dummy fins arranged in the same direction, the dummy fin region separating two adjacent effective fin regions;
the polycrystalline silicon is arranged in the same direction and is intersected with the effective fins and the virtual fins, and the intersection regions of the polycrystalline silicon and the effective fins form gate regions of the fin field effect transistors; wherein
The distance between two adjacent effective fins is a, the distance between two adjacent dummy fins is b, and b is smaller than a.
2. The standard cell structure of claim 1, wherein the distance a between two adjacent active fins is a standard fin pitch.
3. The FinFET standard cell structure of claim 1, wherein the spacing b between two adjacent dummy fins is any value between 1nm and 30 nm.
4. The FinFET standard cell structure of claim 3, wherein a spacing a between two adjacent active fins is greater than a spacing b between two adjacent dummy fins by setting a size of a mandrel used to form the inter-dummy fin spacing to be smaller than a size of a mandrel used to form the active inter-fin spacing.
5. The finfet standard cell structure of claim 1, wherein each dummy fin region comprises two dummy fins.
6. The FinFET standard cell structure of claim 5, wherein the plurality of active fins are arranged in parallel; a plurality of dummy fins are arranged in parallel; and a plurality of polysilicon strips are arranged in parallel.
7. The FinFET standard cell structure of claim 1, further comprising: a metal 0 layer, the metal 0 layer including M0A, the active fins of the active fin region connected together with M0A.
8. The finfet standard cell structure of claim 7, wherein the M0A is connected to the metal layer through a contact hole layer.
9. The FinFET standard cell structure of claim 1, wherein the FinFET standard cell is used to form NORFlash, an inverter, or NADNFlash.
CN202110600440.0A 2021-05-31 2021-05-31 Fin formula field effect transistor standard cell structure Pending CN113394215A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140097493A1 (en) * 2012-10-09 2014-04-10 Samsung Electronics Co., Ltd. Cells including at least one fin field effect transistor and semiconductor integrated circuits including the same
TW201419451A (en) * 2012-11-14 2014-05-16 Taiwan Semiconductor Mfg SRAM cell array and method for manufacturing the same
US20160098508A1 (en) * 2014-10-01 2016-04-07 Sang-hoon BAEK Method and system for designing semiconductor device
US20170061056A1 (en) * 2015-09-02 2017-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Cell grid architecture for finfet technology
US20190189457A1 (en) * 2017-12-14 2019-06-20 International Business Machines Corporation Two-color self-aligned double patterning (sadp) to yield static random access memory (sram) and dense logic

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140097493A1 (en) * 2012-10-09 2014-04-10 Samsung Electronics Co., Ltd. Cells including at least one fin field effect transistor and semiconductor integrated circuits including the same
TW201419451A (en) * 2012-11-14 2014-05-16 Taiwan Semiconductor Mfg SRAM cell array and method for manufacturing the same
US20160098508A1 (en) * 2014-10-01 2016-04-07 Sang-hoon BAEK Method and system for designing semiconductor device
US20170061056A1 (en) * 2015-09-02 2017-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Cell grid architecture for finfet technology
US20190189457A1 (en) * 2017-12-14 2019-06-20 International Business Machines Corporation Two-color self-aligned double patterning (sadp) to yield static random access memory (sram) and dense logic

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