CN113394199B

CN113394199B - Semiconductor arrangement

Info

Publication number: CN113394199B
Application number: CN202110648650.7A
Authority: CN
Inventors: 张耀平; 邓天伟
Original assignee: Individual
Current assignee: Individual
Priority date: 2021-06-10
Filing date: 2021-06-10
Publication date: 2023-02-03
Anticipated expiration: 2041-06-10
Also published as: CN113394199A

Abstract

The invention discloses a semiconductor arrangement, which comprises a radio chip, an interface board and salient points, wherein a radio circuit is arranged in the radio chip and is connected with the interface board, and the salient points are arranged on the interface board. The invention adopts the spherical salient points and the cylindrical salient points in the standard chip interconnection technology to improve the performance of the on-chip antenna and the antenna array. The invention can be widely applied to the field of chip antennas.

Description

Semiconductor arrangement

Technical Field

The invention relates to the field of chip antennas, in particular to a semiconductor arrangement.

Background

The terahertz (THz) frequency range, from 300GHz to 3THz, has been identified as a key spectral range for many applications. However, the high cost and low integration level of III-V devices required for the system limits the widespread use of terahertz devices. The improvement in high frequency performance of CMOS makes CMOS a possible low cost alternative to implementing a system, and the use of this spectral range can be greatly expanded. In terahertz, it becomes more feasible to integrate an antenna with other circuits into a single chip of semiconductor technology than at millimeter wave frequencies, because the size of the antenna is greatly reduced. The existing chip antenna has the problem of low power efficiency.

Disclosure of Invention

It is an object of the invention to provide a semiconductor arrangement that can improve the performance of on-chip antennas and antenna arrays.

The technical scheme adopted by the invention is as follows: a semiconductor arrangement comprises a radio chip, an interface board and bumps, wherein a radio circuit is arranged in the radio chip and connected with the interface board, and the bumps are arranged on the interface board.

Further, the radio chip comprises a passivation layer, a silicon oxide dielectric layer, a grounding layer on the chip and a silicon wafer layer from top to bottom, the interface board is at least partially embedded in the passivation layer, and the interface board and the salient points form a salient point antenna array.

Further, still include on-chip antenna and parasitic plate, be equipped with the bump on-chip antenna and the parasitic plate respectively, on-chip antenna is microstrip patch antenna, short circuit microstrip patch antenna, planar inverted-F antenna, magnetoelectric dipole antenna, microstrip quasi-yagi antenna and microstrip bow tie antenna.

The wireless chip is characterized by further comprising a wafer and a conducting plate, wherein a wireless chip is arranged on the wafer, the wafer is in contact with a silicon wafer layer of the wireless chip, a bump antenna array is arranged on the wireless chip, the conducting plate is respectively arranged on the wireless chip and the silicon wafer, and the wireless chip is electrically coupled with the wafer through the conducting plate.

The chip is provided with a radio chip and a salient point antenna array, the radio chip and the salient point antenna array are positioned on the same surface of the chip, and the chip is contacted with a passivation layer of the radio chip through a welding structure.

Further, a radio chip is arranged on the first surface of the wafer, a salient point antenna array is arranged on the second surface of the wafer, and the wafer is in contact with a passivation layer of the radio chip through a welding structure.

Further, the interface board further comprises under bump metal, and the under bump metal is arranged between the interface board and the bump.

Further, the bumps include ball bumps and stud bumps, wherein the bumps comprise at least one of Au, cu, ni, snAg, snCu, snAu, and PbSn, and the bumps are configured to at least one of enhance directivity and increase gain of the antenna, and wherein the ball bumps have a diameter substantially equal to 25% of a resonant wavelength of the antenna.

Further, the stud bump may include a copper stud and a lead-free solder cap, and the stud bump may have a diameter equal to one of 5% to 25%, 10% to 25%, 20% to 25%, or 24% to 25%, or substantially equal to 25% of a resonant wavelength of the antenna. The stud bump may have a height equal to one of 5% to 25%, 10% to 25%, 20% to 25%, or 24% to 25%, or substantially equal to 25% of the antenna resonant wavelength. Wherein the stud bump comprises copper metal.

Furthermore, a through silicon via is arranged on the radio chip and penetrates through the passivation layer, the silicon oxide dielectric layer, the grounding layer on the chip and the silicon wafer layer, and one end of the through silicon via is connected with the interface board.

An arrangement method applied to the above semiconductor arrangement, comprising the steps of: providing a radio circuit; providing an interface board to which radio circuitry can be connected; providing a bump on the interface board;

further, the step of providing a bump on the interface board specifically includes:

depositing photoresist on the interface board and forming an opening on the photoresist; depositing solder in the opening and removing the photoresist; the solder is reflowed to form substantially spherical bumps.

depositing photoresist on the interface board and forming an opening on the photoresist; copper is deposited into the opening to form a copper pillar within the opening.

The invention has the beneficial effects that: the invention adopts the spherical salient points and the cylindrical salient points in the standard chip interconnection technology to improve the performance of the on-chip antenna and the antenna array.

Drawings

FIG. 1 is a conceptual diagram of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 2 is a conceptual diagram of a semiconductor arrangement according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view of the structural geometry of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 4 is a cross-sectional view of the structural geometry of a semiconductor arrangement based on a rewiring scheme in accordance with an embodiment of the present invention;

FIG. 5 is a three-dimensional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 6 is a three-dimensional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 7 is a three-dimensional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 8 is a three-dimensional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 9 is a three-dimensional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 10 is a three-dimensional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 11 is a cross-sectional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 12 is a top view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 13 is a cross-sectional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

fig. 14 is a graph of simulated antenna performance for an interface board antenna in accordance with an embodiment of the present invention;

fig. 15 is a radiation pattern of an interface board antenna according to an embodiment of the present invention;

fig. 16 is a graph of peak gain and radiation efficiency versus frequency for an interface board antenna in accordance with an embodiment of the present invention;

FIG. 17 is a graph of simulated antenna performance for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 18 is a radiation pattern of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 19 is a graph of peak gain and radiation efficiency as a function of frequency for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 20 is a graph of simulated antenna performance for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 21 is a radiation pattern of a semiconductor arrangement in accordance with an exemplary embodiment of the present invention;

FIG. 22 is a graph of peak gain and radiation efficiency as a function of frequency for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 23 is a graph comparing the peak directivity of an interface board antenna with a semiconductor according to an embodiment of the present invention;

FIG. 24 is a simulated surface current plot on a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 25 is a simulated surface current plot on a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 26 is a schematic diagram of an on-chip antenna according to an embodiment of the present invention;

FIG. 27 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 28 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

fig. 29 is a schematic diagram of an on-chip dipole antenna according to an embodiment of the invention;

FIG. 30 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 31 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

fig. 32 is a schematic diagram of a patch antenna on a chip according to an embodiment of the invention;

FIG. 33 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 34 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 35 is a schematic diagram of a patch-on-chip antenna with a feed line in accordance with an embodiment of the present invention;

FIG. 36 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 37 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 38 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 39 is a graph of simulated antenna performance for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 40 is a radiation pattern of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 41 is a graph of peak gain and radiation efficiency as a function of frequency for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 42 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 43 is a bottom view of an interface board of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 44 is a cross-sectional view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 45 is a graph of simulated antenna performance for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 46 is a graph of the relationship between axial ratio and frequency for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 47 is a graph of peak gain and radiation efficiency as a function of frequency for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 48 is a radiation pattern of a semiconductor arrangement in accordance with an exemplary embodiment of the present invention;

FIG. 49 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 50 is a graph of peak gain versus number of radiating elements for a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 51 is a normalized radiation pattern of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 52 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 53 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

FIG. 54 is a schematic view of a semiconductor arrangement in accordance with an embodiment of the present invention;

fig. 55 is a schematic diagram of a semiconductor arrangement in accordance with an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and the specific embodiments. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

Fig. 1 shows a conceptual diagram of a semiconductor arrangement 100A, comprising a radio circuit 102, an interface board 104 and a bump 106, the interface board 104 being connectable to the radio circuit 102 and being able to connect toConfigured to have at least one of receive input from the antenna and further provide antenna input to the radio circuitry 102, or configured to receive output from the radio circuitry 102 and further provide radio circuitry output to the antenna; the bumps 106 are disposed on the interface board 104. The radio circuit 102 may be provided in one radio chip. The radio chip may include a passivation layer, a silicon oxide dielectric layer, an on-chip ground plane, and a silicon wafer layer. The passivation layer is arranged on the silicon oxide dielectric layer, the silicon oxide dielectric layer is arranged on the grounding layer on the chip, and the grounding layer on the chip is arranged on the silicon wafer layer. The interface board 104 may be placed on the wireless die, at least partially embedded in the passivation layer. The interface board 104 may be an input/output board. The bumps 106 may be formed directly on the interface board 104 and the bumps 106 may be formed using chip interconnect technology. The bump 106 may be made of at least one metal material selected from Au, cu, ni, snAg, snCu, snAu, and PbSn, and the bump 106 may be a ball bump or a stud bump, which may be used to at least one of enhance directivity or increase gain of the antenna. The ball bumps generally have a diameter at least equal to 25% of the antenna resonant wavelength, while the diameter of the ball bumps may be less than the length of the interface board 104. The diameter of the ball bumps may generally be at least in the range of 10% to 25% of the length of the interface plate 104. The stud bumps generally have a diameter at least equal to 25% of the resonant wavelength of the antenna. The height of the stud bump can be set arbitrarily. Therefore, the height of the semiconductor arrangement 100A may not be limited by the height of the stud bump. When the stud bump height is substantially equal to

The gain and efficiency of the semiconductor arrangement 100A may be highest, where λ is the antenna resonant wavelength and n represents an integer. When the stud bump height is substantially equal to

The gain and efficiency of the semiconductor arrangement 100A may be the lowest. The stud bump includes copperA column.

Fig. 2 shows a conceptual diagram of a semiconductor arrangement 100B, which, like the semiconductor arrangement 100A, may include a radio circuit 102, an interface board 104 and a bump 106, and further include an antenna 108 and at least one parasitic board 110, the antenna 108 being one of a microstrip patch antenna, a short-circuited microstrip patch antenna, a planar inverted-F antenna, a magneto-electric dipole antenna, a microstrip monopole antenna, a microstrip quasi-yagi antenna and a microstrip bow-tie antenna. At least one parasitic plate 110 may be disposed adjacent to the interface plate 104. At least one parasitic plate 110 may be at least substantially identical to the interface plate 104. The parasitic plate 110 cannot be coupled and connected to any feed line or feed structure. The parasitic plate 110 may increase the operating bandwidth of the semiconductor arrangement 100B. The antenna 108 may be integrated with the interface board 104. Alternatively, the antenna 108 may be separate from the interface board 104.

Based on various embodiments, the semiconductor arrangement may include bumps fabricated using standard chip interconnect technology to enhance the performance of on-chip antennas and antenna arrays. The bump may be at least one of a ball bump or a stud bump. The bumps may improve the on-chip antenna gain by about 5.4dB. Since the bumps may be provided using conventional chip interconnect technology, the semiconductor arrangement may provide a cheaper and more reliable antenna solution than existing antenna solutions such as lens technology or overlying dielectric layer technology.

Fig. 3 shows a cross-sectional view of a structural geometry of a semiconductor arrangement 300, which semiconductor arrangement 300 may be identical or substantially similar to semiconductor arrangement 100A of fig. 1. The semiconductor arrangement 300 can include a substrate (which can be a wafer 330), the interface board 304, and the bumps 306, the wafer 330 can be a silicon (Si) wafer. The bumps may be spherical, referred to herein as spherical bumps 306. Semiconductor arrangement 300 can further include a passivation layer 332 disposed on wafer 330 and adjacent to interface board 304. Semiconductor arrangement 300A may further include an Under Bump Metallization (UBM) 334 under ball bump 306. The ball bumps 306 may be the same bumps made by conventional chip interconnect techniques used to connect two wafer chips together. The ball bumps 306 can be deposited onto the silicon wafer 330 by electroplating on the interface board 304 of the chip. Each ball bump 306 may be deposited on a respective Under Bump Metallization (UBM) 334. The ball bump 306 may be composed of at least one metal material of Au, cu, ni, snAg, snCu, snAu, and PbSn. The ball bumps 306 may be deposited on an interface board 304 of a package or Printed Circuit Board (PCB), and the ball bumps 306 may be about 20-500 μm in height, that is, about 20-500 μm in diameter. The ball bump pitch, i.e., the distance between the centers of two adjacent ball bumps, may be about 40-1000 μm. The height error may be less than 2 μm for bumps having a height of about 25 μm on an 8 inch wafer.

The semiconductor arrangement shown in fig. 4 (a) and 4 (b) is the same as or substantially similar to semiconductor arrangement 300, except that RDL rerouting is applied to connect Under Bump Metallization (UBM) 334 to interface board 304, under Bump Metallization (UBM) 334 may be a multi-layer metallization such that the positional coordinates of ball bumps 306 and the positional coordinates of interface board 304 need not correspond one-to-one. The multi-layer Under Bump Metallurgy (UBM) 334 may be used as a power combiner to combine signals of different interface boards 304 into the same spherical bump 306 for radiation. The multi-layer Under Bump Metallurgy (UBM) 334 can be used as a power splitter to distribute signals of one interface board 304 to different spherical bumps 306 for radiation.

One antenna device may include at least one of a ball bump antenna or a stud bump antenna. The antenna device may further include at least one of a ball bump antenna array or a stud bump antenna array. A ball bump antenna or a stud bump antenna may be implemented on an input/output board (I/O pad) of a radio signal on one chip. In addition, a ball bump antenna or a stud bump antenna may be implemented on an input/output board of a radio signal on the package.

Fig. 5 shows a semiconductor arrangement 500 comprising an array of ball bump antennas on a radio chip 502. The radio chip 502 may be implemented with a chip die. Each ball bump antenna may include a ball bump 506, with ball bump 506 being located on interface board 504 connected to radio chip 502. Ball bumps 506 may be fabricated using conventional fabrication processes for chip interconnects. The radio chip 502 may include radio circuitry for processing the radio signal, e.g., changing the frequency of the radio signal, modulating the radio signal or encoding the radio signal according to a modulation scheme. The frequency of the radio signal may be in the terahertz frequency range. The radio circuit may comprise a receiver of radio signals or a transmitter of radio signals. The radio circuit may include a radio transceiver. The radio circuit may be connected to interface board 504. The interface board 504 may include an antenna feed structure. The radio chip 502 may include a silicon wafer layer 530, an on-chip ground layer on the silicon wafer layer 530, a silicon oxide dielectric layer 550 on the on-chip ground layer, and a passivation layer 532. Interface board 504 may be at least partially embedded in passivation layer 532 with a top surface of interface board 504 in contact with ball bumps 506. The radio chip 502 may include a conductive plate 552. A conductive plate 552 is also disposed on the passivation layer 532. The radio chip may be placed on a substrate, such as a wafer 554, and the wafer 554 may include more conductive plates 556. The radio chip 502 can electrically couple signals to the die 554 by connecting the conductive plate 552 to the conductive plate 556 by wire bonds 558. The radio chip 502 and the die 554 may constitute a die package. The die package may include other circuitry that may be used to receive information from the radio chip 502 or to transmit information through the radio chip 502.

Fig. 6 shows a semiconductor arrangement 600 similar to the semiconductor arrangement 500 except that the semiconductor arrangement 600 comprises a stud bump antenna array instead of a ball bump antenna array. The stud bump antenna includes stud bumps 606 that are located on interface board 504. Stud bumps 606 may be fabricated using conventional fabrication processes for chip interconnect bonding.

Fig. 7 shows a semiconductor arrangement 700 that is similar to the semiconductor arrangement 500 except that the ball bump antenna array is disposed on a wafer 554 instead of on the radio chip 502. The radio chip 502 may further include a solder structure 770 for connecting the radio chip 502 to the die 554. The radio chip 502 may be flipped over and bonded to the wafer 554 with the top of the radio chip 502 (where the passivation layer 532 is located) facing the wafer 554. The radio chip 502 may be bonded to the wafer 554 by first flipping the radio chip 502 face down and aligning the solder pads on the radio chip 502 to the corresponding solder pads on the wafer 554 and then reflowing the solder structure 770 to the radio chip 502. Each of the ball bump antennas may include a ball bump 506, the ball bump 506 being located on an interface board 504 connected to the radio chip 502. Interface board 504 may be placed on wafer 554 instead of radio chip 502 as in semiconductor arrangement 500. Ball bumps 506 may be fabricated using conventional fabrication processes for chip interconnects. The radio chip 502 may be implemented with a chip die. The radio chip 502 may include a radio circuit for processing radio signals. Interface board 504 may be connected to radio circuitry or radio chip 502 by a plurality of connection lines 772. The solder structure 770 may be at least partially embedded in the passivation layer 532 with a top surface of the solder structure 770 in contact with the connecting wire 772. The radio chip 502 and the die 554 may be one die package. The die package may be connected to other circuitry external.

Fig. 8 shows a semiconductor arrangement 800 similar to that of fig. 7, except that the radio chip 502 is placed on a first side of the wafer 554 and the ball bump antenna is placed on a second side of the wafer 554, where the first and second sides of the wafer 554 are located on opposite sides of the wafer, respectively, i.e.: various ball bump antennas may be placed on opposite sides of the wafer 554 as the radio chip 502. Various ball bump antennas may be connected to the wireless chip 502 by various interconnections through the wafer 554, respectively. The various interconnect lines may include various via structures.

Fig. 9 shows a semiconductor arrangement 900 that is similar to semiconductor arrangement 600 except that instead of a ball-bump antenna, the semiconductor arrangement includes a plurality of stud-bump antennas, including stud-bump 606.

Fig. 10 shows a semiconductor arrangement 1000 that is similar to semiconductor arrangement 800 except that it includes a plurality of stud bump antennas instead of ball bump antennas, the stud bump antennas including stud bumps 606.

Fig. 11 shows a cross-sectional view of a semiconductor arrangement 1100 illustrating the geometry and dimensions of a ball bump antenna. The semiconductor arrangement 1100 comprises, in turn, an off-chip ground layer 1112, a silicon dielectric layer 330, an on-chip ground layer 1110, a silicon oxide dielectric layer 550 and a passivation layer 332, on which passivation layer 332 the interface board 304 is arranged, wherein the interface board 304 can be connected to radio circuitry. The silicon dielectric layer 330 has a thickness of about 300-700 μm, a dielectric constant of 11.9, and a resistivity of 2-20 Ω. The silicon oxide dielectric layer 550 has a thickness of about 8 μm and a dielectric constant of 4, and a ball bump 306 may be placed on the interface board 304. The semiconductor arrangement 1100 may be a ball bump antenna.

Fig. 12 shows a top view 1200 of a semiconductor arrangement 1100 with the radius of the spherical bump 306 noted r _ball 1220, a ball bump 306 is placed on top of the interface board 304, and has a length l _pad 1224 width w _pad 1222，r _ball 1220 is generally less than l _pad 1224 and w _pad 1222。

Fig. 13 shows a cross-sectional view of a semiconductor arrangement 1300 illustrating the geometry and dimensions of a stud bump antenna, which semiconductor arrangement 1300 may be. Semiconductor arrangement 1300 comprises in turn an off-chip ground layer 1112, a silicon wafer layer 330, an on-chip ground layer 1110, a silicon oxide dielectric layer 550 and a passivation layer 332, on which passivation layer 332 an interface board 304 can be provided, wherein interface board 304 can be connected to the radio circuitry. The thickness of silicon wafer layer 330 can be written as h _si 1338 of about 300-700 μm, a dielectric constant of 11.9, and a resistivity of 2-20. Omega. Cm. The thickness of the silicon oxide dielectric layer 550 can be written as h _sio2 1336, about 8 μm, and a dielectric constant of 4. A ball bump 306 may be placed on interface board 304. A gap is formed between two adjacent interface boards 304, and the width of the gap is denoted as w _gap 1332. The height of stud bump 406 is recorded as h _pillar 1334 radius of stud bump 406Is r _pillar 1330. The semiconductor arrangement 1300 may further comprise feed lines 1340, one feed line 1340 requiring to be kept at a distance w from the other feed lines 1340 _gap . These feed lines may be used to provide voltages of different polarities to stud bumps 1330.

Simulation results of the semiconductor arrangement based on various embodiments will be described below. The semiconductor arrangement may be manufactured using standard chip interconnect technology. The semiconductor arrangement may include integrating a terahertz transceiver having a ball bump antenna or a stud bump antenna in a single wafer package. From the simulation results, it can be seen that both the ball bump antenna and the stud bump antenna can achieve a larger antenna radiation gain enhancement.

Fig. 14 shows a simulated antenna performance diagram 1400 of an interface board antenna, comprising: the vertical axis 1442 represents the input impedance of the antenna and the horizontal axis 1444 represents frequency. The antenna size studied is w _pad 1222＝l _pad 1224=252 μm. The antenna is disposed on an 8- μm thick silicon oxide (SiO 2) dielectric layer and a low resistivity 10- Ω cm300- μm thick silicon wafer layer. Diagram 1400 further includes: a first line 1446 representing the imaginary part of the input impedance (marked with a square figure) and a second line 1448 representing the real part of the input impedance (marked with a circle figure). Graph 1400 shows that the second line 1448 peaks around 285GHz and the first line drops to a minimum around 290 GHz. Fig. 14 also shows an inset diagram 1410 having a longitudinal axis 1412 and a lateral axis 1414. The vertical axis 1412 represents | S11|, and the horizontal axis 1414 represents the operating frequency. | S11| represents the magnitude of the signal power reflected from the antenna, also referred to as the reflection coefficient or return loss. As can be seen from inset plot 1410, return loss is the lowest around 290 GHz.

Fig. 15 shows a radiation pattern 1500 of the interface board antenna of fig. 14, comprising: a vertical axis 1502 representing the gain of the antenna, a first line 1504 representing cross-polarization characteristics in the H-plane, a second line 1506 representing cross-polarization characteristics in the E-plane, a third line 1508 representing co-polarization characteristics in the E-plane, and a fourth line 1510 representing co-polarization characteristics in the H-plane. The E surface is an electric field, and the H surface is a magnetic field. The radiation pattern of the interface board antenna is similar to that of the patch antenna because there is an on-chip ground between the silicon substrate (i.e., silicon wafer layer) and the silicon oxide layer as a reflecting surface.

Fig. 16 shows a graph 1600 of peak gain and radiation efficiency versus frequency for an interface board antenna, comprising: a first vertical axis 1602 representing peak gain of the antenna, a second vertical axis 1604 representing radiation efficiency of the antenna, a horizontal axis 1606 representing frequency, a first line 1608 representing radiation gain, the values of which are read from the first vertical axis 1602, a second line 1610 representing radiation efficiency of the antenna, the values of which are read from the second vertical axis 1604. As can be seen from the first line 1608, the gain of the interface board antenna is around 3.2dBi at frequencies around 302GHz, and the second line 1620 shows that the antenna radiation efficiency is about 34% at 302 GHz.

Fig. 17 shows a simulated antenna performance diagram 1700 for a ball bump antenna. The ball bump antenna is similar to the semiconductor arrangement 1100 in fig. 11. A ball bump antenna is formed by adding a ball bump to the interface board antenna of fig. 14. The radius of the spherical bump may be about 105 μm. The graph 1700 includes: a vertical axis 1772 representing the input impedance, a horizontal axis 1774 representing frequency, a first line 1776 (marked with a square figure) representing the imaginary part of the input impedance, a second line 1778 (marked with a circle figure) representing the real part of the input impedance, the second line 1778 peaking around 285GHz and the first line dropping to a minimum around 290GHz, similar to diagram 1400 of the interface board antenna, but without the inclusion of spherical bumps in diagram 1400. Fig. 17 also includes inset 1710 (vertical axis 1712 and horizontal axis 1714), with vertical axis 1712 representing | S11| of the spherical bump and horizontal axis 1714 representing frequency. As can be seen from graph 1710, return loss | S11| is the lowest value around 290GHz, similar to graph 1410 in fig. 14. As can be seen from fig. 17, the resonant frequency of the ball bump antenna is almost the same as the resonant frequency of the interface board antenna.

Fig. 18 shows a radiation pattern 1800 of the ball-bump antenna of fig. 17, comprising: a vertical axis 1802 representing the gain of the ball bump antenna, a first line 1804 representing cross-polarization characteristics in the H-plane, a second line 1806 representing cross-polarization characteristics in the E-plane, a third line 1808 representing co-polarization characteristics in the E-plane, and a fourth line 1810 representing co-polarization characteristics in the H-plane.

FIG. 19 shows a plot 1900 of peak gain and radiation efficiency as a function of frequency for the ball bump antenna of FIG. 17, including: a first vertical axis 1902 representing peak gain of the antenna, a second vertical axis 1904 representing radiation efficiency of the antenna, a horizontal axis 1906 representing frequency, a first line 1908 representing radiation gain, the values read from the first vertical axis 1902, a second line 1920 representing radiation efficiency of the antenna, the values read from the second vertical axis 1904. As can be seen from the first line 1908, the highest gain of the ball bump antenna is around 8dBi when the frequency is around 310 GHz. The second line 1920 shows that the antenna radiation efficiency is about 56% at 310 GHz. At 270GHz, the maximum antenna radiation efficiency is 72%. Although the resonant frequency of the ball bump antenna is almost the same as the interface board antenna in fig. 14, the maximum gain of the ball bump antenna is 4.8dB higher than the interface board antenna due to the additional ball bumps.

Fig. 20 shows a simulated antenna performance plot 2000 for a stud bump antenna similar to semiconductor arrangement 1300. A ball bump antenna is formed by adding stud bumps to the interface board antenna of fig. 14. The stud bumps may have a radius of about 105um and a height of about 210um. The graph 2000 includes: a vertical axis 2002 representing the input impedance, a horizontal axis 2004 representing the frequency, a first line 2006 (marked with a square figure) representing the imaginary part of the input impedance, and a second line 2008 (marked with a circle figure) representing the real part of the input impedance. The second line 2008 peaks around 285GHz and the first line drops to a minimum around 290GHz, similar to the diagram 1400 of the interface board antenna, but without the inclusion of the spherical bumps in the diagram 1400. Fig. 20 also includes inset 2010, with vertical axis 2012 representing spherical bump | S11 and horizontal axis 2014 representing frequency. As can be seen from graph 2010, return loss | S11| is the lowest value around 290GHz, similar to graph 1410 in fig. 14. As can be seen from fig. 20, the resonance frequency of the stud bump antenna is almost the same as the resonance frequency of the interface board antenna.

Fig. 21 shows a radiation pattern 2100 for the stud bump antenna of fig. 20, including: a longitudinal axis 2102 representing the gain (in dB) of the stub bump antenna, a first line 2104 representing cross polarization characteristics in the H-plane, a second line 2106 representing cross polarization characteristics in the E-plane, a third line 2108 representing co polarization characteristics in the E-plane, and a fourth line 2110 representing co polarization characteristics in the H-plane.

FIG. 22 shows a graph 2200 of peak gain and radiation efficiency versus frequency for the stud bump antenna of FIG. 20, including: a first vertical axis 2202 representing peak gain of the antenna, a second vertical axis 2204 representing radiation efficiency of the antenna, a horizontal axis 2206 representing frequency, a first line 2208 representing radiation gain, the values read from the first vertical axis 2202, a second line 2220 representing radiation efficiency of the antenna, the values read from the second vertical axis 2204. As can be seen from the first line 2208, the highest gain of the stud bump antenna is around 8.9dBi at a frequency of around 300GHz, and the second line 2220 shows an antenna radiation efficiency of about 70% at 290GHz and 75% at 260 GHz. Although the resonance frequency of the stud bump antenna is almost the same as the interface board antenna in fig. 14, the maximum gain of the stud bump antenna is 5.8dB higher than the interface board antenna due to the additional stud bumps.

Fig. 23 illustrates a graph 2300 comparing peak directivity for the interface board antenna of fig. 14, the ball bump antenna of fig. 17, and the stud bump antenna of fig. 20. Diagram 2300 includes: a vertical axis 2302 representing the peak directivity of the antenna, a horizontal axis 2304 representing frequency, a first line 2306 representing the peak directivity of the interface board antenna, a second line 2308 representing the peak directivity of the ball bump antenna, and a third line 2310 representing the peak directivity of the stud bump antenna. The graph 2300 shows that the ball bump antenna and the stud bump antenna can achieve about 5dB higher peak directivity at the resonant frequency than the interface board antenna, and as shown in fig. 19 and 22, the ball bump antenna and the stud bump antenna can also achieve higher radiation efficiency than the interface board antenna. The reason why the spherical bumps or the stud bumps increase the antenna gain is to enhance the directivity of the antenna and to improve the radiation efficiency of the antenna.

Fig. 24 shows a simulated surface current diagram 2400 over a ball-bump antenna, including a top view 2402 of the ball-bump antenna and a side view 2404 of the ball-bump antenna, and fig. 25 shows a simulated surface current diagram 2500 over a stud-bump antenna, including a top view 2502 of the stud-bump antenna and a side view 2504 of the stud-bump antenna, in accordance with various embodiments. And drawing a surface current diagram of the bump antenna through electromagnetic simulation, and researching the enhancement mechanism of the bump antenna relative to the directivity of the interface board antenna.

As can be seen from fig. 24 and 25, on the top surface of the bump, the current behaves like a dipole, becoming the second radiator, while the original radiator is formed by the current on the interface board. Thus, the ball bump antenna and the stud bump antenna can be viewed as two dipole arrays with reflectors. Wherein the reflector may be an on-chip ground plane.

According to various embodiments, the semiconductor arrangement comprises an on-chip antenna and bumps, which may be ball bumps or stud bumps. As shown in fig. 14-25, the performance of the on-chip antenna can be greatly improved by adding ball bumps or stud bumps. By adopting a standard chip interconnection technology, spherical salient points or cylindrical salient points can be added on the antenna of the interface board. The radiation gain enhancement mechanism of the spherical bump antenna and the cylindrical bump antenna is that the bumps improve the directivity and the radiation efficiency of the antenna. The improved directivity is due to a better array factor and the improved radiation efficiency is due to reduced loss effects from the silicon wafer.

Fig. 26 shows a semiconductor arrangement 2600 comprising a chip-on-chip patch antenna 2602, the chip-on-chip patch antenna 2602 being placed between and adjacent to two parasitic plates 2604, the chip-on-chip patch antenna 2602 being placed on an 8 μm thick dielectric layer of silicon oxide and a low resistivity 10- Ω cm300- μm thick layer of silicon wafer, the parasitic plates 2604 being placed on the antenna E-plane. The on-chip patch antenna 2602 may be spaced apart from any one of the parasitic plates 2604 by a distance of about 30 μm. The parasitic plate has little effect on the resonant frequency of the on-chip patch antenna. The maximum gain and maximum radiation efficiency of the semiconductor arrangement 2600 is similar to an on-chip patch antenna without a parasitic plate.

Fig. 27 shows a semiconductor arrangement 2700 similar to the semiconductor arrangement 2600, but further including ball bumps 2706 placed on top of each parasitic plate 2604 and patch antenna 2602. The patch antenna 2602 and the parasitic plate 2604 may be placed on an 8 μm thick silicon oxide dielectric layer and a low resistivity 10- Ω cm300- μm thick silicon wafer layer. The parasitic plate 2604 and the ball bump 2706 may be disposed on the antenna E plane. The gap distance between the on-chip patch antenna board 2602 and the parasitic board 2604 is about 30 μm. Semiconductor structure 2700 is also referred to herein as a globose bump antenna. In addition, the resonant frequency of the semiconductor arrangement 2700 is similar to the on-chip patch antenna with parasitic plates in fig. 26 (semiconductor arrangement 2600). However, the ball bump antenna with the parasitic plate has better radiation gain and radiation efficiency than the on-chip patch antenna without the parasitic plate.

Fig. 28 shows a semiconductor arrangement 2800 similar to semiconductor arrangement 2700, except that the parasitic plate 2604 is disposed on the antenna H-plane. The maximum gain of the ball-bump antenna is similar to the maximum radiation gain and maximum radiation efficiency of the semiconductor arrangement 2700. That is, when the parasitic plate and the ball bump are placed on the H plane as shown in fig. 28, the influence on the maximum radiation gain and the maximum radiation efficiency is small.

Fig. 29 shows a semiconductor arrangement 2900 comprising a dipole antenna 3102 and two interface boards 3104. The semiconductor arrangement 2900 may be a type of on-chip dipole antenna. Common on-chip antenna forms include microstrip dipole antennas, patch antennas, quasi-yagi antennas, and bow-tie antennas. The dipole antenna 3102 may be placed on an 8 μm thick silicon oxide dielectric layer and a low resistivity 10- Ω cm300- μm thick silicon wafer layer. The dipole antenna 3102 may be designed as a half-wavelength dipole. One arm of the dipole may have a length equal to a quarter wavelength of the designed resonant frequency.

The semiconductor arrangement 2900 is used as a reference antenna to compare simulation results of other semiconductor arrangements discussed below.

Fig. 30 shows a semiconductor arrangement 3000 comprising a dipole antenna 3102 and two interface boards 3104. On the basis of the semiconductor arrangement 2900, the semiconductor arrangement 3000 further includes a ball bump 2706 on each interface board 3104. The semiconductor arrangement 3000 may be a ball bump antenna on a chip. The dipole antenna 3102 may be placed on an 8 μm thick silicon oxide dielectric layer and a low resistivity 10- Ω cm300- μm thick silicon wafer layer. The diameter of each ball bump 2706 can be designed to be slightly less than a quarter wavelength. The resonant frequency of semiconductor arrangement 3000 is similar to the resonant frequency of semiconductor arrangement 2900, but the maximum radiation gain of semiconductor arrangement 3000 is significantly higher than that of semiconductor arrangement 2900 due to the attached spherical bumps 2706.

Fig. 31 shows a semiconductor arrangement 3100. Semiconductor arrangement 3100 is similar to semiconductor arrangement 3000 except that ball bumps 2706 are replaced with stud bumps 3306. The semiconductor arrangement 3100 may be a kind of on-chip stud bump antenna. The diameter and height of the stud bump 3306 may be designed to be slightly less than a quarter wavelength. The resonance frequencies of the stud bump antennas are almost the same compared to the semiconductor arrangement 2900. However, the maximum gain of the stud bump antenna is significantly improved due to the additional stud bump 3306. By comparing the current distribution over the semiconductor arrangement, it can be seen that an increase in radiation gain is achieved by adding a ball bump or stud bump to the on-chip antenna. The increase in the radiation gain of the antenna is due to the better radiation directivity (array factor) and better radiation efficiency. The improvement in radiation efficiency is mainly due to radiation caused by the current flowing on the upper surfaces of the ball bumps and the stud bumps.

Fig. 32 shows a semiconductor arrangement 3200. The semiconductor arrangement 3200 may comprise one patch antenna 3402. The patch antenna 3402 may include an interface board with the patch antenna 3402 placed on an 8 μm thick silicon oxide dielectric layer and a low resistivity 10- Ω cm300- μm thick silicon wafer layer. The patch antenna 3402 may be fed through a metal post/hole formed from a first metal layer in a silicon oxide dielectric layer to a top metal layer.

The semiconductor arrangement 3200 may serve as a reference for comparison with other semiconductor arrangements. The on-chip patch antenna 3402 may be designed as a quarter-wavelength patch, the length of the patch antenna 3402 being equal to 1/4 wavelength, and the width being greater than or equal to 1/4 wavelength.

Fig. 33 shows a semiconductor arrangement 3300 in accordance with various embodiments. The semiconductor arrangement 3300 is similar to the semiconductor arrangement 3200, but it further comprises ball bumps 2706 on top of the patch antenna 3402, and the patch antenna 3402 may comprise an interface board to connect with the ball bumps 2706.

Fig. 34 shows a semiconductor arrangement 3400 similar to the semiconductor arrangement 3300 except that the ball bumps 2706 are replaced with stud bumps 3306.

Fig. 35 shows a semiconductor arrangement 3500 comprising: a patch antenna 3402 disposed on the 8 μm thick silicon oxide dielectric layer and the low resistivity 10- Ω cm300- μm thick silicon dielectric layer, a feed line 3702 connected to the patch antenna 3402, the feed line 3702 may be a quarter wavelength feed line. The patch antenna 3402 is fed through a metal post/hole formed from a first metal layer to a top metal layer at the end of the feed line 3702.

Fig. 36 shows a semiconductor arrangement 3600 similar to the semiconductor arrangement 3500, but further including ball bumps 2706 on the patch antenna 3402.

Fig. 37 shows a semiconductor arrangement 3700 that is similar to the semiconductor arrangement 3600, except that the ball bumps 2706 are replaced with stud bumps 3306.

Fig. 38 shows a semiconductor arrangement 3800 including an on-chip stud bump monopole antenna 4006 disposed on an 8 μm thick silicon oxide dielectric layer and a low resistivity 10- Ω cm300- μm thick silicon wafer layer. The on-chip stud bump monopole antenna 4006 can be considered a monopole antenna. That is, the on-chip stud bump monopole antenna 4006 or the array of on-chip stud bump monopole antennas 4006 may be configured to function as a monopole antenna and may have a radiation pattern similar to a monopole antenna. The on-chip stud bump monopole antenna 4006 may radiate laterally, as opposed to the forward radiation of an on-chip antenna or an on-chip antenna array. The stub bump monopole antenna 4006 may be designed to be a quarter wavelength in length, with a diameter much smaller than the wavelength of the resonant frequency, the stub bump monopole antenna 4006 may be implemented on the interface board 4004, and the interface board 4004 may include a patch antenna.

Fig. 39 shows a simulated antenna performance diagram 3900 of a semiconductor arrangement 3800 comprising: a vertical axis 4102 representing the input impedance, a horizontal axis 4104 representing frequency, a first line 1446 representing the imaginary part of the input impedance, and a second line 4108 representing the real part of the input impedance. Also shown is an inset plot 4110, with the vertical axis 4112 representing | S11|, and the horizontal axis 4114 representing frequency.

Fig. 40 shows a radiation pattern 4000 of a semiconductor arrangement 3800 comprising: a vertical axis 4202 representing the radiation gain of the antenna, a first line 4204 representing cross-polarization characteristics in the H-plane, a second line 4206 representing cross-polarization characteristics in the E-plane, a third line 4208 representing co-polarization characteristics in the E-plane, and a fourth line 4210 representing co-polarization characteristics in the H-plane.

Fig. 41 shows a plot 4100 of peak gain and radiation efficiency versus frequency for a semiconductor arrangement 3800 comprising: a first vertical axis 4302 representing peak gain of the antenna, a second vertical axis 4304 representing radiation efficiency of the antenna, a horizontal axis 4306 representing frequency, a first line 4380 representing radiation gain, values read from the first vertical axis 4302, and a second line 4310 representing radiation efficiency of the antenna, values read from the second vertical axis 4304. From the first line 4380, it can be seen that the antenna has a peak gain of 0.7dBi at 0.29THz and a radiation efficiency of 65% at 0.29 THz.

Fig. 42 shows a semiconductor arrangement 4200, the semiconductor arrangement 4200 including stud bumps 3306 on an interface board 4004 placed over an 8 μm thick silicon oxide dielectric layer and a low resistivity 10- Ω cm300- μm thick silicon dielectric layer. Two opposite phase feed points under the interface board 4004 can differentially excite the stud bumps 3306, and the formed circularly polarized bandwidth can cover 0.22-0.39 THz.

Fig. 43 shows a bottom view 4300 of an interface board 4004 of a semiconductor arrangement 4200. A first feed point 4502A and a second feed point 4502B may be disposed below the interface board 4004, wherein the feed points may be configured to feed radio signals to the stud bumps 3306 through respective feed posts/holes.

Fig. 44 shows a cross-sectional conceptual view 4400 of a semiconductor arrangement 4200. The feed point may be disposed below the interface board 4004 and connected to the stud bump 3306, the first feed point 4502A may provide a positive voltage to the stud bump 3306, and the second feed point 4502B may provide a negative voltage to the stud bump 3306, i.e., the first feed point 4502A and the second feed point 4502B may be a pair of anti-phase feed structures that may be configured to generate circularly polarized signals by providing anti-phase signal inputs to the stud bump 3306.

Fig. 45 shows a simulated antenna performance diagram 4500 of a semiconductor arrangement 4200, including: a vertical axis 4702 representing the input impedance, a horizontal axis 4704 representing frequency, a first line 4706 representing the imaginary component of input impedance Z11, a second line 4708 representing the real component of input impedance Z11, a third line 4710 representing the imaginary component of cross-coupled impedance Z21, and a fourth line 4712 representing the real component of cross-coupled impedance Z21.

Fig. 46 shows a graph 4600 of the relationship between axial ratio and frequency of the semiconductor arrangement 4200, including: an axial ratio vertical axis 4802 and a horizontal axis 4804 representing frequency. The axial ratio is an indicator of the antenna polarization type. When the axial ratio is less than 3dB, the antenna polarization is circular polarization. Circularly polarized antennas can receive electromagnetic waves of any type of polarization, whereas linearly polarized antennas can only receive electromagnetic waves of the same linear polarization.

Fig. 47 shows a plot 4700 of peak gain and radiation efficiency of a semiconductor arrangement 4200 as a function of frequency, including: a first vertical axis 4902 representing peak gain, a second vertical axis 4904 representing radiation efficiency, a horizontal axis 4906 representing frequency, a first line 4908 representing radiation gain, the values read from the first vertical axis 4902, a second line 4910 representing antenna radiation efficiency, the values read from the second vertical axis 4904. As can be seen from the first line 4908, the peak gain of the antenna at 0.315THz is 4.6dBi, and the radiation efficiency at 0.315THz is 51%.

Fig. 48 shows a radiation pattern 4800 of a semiconductor arrangement 4200, comprising: a vertical axis 5002 representing antenna gain, a first line 5004 representing cross-polarization characteristics in the H-plane, a second line 5006 representing cross-polarization characteristics in the E-plane, a third line 5008 representing co-polarization characteristics in the E-plane, and a fourth line 5010 representing co-polarization characteristics in the H-plane.

Fig. 49 shows a semiconductor arrangement 4900 comprising a linear array of on-chip ball bumps 2706 placed on an 8 μm thick layer of silicon oxide dielectric and a low resistivity 10- Ω cm300- μm thick layer of silicon wafer, wherein the ball bumps 2706 are provided on an interface board 4004, each ball bump 2706 may be substantially identical, the array may comprise at least one row of ball bumps 2706, each row may comprise at least one ball bump 2706, and the interface board 4004 may be connected to a feed line. Each spherical bump 2706, together with the respective interface board 4004 and feed lines, can be considered a radiating element. At 0.32THz, the distance between each radiating element may be a quarter wavelength. The radiating elements may be arranged in circular arrays, square arrays, and arrays of any other shape.

Fig. 50 shows a graph 5000 of the peak gain versus the number of radiating elements for a semiconductor arrangement 4900, comprising: the vertical axis 5202 represents peak gain and the horizontal axis 5204 represents the number of radiating elements. The graph 5000 shows that the peak gain increases with the number of radiating elements.

Fig. 51 shows a normalized radiation pattern 5100 of a semiconductor arrangement 4900, wherein the semiconductor arrangement 4900 comprises 12 radiating elements. The radiation pattern 5100 includes: vertical axis 5302, which represents antenna gain, horizontal axis 5304, which represents azimuth, first line 5306, which represents cross-polarization characteristics in the H-plane, second line 5308, which represents cross-polarization characteristics in the E-plane, third line 5310, which represents co-polarization characteristics in the E-plane, and fourth line 5312, which represents co-polarization characteristics in the H-plane.

Fig. 52 shows a semiconductor arrangement 5200 comprising a ball bump 5206, an interface board 5204, a passivation layer 5232, a silicon oxide dielectric layer 5250, a silicon seed layer 5230, an off-chip substrate 5240 and a through-silicon-via (TSV) layer 5210, the interface board 5204 at least partially embedding the passivation layer 5232, the ball bump 5206 connecting to the interface board 5204, a portion of the through-silicon-via (TSV) layer 5210 extending through the passivation layer 5232, the silicon oxide dielectric layer 5250 and the silicon seed layer 5230, the interface board 5204 connecting to the off-chip substrate 5240 through the through-silicon-via (TSV) layer 5210, the through-silicon-via (TSV) layer 5210 may be used to connect to a ground signal layer of the off-chip substrate 5240 such that the on-chip antenna obtains a ground structure. The structure can be used as a ground inductor for loading, a Through Silicon Via (TSV) 5210 can be used for connecting a signal line of an external substrate 5240, and an on-chip spherical bump 5206 and the TSV 5210 can also form a cylindrical antenna, a monopole antenna, or the like for transmitting or receiving radio frequency signals. When two bumps 5206 are used with two through-silicon vias (TSVs), on-chip magnetic dipole antennas, magneto-electric dipole antennas, and the like, may be formed. When the two bumps 5206 are used together with two through-silicon vias (TSVs), an interconnection line connecting the two through-silicon vias (TSVs) is formed on the off-chip substrate 5240, and a radiating antenna structure such as a loop antenna structure on a chip can be formed.

Fig. 53 shows a semiconductor arrangement 5300 comprising a plurality of layers of chips, the semiconductor arrangement of each layer of chips being similar to the semiconductor arrangement 5200, in this embodiment, the ball bumps 5306 are used to vertically connect different chips, which can be used as signal connections, or power supply, or ground connections, the number of chips stacked in a 3D package can exceed 100, specifically the ball bumps 5306 of the first layer are connected to the interface board 5304 of the first layer, the interface board 5304 of the first layer is connected to the interface board 5304 of the bottom of the first layer through the through-silicon vias 5310 of the first layer, the interface board 5304 of the bottom of the first layer is connected to the ball bumps 5306 of the second layer, and so on to the bottom. The salient points are placed on the topmost chip and form an on-chip radiation structure together with the interface board and the through silicon vias, and the top connection salient points of the other chips, the interface board and the through silicon vias can also form an on-chip radiation structure. When n layers of chips are packaged together, when the through-silicon vias are (i =0,1, 2.) (1/4 + i) wavelength to (3/4 + i) wavelength of the working frequency of the radiation structure, the bumps, the interface board and the through-silicon vias of the n layers of packaged chips can be vertically connected to form an n-unit vertical antenna array for providing high-gain antenna radiation in the 3D package. The m 3D package n element vertical antenna arrays may form a 3D package m x n element vertical antenna array.

Fig. 54 shows a semiconductor arrangement 5400 comprising a ball bump 5406, an interface board 5404, a passivation layer 5432, a silicon oxide dielectric layer 5450, a silicon wafer layer 5430, an off-chip substrate 5440, a multi-layer substrate 5470, and an electro-magnetic lens 5460, each layer or several layers of the multi-layer substrate 5470 being provided with an electro-magnetic lens 5460, respectively, the interface board 5404 being at least partially embedded in the passivation layer 5432, the ball bump 5406 being connected to the interface board 5404, and an electro-magnetic lens 5460 structure being placed in the interconnecting multi-layer substrate 5470 above and around the ball bump 5406. The electromagnetic lens 5460 may be an electromagnetic metamaterial, may be an electromagnetic super surface, may be an electromagnetic resonant structure, or the like. The electromagnetic wave radiated from the semiconductor placement is condensed by the electromagnetic lens 5460, thereby enhancing the radiation directivity and radiation gain of the semiconductor placement. The semiconductor placement is compatible with the electromagnetic lens, and the radiation directionality and the radiation gain of the semiconductor placement can be further enhanced through the electromagnetic lens. In the case of package interconnection, it is also possible to obtain high-gain terahertz electromagnetic wave radiation using this semiconductor placement, the radiation electromagnetic wave being substantially radiated into the air through the interconnection multilayer.

Fig. 55 shows a semiconductor arrangement 5500 comprising a ball bump 5506, an interface board 5504, a passivation layer 5532, a silicon oxide dielectric layer 5550, a silicon wafer layer 5530, an off-chip substrate 5540 and a hemispherical or semi-ellipsoidal dielectric lens 5560, the interface board 5504 is at least partially embedded in the passivation layer 5532, the ball bump 5506 is connected to the interface board 5504, the semiconductor arrangement is compatible with the hemispherical dielectric lens, the hemispherical dielectric lens 5560 is placed above a chip to cover the ball bump 5506 and collect and focus electromagnetic waves radiated from the ball bump 5506, thereby further enhancing the radiation directivity and radiation gain of the semiconductor arrangement.

In the above embodiments, the ball bumps may be replaced with the stud bumps under the same condition, and the functions and actions thereof may be similar, referring to the above embodiments:

the semiconductor arrangement may comprise an on-chip dipole antenna and at least one ball bump or stud bump. The new antenna technology which is manufactured by adopting the spherical salient points and the cylindrical salient points in the standard chip interconnection technology can greatly improve the performance of the on-chip antenna. In the above simulation, the peak gain of a conventional on-chip dipole antenna can be increased from 5.7dBi to 11.1dBi by simply adding two bumps. The mechanism for the 5.4dB gain increase is due to the improved antenna directivity (better array factor) and radiation efficiency (less dielectric loss of silicon).

The semiconductor arrangement may comprise one chip-on-chip patch antenna fed through the metal stud/hole and at least one ball bump or stud bump. Simulation results show that the peak gain of the traditional chip-on-chip patch antenna can be improved from 2.3dBi to 5.13dBi by adding the spherical salient points on the patch antenna. Similarly, the peak gain of the patch antenna on chip can be increased to 5.3dBi by adding one stud bump.

The semiconductor arrangement may comprise a microstrip fed chip-on-chip patch antenna and at least one spherical or stud bump. Simulation results show that the peak gain of the microstrip line fed chip-on-chip patch antenna can be increased from 1.0dBi to 2.8dBi. Similarly, the peak gain of a microstrip fed chip-on-chip patch antenna can be increased to 3.3dBi by adding a stud bump. The mechanism for the gain improvement of 2-3 dB is due to the improvement of antenna directivity (better array factor) and radiation efficiency (less silicon dielectric layer loss).

The semiconductor arrangement may be configured to function as a monopole antenna. Current distribution simulations also show that the copper cylinder antenna or array can act as a monopole antenna or array. The copper pillar antenna or array may radiate in the lateral direction.

The semiconductor arrangement may be a circularly polarized on-chip antenna or a circularly polarized on-chip antenna array.

While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor arrangement is characterized by comprising spherical bumps, an interface board, a passivation layer, a silicon oxide medium layer, a silicon crystal sheet layer, an off-chip substrate, a plurality of layers of substrates and electromagnetic lenses, wherein each layer or a plurality of layers of substrates of the plurality of layers of substrates are respectively provided with the electromagnetic lenses, the interface board is at least partially embedded into the passivation layer, the spherical bumps are connected with the interface board, and the electromagnetic lens structures are arranged above and around the spherical bumps in the interconnected plurality of layers of substrates.

2. A semiconductor arrangement is characterized by comprising spherical convex points, an interface board, a passivation layer, a silicon oxide dielectric layer, a silicon wafer layer, an off-chip substrate and a hemispherical or semi-ellipsoidal dielectric lens, wherein the passivation layer is at least partially embedded in the interface board, the spherical convex points are connected with the interface board, a semiconductor is compatible with the hemispherical dielectric lens, and the hemispherical dielectric lens is placed above a chip and covers the spherical convex points.

3. A semiconductor arrangement according to any of claims 1-2, further comprising under bump metallization, the under bump metallization being arranged between the interface board and the bump.