CN113381761A - IQ imbalance calibration module and method for phase quantization ADC - Google Patents

Abstract

The invention discloses a calibration module and a calibration method for IQ imbalance of a phase quantization ADC (analog to digital converter), wherein the calibration module is characterized in that: the device comprises an offset error calibration module, a gain error calibration module, a phase error calibration module and a time sequence control module; the mismatch error calibration module obtains a calibration coefficient by utilizing the integral of IQ in a period to compensate; the gain error calibration module is used for obtaining a calibration coefficient by utilizing the integration of the IQ after misadjustment calibration in a half period for compensation; the phase error calibration module utilizes IQ half-period signals to make difference to obtain an included angle so as to compensate; the time sequence control module consists of a single period module and a half period module, and respectively generates a single period and a half period. The invention can calibrate the comprehensive condition of maladjustment error, gain error and phase error, thereby converting an undesired IQ signal into an ideal IQ orthogonal signal and inputting the ideal IQ orthogonal signal into the phase quantization ADC for analog-to-digital conversion.

Description

IQ imbalance calibration module and method for phase quantization ADC

Technical Field

The invention relates to the field of analog-digital conversion, in particular to a calibration module for IQ imbalance of an input signal of a phase quantization analog-digital converter and a calibration algorithm thereof.

Background

Modern electronic systems such as communication systems, radar, image/video processing, etc. require high speed, high precision analog to digital converters. The conventional single-channel analog-to-digital converter is physically limited to realize high speed while ensuring high precision, and particularly, the design of the high-precision and high-speed analog-to-digital converter adopting the conventional structure becomes more difficult as the deep submicron CMOS process is developed to lower power supply voltage and smaller feature size.

As integrated circuit processes advance, the accuracy of conventional voltage domain analog-to-digital converters is limited by the ever-decreasing supply voltage and severe device misalignment. However, the increase in device speed has made the advantage of resolution in the time domain, and thus a/D conversion in the phase domain has become a new approach to high performance ADCs.

PHADC in the prior art all adopt arctan^Q/_IThe ratio of (a) to (b) is quantized, which results in high requirement on the orthogonalization precision of the input Q and I, and the imbalance between IQ will bring a certain error to the subsequent quantization process. Due to the non-ideality of the circuit, certain errors are inevitably generated in the quadrature process, and the expressions of these errors on the IQ function are also mainly three types: mismatch error, gain error, and phase error.

Disclosure of Invention

In order to overcome the defects in the prior art, the invention provides an IQ imbalance calibration module and method for a phase quantization ADC (analog to digital converter), so that the IQ imbalance calibration module and method can be suitable for the calibration of IQ errors in any three forms, and the IQ imbalance calibration can be effectively and comprehensively realized, so that an undesired IQ signal is converted into an ideal IQ quadrature signal to be input into a PHADC (phase locked loop converter) for analog-to-digital conversion.

The invention adopts the following technical scheme for solving the technical problems:

the invention relates to an IQ unbalanced calibration module for a phase quantization ADC (analog to digital converter), which is characterized in that the calibration module is arranged between an orthogonal system and the phase quantization ADC and is used for calibrating IQ orthogonal signals output by the orthogonal system and transmitting the IQ orthogonal signals to the phase quantization ADC;

the calibration module consists of an offset error calibration module, a gain error calibration module, a phase error calibration module and a time sequence control module;

the time sequence control module is composed of a single period generation module and a half period generation module, wherein the single period generation module is used for receiving the initial signal Q₀And an initial signal I₀Performs periodic processing to output signal Q₀Single periodic signal T _ Q1, original signal I₀At a cycle number T _ I1;

the offset error calibration module receives an initial signal Q input from the outside₀And an initial signal I₀And single periodic signals T _ Q1 and T _ I1 output by the timing control module, and the initial signal Q is synchronized in one period₀And an initial signal I₀Performing integration processing to obtain offset compensation factors a and b, compensating by using the offset compensation factors a and b, and outputting the Q after first calibration₁Signal and I after first calibration₁A signal;

the half-cycle generation module is used for receiving the Q after the first calibration₁Signal and I after first calibration₁The signal is processed by half-cycle signal generation, and the output signal is Q after first calibration₀Signal T _ Q2 of half cycle of signal and I after first calibration₀Signal T _ I2, which is a half cycle of the signal;

the gain error calibration module receives the Q after the first calibration₁Signal and I after first calibration₁After first calibration of the signal and timing control module outputQ₀Signal T _ Q2 of half period of signal and I after first calibration₀Signal T _ I2, and calibrating the first Q within a half cycle₀Signal and I after first calibration₀Performing integral processing on the signal to obtain a gain compensation factor K, and then utilizing the gain compensation factor K to perform I after the first calibration₁Compensating the signal and outputting the finally calibrated I₂A signal;

the phase error calibration module receives the Q after the first calibration₁Signal and final calibrated I₂First calibrated Q output by signal and time sequence control module₁Half period of signal T _ Q2, I after first calibration₁Half period T _ I2 and period T of the signal, and for Q after the first calibration₁Half period of signal T _ Q2 and I after first calibration₁Carrying out difference processing on the half period T _ I2 of the signal to obtain an included angle theta, and then utilizing a compensation formula of the included angle theta to carry out Q calibration after the first time₁Compensating the signal and outputting the finally calibrated Q₂A signal.

The IQ imbalance calibration module for the phase quantization ADC is also characterized in that the single period generation module consists of 2 zero-crossing comparators, 2 rising edge triggers, 4 falling edge triggers, 2 summers, 4 subtracters and 1 integrator;

the first zero-crossing comparator receives an initial signal I₀And outputs a control signal C _ I₀；

The first falling edge trigger receives a level signal with an initial value of '1' and the control signal C _ I₀And outputs a signal D1_ I₀；

The first rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ I₀And outputs a signal D2_ I₀；

The fifth subtractor receives the signal D1_ I₀And signal D2_ I₀And outputs a signal S _ I₀；

The first adder receives the signal S _ I₀And a control signal C _ I₀And outputs a signal A _ I₀；

The second falling edge trigger receives a level signal with an initial value of '1' and a control signal A _ I₀And outputs a signal D3_ I₀；

The sixth subtractor receives the subtracted signal D1_ I₀And a subtraction signal D3_ I₀And outputs a signal T _ I1;

the sixth integrator receives the signal T _ I1 and outputs the self-integration result as a period number T;

the second zero-crossing comparator receives an initial signal Q₀And outputs a control signal C _ Q₀；

The third falling edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₀And outputs a signal D1_ Q₀；

The second rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₀And outputs a signal D2_ Q₀；

The seventh subtractor receives the signal D1_ Q₀And signal D2_ Q₀And outputs a signal S _ Q₀；

The second adder receives the signal S _ Q₀And a control signal C _ Q₀And outputs a signal A _ Q₀；

The fourth falling edge trigger receives a level signal with an initial value of '1' and a control signal A _ Q₀And outputs a signal D3_ Q₀；

The eighth subtractor receives the subtracted signal D1_ Q₀And a subtraction signal D3_ Q₀And outputs a signal T _ Q1.

The offset error calibration module consists of 2 integrators, 2 dividers and 2 subtractors;

the first integrator receives an initial signal Q₀And as the integrated number and the signal T _ Q1 and as the integration interval, thereby outputting the offset error factor Ta with the multiple of the period;

the first divider receives the offset error factor Ta with the multiple of the period number and serves as a dividend and the period number T and serves as a divisor, and therefore the offset error factor a is output;

the first subtracter receives an initial signal Q₀And as the subtracted and offset error factor a and as the subtracted number, to output the first calibrated Q₁A signal;

the second integrator receives the initial signal I₀And as the integrated number and the signal T _ I1 and as the integration interval, thereby outputting the offset error factor Tb with multiple periods;

the second divider receives the offset error factor Tb with the multiple of the period number and serves as a dividend and the period number T and serves as a divisor, and therefore the offset error factor b is output;

the second subtracter receives the initial signal I₀And as the subtracted and offset error factor b and as the subtracted number, to output the first calibrated I₁A signal.

The half-period module consists of 2 zero-crossing comparators, 2 rising edge triggers, 2 falling edge triggers and 2 subtractors;

the third zero-crossing comparator receives the signal Q after the first calibration₁And outputs a control signal C _ Q₁；

The fifth falling edge trigger receives a level signal with an initial value of '1' and the control signal C _ Q₁And outputs a signal D1_ Q₁；

The third rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₁And outputs a signal D2_ Q₁；

The ninth subtractor receives the signal D1_ Q₁And signal D2_ Q₁And outputs a signal T _ Q2;

the fourth zero-crossing comparator receives the signal I after the first calibration₁And outputs a control signal C _ I₁；

The sixth falling edge trigger receives a level signal with an initial value of '1' and the control signal C _ I₁And outputs a signal D1_ I₁；

The fourth rising edge trigger receives a level signal with an initial value of '1' and the control signal C _ I₁And outputs a signal D2_ I₁；

The tenth subtractor receives the signal D1_ I₁And signal D2_ I₁And outputs a signal T _ I2.

The gain error calibration module consists of 1 multiplier, 2 integrators and 1 divider;

the third integrator receives the signal Q after the first calibration₁And as the integrated number and the signal T _ Q2 and as the integration interval, thereby outputting a result a;

the fourth integrator receives the signal I after the first calibration₁And as the integrated number and the signal T _ I2 and as the integration interval, thereby outputting a result B;

a third divider receives the result A as a dividend and the result B as a divisor, thereby outputting a gain compensation factor K;

the first multiplier receives the gain compensation factor K and the signal I after the first calibration₁And outputs the finally calibrated I₂A signal.

The phase error calibration module consists of 2 subtractors, 1 absolute value module, 1 integrator, 1 trigonometric function module and 2 multipliers;

the third subtractor receives the signal T _ Q2 as a decremented number and the signal T _ I2 as a decremented number, thereby outputting a signal EN;

the absolute value module receives a signal EN and outputs a signal | EN;

the fifth integrator receives the signal | EN | and outputs the self integration result as a phase angle clamping difference theta;

the trigonometric function module receives the phase included angle difference theta and outputs a signal csc theta and a signal cot theta;

the second multiplier receives the signal csc theta and receives the signal Q after the first calibration₁And outputs a signal csc theta x Q₁；

The third multiplier receives the signal cot θ and the finally calibrated I₂Signal and output signal cot theta x I₂；

The fourth subtractor receives the signal csc θ × Q₁And signal cot θ × I₂And outputs the final calibrationAfter Q₂A signal.

The invention relates to a calibration method for IQ imbalance of a phase quantization ADC (analog to digital converter), which is characterized by comprising the following steps of:

step 1, in a single period, utilizing a rising edge trigger and a falling edge trigger to carry out pair on initial signals Q₀And I₀Processing to obtain an initial signal Q₀And the initial signal I and the single periodic signal T _ Q1₀The single periodic signal T _ I1; processing the single periodic signal T _ I1 by using an integrator to obtain a period number T;

step 2, respectively aiming at the initial signals I in a single period₀And Q₀Performing integration processing to obtain offset compensation factors a and b;

step 3, initial signal I₀Subtracting the offset compensation factor a to obtain I after the first calibration₁A signal; will be the initial signal Q₀Subtracting the offset compensation factor b to obtain the Q after the first calibration₁A signal;

step 4, in a half period, respectively using a rising edge trigger and a falling edge trigger to respectively carry out I after the first calibration₁Sum of signals Q₁Processing the signal to obtain I after the first calibration₁Signal T _ I2 of half cycle of signal and Q after first calibration₁A signal T _ Q2 for half the period of the signal;

step 5, respectively carrying out first calibration on the I in a half period₁Signal and Q₁Performing integral processing on the signal to obtain results A and B, and dividing the results A and B to obtain a gain compensation factor K;

step 6, carrying out calibration on the I after the first calibration₁Multiplying the signal by a gain compensation factor K to obtain the finally calibrated I₂A signal;

and 7, subtracting the half-period signal T _ Q2 from the half-period signal T _ I2 to obtain a signal EN, and performing absolute value and integration processing on the signal EN to obtain an initial signal Q₀And an initial signal I₀Phase angle difference θ of (a); obtaining the final calibrated Q by using the formula (1)₂Signals are input into a phase quantization ADC:

Q₂＝cscθ×Q₁-cotθ×I₂ (1)。

compared with the prior art, the invention has the beneficial effects that:

1. the IQ imbalance calibration module and the IQ imbalance calibration method for the Phase-to-domain ADC (Phase-to-digital ADC) are adopted, gain errors, imbalance errors and Phase errors are considered at the same time, and the problem of I and Q imbalance in the prior art is solved, so that the influence of the I and Q errors in the PHADC is reduced, and the precision of the PHADC is improved.

2. The invention considers gain error, maladjustment error and phase error at the same time, and designs the calibration algorithm, which can eliminate the situation that three kinds of errors exist at the same time, is suitable for IQ signal calibration of any frequency, and has strong universality.

3. The calibration is finished before the PHADC runs, so that extra errors cannot be added to the PHADC by the calibration module, and the accuracy of the PHADC is improved.

4. In the calibration algorithm, the implementation process only needs simple mathematical operation, the calculation complexity is low, and the calibration algorithm is easy to implement.

Drawings

FIG. 1 is a prior art schematic frame diagram;

FIG. 2 is an overall schematic framework diagram of the calibration algorithm of the present invention;

FIG. 3 is a schematic block diagram of the misalignment error calibration block of the calibration algorithm of the present invention;

FIG. 4 is a schematic block diagram of the gain error calibration module of the calibration algorithm of the present invention;

FIG. 5 is a schematic block diagram of a phase error calibration module in the calibration algorithm of the present invention;

FIG. 6 is a schematic block diagram of the timing control module of the calibration algorithm of the present invention;

FIG. 7 is a schematic block diagram of a single cycle generation module in the calibration algorithm of the present invention;

FIG. 8 is a schematic frame diagram of a half-cycle module in the calibration algorithm of the present invention;

FIG. 9 is a graph of an uncalibrated output spectrum of a system with an input signal normalized to a frequency of 0.103 according to an embodiment with an IQ mismatch error of 0.1, a gain error of 10%, and a phase error of 0.1;

FIG. 10 is a calibrated output spectrum of a system with an input signal normalized to 0.103 for an IQ mismatch error of 0.1, a gain error of 10%, and a phase error of 0.1;

FIG. 11 is a graph of an uncalibrated output spectrum of a system with an input signal normalized to a frequency of 0.403 according to an embodiment with an IQ mismatch error of 0.1, a gain error of 10%, and a phase error of 0.1;

FIG. 12 is a graph of the calibrated output spectrum of a system with an input signal normalized to a frequency of 0.403 according to an embodiment with an IQ mismatch error of 0.1, a gain error of 10%, and a phase error of 0.1.

Detailed Description

In this embodiment, an IQ imbalance calibration module for a phase quantization ADC, an IQ imbalance input signal of the phase quantization ADC is generated after passing through a quadrature system, and an actual vector modulation signal can be represented by equation (1) because an error exists in the actual quadrature system:

S(t)＝(C_I+I(t))cos(ωt)+(C_Q+k×Q(t))sin(ωt-θ) (1)

in formula (1): CI and CQ represent dc signals within the channel, k represents an imbalance coefficient of IQ, and θ represents a quadrature error between the IQ signals.

Adding all phase gain and offset error to obtain Q₀And I₀Expression (2) and expression (3):

Q₀＝A sin(ω+θ)+a (2)

I₀＝B cosω+b (3)

in the formulas (2) and (3), A and B are gain errors, a and B are offset errors, and theta is the phase deviation between IQs;

therefore, as shown in fig. 1, a calibration module is disposed between the quadrature system and the phase quantization ADC, and is configured to calibrate an IQ quadrature signal output by the quadrature system and transmit the calibrated IQ quadrature signal to the phase quantization ADC;

as shown in fig. 2, the calibration module is composed of an offset error calibration module, a gain error calibration module, a phase error calibration module and a timing control module, and the four modules respectively perform different functions to remove offset errors, gain errors and phase errors in IQ imbalance;

as shown in fig. 6, the timing control module is composed of a single cycle generation module and a half cycle generation module. Single period generation module pair received initial signal Q₀And an initial signal I₀Performs periodic processing to output signal Q₀Single periodic signal T _ Q1, original signal I₀At a cycle number T _ I1;

in specific implementation, as shown in fig. 7, the single period generation module is composed of 2 zero-crossing comparators, 2 rising edge flip-flops, 4 falling edge flip-flops, 2 adders, 4 subtractors, and 1 integrator;

the first zero-crossing comparator receives an initial signal I₀And outputs a control signal C _ I₀；

The first falling edge trigger receives a level signal with an initial value of '1' and a control signal C _ I₀And outputs a signal D1_ I₀；

The first rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ I₀And outputs a signal D2_ I₀；

The fifth subtractor receives the signal D1_ I₀And signal D2_ I₀And outputs a signal S _ I₀；

The first adder receives the signal S _ I₀And a control signal C _ I₀And outputs a signal A _ I₀；

The second falling edge trigger receives a level signal with an initial value of '1' and a control signal A _ I₀And outputs a signal D3_ I₀；

The sixth subtractor receives the subtracted signal D1_ I₀And a subtraction signal D3_ I₀And outputs a signal T _ I1;

the sixth integrator receives the signal T _ I1 and outputs the self-integration result as a period number T;

the second zero-crossing comparator receives an initial signal Q₀And outputs a control signal C _ Q₀；

The third falling edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₀And outputs a signal D1_ Q₀；

The second rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₀And outputs a signal D2_ Q₀；

The seventh subtractor receives the signal D1_ Q₀And signal D2_ Q₀And outputs a signal S _ Q₀；

The second adder receives the signal S _ Q₀And a control signal C _ Q₀And outputs a signal A _ Q₀；

The fourth falling edge trigger receives a level signal with an initial value of '1' and a control signal A _ Q₀And outputs a signal D3_ Q₀；

The eighth subtractor receives the subtracted signal D1_ Q₀And a subtraction signal D3_ Q₀And outputs a signal T _ Q1.

As shown in FIG. 2, the offset error calibration module receives an initial signal Q input from the outside₀And an initial signal I₀And single periodic signals T _ Q1 and T _ I1 output by the timing control module, and the initial signal Q is synchronized in one period₀And an initial signal I₀Performing integration processing to obtain offset compensation factors a and b, compensating by using the offset compensation factors a and b, and outputting the Q after first calibration₁Signal and I after first calibration₁A signal;

in a specific implementation, as shown in fig. 3, the offset error calibration module is composed of 2 integrators, 2 dividers, and 2 subtractors;

the first integrator receives an initial signal Q₀And as the integrated number and the signal T _ Q1 and as the integration interval, thereby outputting the offset error factor Ta with the multiple of the period;

the first divider receives the offset error factor Ta with the multiple of the period number and serves as a dividend and the period number T and serves as a divisor, and therefore the offset error factor a is output;

the first subtracter receives an initial signal Q₀And as the subtracted and offset error factor a and as the subtracted number, to output the first calibrated Q₁A signal;

the second integrator receives the initial signal I₀And as the integrated number and the signal T _ I1 and as the integration interval, thereby outputting the offset error factor Tb with multiple periods;

the second divider receives the offset error factor Tb with the multiple of the period number and serves as a dividend and the period number T and serves as a divisor, and therefore the offset error factor b is output;

the second subtracter receives the initial signal I₀And as the subtracted and offset error factor b and as the subtracted number, to output the first calibrated I₁A signal.

As shown in FIG. 2, the half-cycle generation module pairs the received first calibrated Q₁Signal and I after first calibration₁The signal is processed by half-cycle signal generation, and the output signal is Q after first calibration₀Signal T _ Q2 of half cycle of signal and I after first calibration₀Signal T _ I2, which is a half cycle of the signal;

in specific implementation, as shown in fig. 8, the half-cycle module is composed of 2 zero-crossing comparators, 2 rising edge flip-flops, 2 falling edge flip-flops, and 2 subtractors;

the third zero-crossing comparator receives the signal Q after the first calibration₁And outputs a control signal C _ Q₁；

The fifth falling edge trigger receives a level signal with an initial value of '1' and the control signal C _ Q₁And outputs a signal D1_ Q₁；

The third rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₁And outputs a signal D2_ Q₁；

The ninth subtractor receives the signal D1_ Q₁And signal D2_ Q₁And outputs a signal T _ Q2;

fourth step ofThe zero-crossing comparator receives the signal I after the first calibration₁And outputs a control signal C _ I₁；

The sixth falling edge trigger receives a level signal with an initial value of '1' and the control signal C _ I₁And outputs a signal D1_ I₁；

The fourth rising edge trigger receives a level signal with an initial value of '1' and the control signal C _ I₁And outputs a signal D2_ I₁；

The tenth subtractor receives the signal D1_ I₁And signal D2_ I₁And outputs a signal T _ I2.

As shown in FIG. 2, the gain error calibration module receives the first calibrated Q₁Signal and I after first calibration₁First calibrated Q output by signal and time sequence control module₀Signal T _ Q2 of half period of signal and I after first calibration₀Signal T _ I2, and calibrating the first Q within a half cycle₀Signal and I after first calibration₀Performing integral processing on the signal to obtain a gain compensation factor K, and then utilizing the gain compensation factor K to perform first calibration on the I₁Compensating the signal and outputting the finally calibrated I₂A signal;

in a specific implementation, as shown in fig. 4, the gain error calibration module is composed of 1 multiplier, 2 integrators, and 1 divider;

the third integrator receives the signal Q after the first calibration₁And as the integrated number and the signal T _ Q2 and as the integration interval, thereby outputting a result a;

the fourth integrator receives the signal I after the first calibration₁And as the integrated number and the signal T _ I2 and as the integration interval, thereby outputting a result B;

a third divider receives the result A as a dividend and the result B as a divisor, thereby outputting a gain compensation factor K;

the first multiplier receives the gain compensation factor K and the signal I after the first calibration₁And outputs the finally calibrated I₂A signal.

As shown in FIG. 2, the phase error calibration module receives the first calibrated Q₁Signal and final calibrated I₂First calibrated Q output by signal and time sequence control module₁Half period of signal T _ Q2, I after first calibration₁Half period T _ I2 and period T of the signal, and for Q after the first calibration₁Half period of signal T _ Q2 and I after first calibration₁Performing difference processing on the half period T _ I2 of the signal to obtain an included angle theta, and then utilizing a compensation formula of the included angle theta to calibrate the Q after the first time₁Compensating the signal and outputting the finally calibrated Q₂A signal.

In specific implementation, as shown in fig. 5, the phase error calibration module is composed of 2 subtractors, 1 absolute value module, 1 integrator, 1 trigonometric function module, and 2 multipliers;

the third subtractor receives the signal T _ Q2 as a decremented number and the signal T _ I2 as a decremented number, thereby outputting a signal EN;

the absolute value module receives a signal EN and outputs a signal | EN;

the fifth integrator receives the signal | EN | and outputs the self integration result as a phase angle clamping difference theta;

the trigonometric function module receives the phase included angle difference theta and outputs a signal csc theta and a signal cot theta;

the second multiplier receives the signal csc theta and receives the signal Q after the first calibration₁And outputs a signal csc theta x Q₁；

The third multiplier receives the signal cot θ and the finally calibrated I₂Signal and output signal cot theta x I₂；

The fourth subtractor receives the signal csc θ × Q₁And signal cot θ × I₂And outputs the final calibrated Q₂A signal.

In this embodiment, in order to observe the calibration effect, firstly add an offset error, a gain error and a phase error to IQ, and then access a phase quantization ADC with a 6bit precision and a sampling rate of 10MHz, compare how the effect before and after calibration is by observing the change of ENOB before and after calibration, specifically, the method includes the following steps:

step 1, utilizing a rising edge trigger and a falling edge trigger to carry out pair on initial signals Q₀And I₀Processing to obtain an initial signal Q₀And the initial signal I and the single periodic signal T _ Q1₀The single periodic signal T _ I1; and processing the single periodic signal T _ I1 by using an integrator to obtain a periodic number T, wherein the specific signal flow is as follows: at an initial signal I₀Firstly, a signal C _ I0 obtained by the first zero-crossing comparator is used as an enabling signal of a first rising edge trigger and a first falling edge trigger, then a signal D1_ I0 obtained by the first falling edge trigger is subtracted from a signal D2_ I0 obtained by the first rising edge trigger to obtain a new signal S _ I0, then a signal C _ I0 obtained by the first zero-crossing comparator is added to obtain a new signal A _ I0, and the new signal A _ I0 is used as an enabling signal of a second falling edge trigger to obtain a new signal D3_ I0 which is subtracted from a signal D1_ I0 obtained by the first falling edge trigger to obtain a single periodic signal T _ I1; signal Q₀First, the signal C _ Q0 obtained by the second zero-crossing comparator is used as an enabling signal of a second rising edge trigger and a third falling edge trigger, then the signal D1_ Q0 obtained by the third falling edge trigger is subtracted from the signal D2_ Q0 obtained by the second rising edge trigger to obtain a new signal S _ Q0, then the signal C _ Q0 obtained by the previous second zero-crossing comparator is added to obtain a new signal A _ Q0, and the new signal A _ Q0 used as an enabling signal of a fourth falling edge trigger is used to obtain a new signal D3_ Q0 which is subtracted from the signal D1_ Q0 obtained by the third falling edge trigger to obtain a single periodic signal T _ Q1. The single period signal T _ I1 is then self-integrated to obtain the period number T, and the single period signal T _ Q1, the single period signal T _ I1 and the period number T are then output.

Step 2, respectively aligning the initial signals I in a single period₀Integration within a single periodic signal T _ I1 and an initial signal Q₀The integration processing is performed in the single periodic signal T _ Q1, as shown in the formula (4) to the formula (7), to obtain the offset compensation factor aAnd b;

step 3, initial signal I₀Subtracting the offset compensation factor a to obtain I after the first calibration₁A signal; will be the initial signal Q₀Subtracting the offset compensation factor b as shown in the formulas (8) and (9) to obtain the Q after the first calibration₁A signal;

Q₁＝A sin(ω+θ) (8)

I₁＝B cosω (9)

step 4, respectively carrying out I calibration for the first time by utilizing a rising edge trigger and a falling edge trigger₁Sum of signals Q₁Processing the signal to obtain I after the first calibration₁Signal T _ I2 of half cycle of signal and Q after first calibration₁The signal T _ Q2 is a half-cycle signal, and the specific signal flow is as follows: inputting Q after first calibration₁The signal C _ Q1 obtained after the signal passes through the third zero-crossing comparator is used as the enabling signals of the third rising edge trigger and the fifth falling edge trigger, and then the signal D1_ Q1 obtained by the fifth falling edge trigger is subtracted from the signal D2_ Q1 obtained by the third rising edge trigger to obtain the Q after the first calibration₁Signal T _ Q2 for half the period of the signal. After first calibration I₁The signal C _ I1 obtained after the signal passes through the fourth zero-crossing comparator is used as a fourth rising edge trigger and a sixth falling edge triggerThe enable signal of the edge flip-flop is then subtracted from the signal D1_ I1 derived from the sixth falling edge flip-flop and the signal D2_ I1 derived from the fourth rising edge flip-flop to obtain I after the first calibration₁Signal T _ I2, one half cycle of the signal.

Step 5, respectively carrying out first calibration on the I in a half period₁Signal and Q₁The signals are integrated as shown in equations (10) and (11) to obtain results a and B.

And dividing A and B to obtain a gain compensation factor K as shown in formula (12):

K＝A/B (12)

step 6, carrying out calibration on the I after the first calibration₁Multiplying the signal by a gain compensation factor K as shown in equation (13) to obtain the final calibrated I₂A signal;

I₂＝I₁×K (13)

and 7, subtracting the half-period signal T _ Q2 from the half-period signal T _ I2 to obtain a signal EN, and performing absolute value and integration processing on the signal EN to obtain an initial signal Q₀And an initial signal I₀Phase angle difference θ of (a); obtaining the final calibrated Q by using the formula (1)₂The signal is input to a phase quantization ADC.

FIG. 9 is a graph of the uncalibrated output spectrum of the system with an input signal normalized to 0.103 for an IQ mismatch error of 0.1, a gain error of 10%, and a phase error of 0.1, showing that ENOB is reduced from 6 bits to 3.8 bits at low frequencies due to the error.

Fig. 10 shows the calibrated output spectrum of the system with the normalized frequency of the input signal of 0.103 when the IQ mismatch error is 0.1, the gain error is 10%, and the phase error is 0.1, and comparing with fig. 9, it can be seen that the frequency of ENOB is increased from 3.8 to 5.8 at low frequency, the accuracy of the phodc is significantly improved, and the calibration effect is significant.

FIG. 11 is a graph of the uncalibrated output spectrum of a system with an input signal normalized to 0.403 according to an embodiment with an IQ mismatch error of 0.1, a gain error of 10%, and a phase error of 0.1, showing that ENOB is reduced from 6 bits to 3.8 bits at high frequencies due to the error.

Fig. 12 is a graph of the calibrated output spectrum of the system with the input signal normalized frequency of 0.403 when the IQ mismatch error is 0.1, the gain error is 10%, and the phase error is 0.1, and comparing with fig. 11, it can be seen that the frequency of ENOB is increased from 3.8 to 5.8 at high frequency, the accuracy of the phodc is significantly improved, and the calibration effect is significant.

Claims (7)

1. An IQ imbalance calibration module for a phase quantization ADC is characterized in that the calibration module is arranged between a quadrature system and the phase quantization ADC and used for calibrating IQ quadrature signals output by the quadrature system and then transmitting the IQ imbalance signals to the bit quantization ADC;

the calibration module consists of an offset error calibration module, a gain error calibration module, a phase error calibration module and a time sequence control module;

the time sequence control module is composed of a single period generation module and a half period generation module, wherein the single period generation module is used for receiving the initial signal Q₀And an initial signal I₀Performs periodic processing to output signal Q₀Single periodic signal T _ Q1, original signal I₀At a cycle number T _ I1;

the offset error calibration module receives an initial signal Q input from the outside₀And an initial signal I₀And single periodic signals T _ Q1 and T _ I1 output by the timing control module, and the initial signal Q is synchronized in one period₀And an initial signal I₀Performing integration processing to obtain offset compensation factors a and b, compensating by using the offset compensation factors a and b, and outputting the Q after first calibration₁Signal and I after first calibration₁A signal;

the half-cycle generation module is used for receiving the Q after the first calibration₁Signal and I after first calibration₁The signal is processed by half-cycle signal generation, and the output signal is Q after first calibration₀Signal T _ Q2 of half cycle of signal and I after first calibration₀Signal T _ I2, which is a half cycle of the signal;

the gain error calibration module receives the Q after the first calibration₁Signal and I after first calibration₁First calibrated Q output by signal and time sequence control module₀Signal T _ Q2 of half period of signal and I after first calibration₀Signal T _ I2, and calibrating the first Q within a half cycle₀Signal and I after first calibration₀Performing integral processing on the signal to obtain a gain compensation factor K, and then utilizing the gain compensation factor K to perform I after the first calibration₁Compensating the signal and outputting the finally calibrated I₂A signal;

the phase error calibration module receives the Q after the first calibration₁Signal and final calibrated I₂First calibrated Q output by signal and time sequence control module₁Half period of signal T _ Q2, I after first calibration₁Half period T _ I2 and period T of the signal, and for Q after the first calibration₁Half period of signal T _ Q2 and I after first calibration₁Carrying out difference processing on the half period T _ I2 of the signal to obtain an included angle theta, and then utilizing a compensation formula of the included angle theta to carry out Q calibration after the first time₁Compensating the signal and outputting the finally calibrated Q₂A signal.

2. The IQ imbalance calibration module for a phase quantization ADC of claim 1, wherein the single period generation module consists of 2 zero-crossing comparators, 2 rising edge flip-flops, 4 falling edge flip-flops, 2 adders, 4 subtractors and 1 integrator;

the first zero-crossing comparator receives an initial signal I₀And outputs a control signal C _ I₀；

The first falling edge trigger receives a level signal with an initial value of '1' and the control signal C _ I₀And outputs a signal D1_ I₀；

The first rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ I₀And outputs a signal D2_ I₀；

The fifth subtractor receives the signal D1_ I₀And signal D2_ I₀And outputs a signal S _ I₀；

The first adder receives the signal S _ I₀And a control signal C _ I₀And outputs a signal A _ I₀；

The second falling edge trigger receives a level signal with an initial value of '1' and a control signal A _ I₀And outputs a signal D3_ I₀；

The sixth subtractor receives the subtracted signal D1_ I₀And a subtraction signal D3_ I₀And outputs a signal T _ I1;

the sixth integrator receives the signal T _ I1 and outputs the self-integration result as a period number T;

the second zero-crossing comparator receives an initial signal Q₀And outputs a control signal C _ Q₀；

The third falling edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₀And outputs a signal D1_ Q₀；

The second rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₀And outputs a signal D2_ Q₀；

The seventh subtractor receives the signal D1_ Q₀And signal D2_ Q₀And outputs a signal S _ Q₀；

The second adder receives the signal S _ Q₀And a control signal C _ Q₀And outputs a signal A _ Q₀；

The fourth falling edge trigger receives a level signal with an initial value of '1' and a control signal A _ Q₀And outputs a signal D3_ Q₀；

The eighth subtractor receives the subtracted signal D1_ Q₀And a subtraction signal D3_ Q₀And outputs a signal T _ Q1.

3. The IQ imbalance calibration module for a phase quantization ADC according to claim 1, wherein the misadjustment error calibration module consists of 2 integrators, 2 dividers, 2 subtractors;

the first integrator receives an initial signal Q₀And as the integrated number and the signal T _ Q1 and as the integration interval, thereby outputting the offset error factor Ta with the multiple of the period;

the first divider receives the offset error factor Ta with the multiple of the period number and serves as a dividend and the period number T and serves as a divisor, and therefore the offset error factor a is output;

the first subtracter receives an initial signal Q₀And as the subtracted and offset error factor a and as the subtracted number, to output the first calibrated Q₁A signal;

the second integrator receives the initial signal I₀And as the integrated number and the signal T _ I1 and as the integration interval, thereby outputting the offset error factor Tb with multiple periods;

the second divider receives the offset error factor Tb with the multiple of the period number and serves as a dividend and the period number T and serves as a divisor, and therefore the offset error factor b is output;

the second subtracter receives the initial signal I₀And as the subtracted and offset error factor b and as the subtracted number, to output the first calibrated I₁A signal.

4. The IQ imbalance calibration module for a phase quantization ADC of claim 1, wherein the half-cycle module consists of 2 zero-crossing comparators, 2 rising-edge flip-flops, 2 falling-edge flip-flops, and 2 subtractors;

the third zero-crossing comparator receives the signal Q after the first calibration₁And outputs a control signal C _ Q₁；

Fifth falling edge triggerReceiving a level signal with an initial value of '1' and a control signal C _ Q₁And outputs a signal D1_ Q₁；

The third rising edge trigger receives a level signal with an initial value of '1' and a control signal C _ Q₁And outputs a signal D2_ Q₁；

The ninth subtractor receives the signal D1_ Q₁And signal D2_ Q₁And outputs a signal T _ Q2;

the fourth zero-crossing comparator receives the signal I after the first calibration₁And outputs a control signal C _ I₁；

The sixth falling edge trigger receives a level signal with an initial value of '1' and the control signal C _ I₁And outputs a signal D1_ I₁；

The fourth rising edge trigger receives a level signal with an initial value of '1' and the control signal C _ I₁And outputs a signal D2_ I₁；

The tenth subtractor receives the signal D1_ I₁And signal D2_ I₁And outputs a signal T _ I2.

5. The IQ imbalance calibration module for a phase quantization ADC of claim 1, wherein the gain error calibration module consists of 1 multiplier, 2 integrators, and 1 divider;

the third integrator receives the signal Q after the first calibration₁And as the integrated number and the signal T _ Q2 and as the integration interval, thereby outputting a result a;

the fourth integrator receives the signal I after the first calibration₁And as the integrated number and the signal T _ I2 and as the integration interval, thereby outputting a result B;

a third divider receives the result A as a dividend and the result B as a divisor, thereby outputting a gain compensation factor K;

the first multiplier receives the gain compensation factor K and the signal I after the first calibration₁And outputs the finally calibrated I₂A signal.

6. The IQ imbalance calibration module for a phase quantization ADC of claim 1, wherein the phase error calibration module consists of 2 subtractors, 1 absolute value module, 1 integrator, 1 trigonometric function module and 2 multipliers;

the third subtractor receives the signal T _ Q2 as a decremented number and the signal T _ I2 as a decremented number, thereby outputting a signal EN;

the absolute value module receives a signal EN and outputs a signal | EN;

the fifth integrator receives the signal | EN | and outputs the self integration result as a phase angle clamping difference theta;

the trigonometric function module receives the phase included angle difference theta and outputs a signal csc theta and a signal cot theta;

the second multiplier receives the signal csc theta and receives the signal Q after the first calibration₁And outputs a signal csc theta x Q₁；

The third multiplier receives the signal cot θ and the finally calibrated I₂Signal and output signal cot theta x I₂；

The fourth subtractor receives the signal csc θ × Q₁And signal cot θ × I₂And outputs the final calibrated Q₂A signal.

7. A calibration method for IQ imbalance of a phase quantization ADC is characterized by comprising the following steps:

step 1, in a single period, utilizing a rising edge trigger and a falling edge trigger to carry out pair on initial signals Q₀And I₀Processing to obtain an initial signal Q₀And the initial signal I and the single periodic signal T _ Q1₀The single periodic signal T _ I1; processing the single periodic signal T _ I1 by using an integrator to obtain a period number T;

step 2, respectively aiming at the initial signals I in a single period₀And Q₀Performing integration processing to obtain offset compensation factors a and b;

step 3, initial signal I₀Subtracting the offset compensation factor a to obtain I after the first calibration₁A signal; will be the initial signal Q₀Subtracting the offset compensation factor b to obtain the Q after the first calibration₁A signal;

step 4, in a half period, respectively using a rising edge trigger and a falling edge trigger to respectively carry out I after the first calibration₁Sum of signals Q₁Processing the signal to obtain I after the first calibration₁Signal T _ I2 of half cycle of signal and Q after first calibration₁A signal T _ Q2 for half the period of the signal;

step 5, respectively carrying out first calibration on the I in a half period₁Signal and Q₁Performing integral processing on the signal to obtain results A and B, and dividing the results A and B to obtain a gain compensation factor K;

step 6, carrying out calibration on the I after the first calibration₁Multiplying the signal by a gain compensation factor K to obtain the finally calibrated I₂A signal;

and 7, subtracting the half-period signal T _ Q2 from the half-period signal T _ I2 to obtain a signal EN, and performing absolute value and integration processing on the signal EN to obtain an initial signal Q₀And an initial signal I₀Phase angle difference θ of (a); obtaining the final calibrated Q by using the formula (1)₂Signals are input into a phase quantization ADC:

Q₂＝cscθ×Q₁-cotθ×I₂ (1)。

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