CN113381651A - Bus current decomposition circuit, commutation error compensation system and method and motor - Google Patents
Bus current decomposition circuit, commutation error compensation system and method and motor Download PDFInfo
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- CN113381651A CN113381651A CN202110676010.7A CN202110676010A CN113381651A CN 113381651 A CN113381651 A CN 113381651A CN 202110676010 A CN202110676010 A CN 202110676010A CN 113381651 A CN113381651 A CN 113381651A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/14—Electronic commutators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/28—Arrangements for controlling current
Abstract
The present disclosure relates to a bus current decomposition circuit, a commutation error compensation system, a method and a motor, the decomposition circuit comprising: the device comprises a current sampling module, a signal amplification module, a line switching module, two low-pass filtering branches and a signal integration module; the current sampling module is connected to the bus current to be detected and converts the bus current into an initial voltage signal; the signal amplification module amplifies the initial voltage signal; the line switching module decomposes the initial voltage signal into a first decomposition voltage and a second decomposition voltage through switching, wherein the first decomposition voltage corresponds to the bus current of the first half period, and the second decomposition voltage corresponds to the bus current of the second half period; the two low-pass filtering branches respectively filter the first decomposition voltage and the second decomposition voltage correspondingly; the signal integration module obtains corresponding first decomposition current and second decomposition current through data processing including integration based on the first decomposition voltage and the second decomposition voltage, and obtains bus current feedback quantity and commutation error feedback quantity.
Description
Technical Field
The disclosure relates to the technical field of motors, in particular to a bus current decomposition circuit, a commutation error compensation system, a commutation error compensation method and a motor.
Background
The existing commutation error compensation method based on motor current signals constructs feedback quantity in a mode of sampling phase current or line current, and then establishes a closed-loop control system to control commutation errors.
However, on one hand, the current high-frequency noise has an influence on the bus (or phase current) sampling, which results in low accuracy of phase change error compensation; on the other hand, in the conventional method, although the feedback amount of the configuration based on the current integration can attenuate the high-frequency noise, the number of points of sampling the current per commutation period is small when the motor rotates at a high speed, and therefore, the integral calculation is misaligned, thereby lowering the precision of commutation error compensation.
Disclosure of Invention
In order to solve the technical problems or at least partially solve the technical problems, the present disclosure provides a bus current decomposition circuit, a commutation error compensation system, a commutation error compensation method, and a motor capable of improving commutation error compensation accuracy.
The utility model provides a bus current decomposition circuit, which comprises a current sampling module, a signal amplification module, a circuit switching module, two low-pass filtering branches and a signal integration module;
the current sampling module is connected to the bus current to be detected and converts the bus current into an initial voltage signal;
the signal amplification module amplifies the initial voltage signal;
the line switching module decomposes the initial voltage signal into a first decomposition voltage and a second decomposition voltage through switch switching, wherein the first decomposition voltage corresponds to the bus current in the first half period, and the second decomposition voltage corresponds to the bus current in the second half period;
the two low-pass filtering branches respectively filter the first decomposition voltage and the second decomposition voltage correspondingly;
the signal integration module obtains corresponding first decomposition current and second decomposition current through data processing including integration based on the first decomposition voltage and the second decomposition voltage, and obtains bus current feedback quantity and commutation error feedback quantity.
In some embodiments, the current sampling module comprises a sampling resistor;
the sampling resistor is connected between the access end of the bus current to be detected and the ground in series, and the signal amplification module is connected to two ends of the sampling resistor in parallel.
In some embodiments, the signal amplification module comprises a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor;
the first resistor and the second resistor are respectively connected to two ends of the sampling resistor, the other end of the first resistor is connected to the inverting input end of the first operational amplifier, and the other end of the second resistor is connected to the non-inverting input end of the first operational amplifier; the third resistor is connected between the non-inverting input end of the first operational amplifier and the other ground, and the fourth resistor is connected between the inverting input end and the output end of the first operational amplifier; the output end of the first operational amplifier is also connected with the input end of the line switching module.
In some embodiments, the line switching module comprises an analog switch; the input end of the analog switch is used as the input end of the line switching module, and the analog switch further comprises a control end, a first output end and a second output end;
the first output end and the second output end are respectively communicated with the two low-pass filtering branches in a one-to-one correspondence manner;
the control end of the analog switch controls the first output end to be communicated with the input end in the first half period, and controls the second output end to be communicated with the input end in the second half period.
In some embodiments, the low-pass filtering branch comprises a second operational amplifier, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor;
the fifth resistor and the sixth resistor are connected in series between the output end of the line switching module and the non-inverting input end of the second operational amplifier; one end of the first capacitor is connected between the fifth resistor and the sixth resistor, and the other end of the first capacitor is connected with the output end of the second operational amplifier; one end of the second capacitor is connected between the sixth resistor and the non-inverting input end of the second operational amplifier, and the other end of the second capacitor is grounded; the output end of the second operational amplifier is also connected with the inverting input end of the second operational amplifier.
In some embodiments, the signal integration module comprises a first arithmetic unit, a second arithmetic unit and two data processing chips;
the two data processing chips are respectively connected with the two low-pass filtering branches in a one-to-one correspondence manner, the output ends of the two signal processing chips are both connected with the first arithmetic unit, and the output ends of the two signal processing chips are both connected with the second arithmetic unit;
the two data processing chips reversely derive the first decomposition current and the second decomposition current based on the first decomposition voltage and the second decomposition voltage respectively;
the first operation unit performs addition operation based on the first split current and the second split current to obtain the bus current feedback quantity;
the second operation unit performs subtraction operation based on the first split current and the second split current to obtain the commutation error feedback quantity.
The present disclosure also provides a commutation error compensation system comprising any of the above circuits.
In some embodiments, the system further comprises a commutation error control loop and a current loop control loop;
the bus current feedback quantity returns to the current loop control loop and is used for realizing bus current closed-loop control of the motor;
and the commutation error feedback quantity is returned to the commutation error control loop and is used for realizing closed-loop control of the commutation error.
The present disclosure also provides a commutation error compensation method, including:
determining a commutation error feedback quantity based on any one of the circuits;
compensating in a commutation error control loop based on the commutation error feedback quantity to realize closed-loop control of the commutation error;
or
And realizing closed-loop control of commutation errors based on any system.
The present disclosure also provides a brushless dc motor, which includes any one of the above circuits, or includes any one of the above systems, or implements commutation error compensation based on any one of the above methods.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
in the bus current decomposition circuit provided by the embodiment of the disclosure, the current sampling module can convert the bus current to be detected into an initial voltage signal and output the initial voltage signal to the signal amplification module; the signal amplification module can amplify the initial voltage signal so as to improve the signal-to-noise ratio; the line switching module can decompose the initial voltage signal into a first decomposition voltage and a second decomposition voltage through switching; the first split voltage corresponds to the bus current in the first half period, and the second split voltage corresponds to the bus current in the second half period; thus, the bus current is correspondingly decomposed into two parts of current; the two low-pass filtering branches can respectively and correspondingly filter the first decomposition voltage and the second decomposition voltage so as to reduce high-frequency noise and improve the accuracy of feedback quantity detection; the signal integration module can correspondingly determine a first decomposition current and a second decomposition current based on the first decomposition voltage and the second decomposition voltage, wherein the first decomposition voltage and the second decomposition voltage respectively comprise a process of integrating the bus current of the first half period corresponding to the first decomposition voltage and the bus current of the second half period corresponding to the second decomposition voltage, and the bus current feedback quantity and the commutation error feedback quantity are obtained through subsequent calculation. Therefore, through integration processing, the problem of inaccurate integral calculation caused by a small number of sampling points is solved, the precision of the feedback quantity is improved, and the precision of commutation error compensation is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic diagram illustrating a bus current variation trend when commutation is accurate in a conventional motor;
fig. 2 is a schematic diagram illustrating a bus current variation trend when commutation lags in the conventional motor;
fig. 3 is a schematic diagram illustrating a bus current variation trend in a conventional motor during phase commutation advance;
fig. 4 is a schematic view illustrating a bus current decomposition principle provided by the embodiment of the present disclosure;
fig. 5 is a schematic diagram of a bus current decomposition logic provided in an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a bus current decomposition circuit according to an embodiment of the disclosure;
FIG. 7 is a schematic diagram of one circuit element of the circuit shown in FIG. 6;
fig. 8 is a schematic structural diagram of a commutation error compensation system according to an embodiment of the present disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
The bus current decomposition circuit provided by the embodiment of the disclosure can be applied to brushless direct current motor control, adds new circuit components on the basis of the existing circuit structure, realizes the decomposition of bus current (hereinafter, may be referred to as "current") by setting the connection relation between the new circuit components, and correspondingly obtains the bus current feedback quantity and the commutation error feedback quantity so as to realize the bus current feedback control and the commutation error compensation. The bus current can be divided into two parts through the bus current decomposition circuit, namely the bus current in the first half period and the bus current in the second half period, the integral values of the bus current in each commutation period are obtained after filtering respectively, then the two integral values are processed, for example, difference is obtained, the integral difference is used as commutation error feedback quantity, a closed loop for commutation error compensation is established based on the integral difference, and the precision of commutation error compensation is improved.
The bus current decomposition circuit, the commutation error compensation system, the commutation error compensation method, the motor controlled based on the bus current decomposition circuit, and the principle of accurately compensating the commutation error provided by the embodiment of the present disclosure are exemplarily described below with reference to fig. 1 to 8.
For example, fig. 1-3 show the variation trend of the bus current when the commutation is accurate, the commutation is delayed and the commutation is advanced, respectively, during the motor control process. Wherein the horizontal axis is phase, the vertical axis is bus current, SA、SBAnd SCRepresenting the commutation signals, i, of the phases of a three-phase motor, respectively1、i2And i3Respectively representing the current during commutation, also understood as the current on both sides of the commutation point,. phi. representing the commutation error,. theta.aRepresents the position of the beginning of the commutation period, and the symbols in the figures are the same, and the same symbols are not repeated in the following. In each phase change period, dividing the bus current into two parts according to half of the period; when the commutation is accurate (phi is 0), the areas of the two partial regions are equal, such as the areas of the two different filling regions in fig. 1 are the same; when the phase change lags (phi)>0) The area corresponding to the current in the first half period is smaller than that in the second half periodProduct, as shown in FIG. 2; when the commutation is advanced (phi)<0) The area corresponding to the current in the first half cycle is larger than the area corresponding to the current in the second half cycle, as shown in fig. 3. Based on this, a commutation error closed-loop correction system, i.e., a commutation error compensation system, can be established using the difference between the current of the first half cycle and the current of the second half cycle as a feedback amount for commutation error compensation. When the bus current is controlled to be in a symmetrical state, the area corresponding to the current in the first half period is equal to the area corresponding to the current in the second half period, and the commutation error is eliminated.
In this connection, the bus current needs to be split, for example, in the manner shown in fig. 4, the bus current can be split into two parts, namely the bus current iLDecomposed into front 1/2 periodic currents iL1And post 1/2 period current iL2Two portions corresponding to the current for the preceding and following times T/2 of a complete cycle T, respectively. And then, filtering the two parts of current respectively, and then summing to obtain a current value which is equal to a bus current filtering value used for current loop control. Thus, the bus current i for current loop controlcCan be formed byL1And iL2I obtained after respective filteringe1And ie2Are added to obtain ic＝ie1+ie2. Wherein ie1For the first split current, i, obtained after filtering and integratione2Is the second split current after filtering and integration. On the other hand, the feedback amount of the commutation error, i.e., the commutation error compensation current, can be obtained based on the difference therebetween, i.e., ie＝ie2-ie1The commutation error is equal to ieThe existence relationship is shown in table 1.
TABLE 1 relationship table of commutation error phi and commutation compensation current
| Lag in commutation | Phase change advance | Accurate phase change | |
| Error of commutation | φ>0 | φ<0 | φ＝0 |
| Compensating current | ie>0 | ie<0 | ie＝0 |
Thus, there is a positive correlation between the commutation error and the magnitude of the compensation current. Based on this, when ieThe output quantity of the controller is the commutation error compensation quantity, for example, the output quantity is calculated by combining the feedback quantity on the basis of the input quantity; then, ieConverging to zero, the commutation error will be compensated.
In conjunction with FIG. 4, according to the Fourier decomposition formula, ie1And ie2The product of the area of the oblique line filling area and the scattered point filling area and 1/T is respectively. Where 1/T can be considered as the gain of the forward path, the forward path is understood as the path from a given value to a controlled quantity, i.e. the path from the input all the way forward without returning to the output. Thus, both split currents can be obtained by multiplying the integral of the current by the forward channel gain, thus essentially using iL1And iL2The integral values distributed in each commutation period avoid the problem of calculation misalignment caused by less sampling points.
On the basis of the above, the decomposition logic of the decomposition circuit provided by the embodiment of the disclosure may be as shown in fig. 5, where SlRepresenting a logic signal generated on the basis of the commutation signal, will SlThe signal is shifted to the right by pi/6 to obtain SrWill SlAnd SrPerforming XOR operation to obtain control signal SwinControl signal SwinFor effecting control of the line switching module 130 (shown in fig. 7) to split the bus current into two portions corresponding to the front and rear half cycles.
Based on logic signal SlThe relationship with the commutation signal can be expressed as:
control signal SwinAND logic signal SlAnd SrThe relationship between can be expressed as:
Swin＝Sl XOR Sr
thus, according to the decomposition logic of FIG. 5, S can be followedwin1 and SwinThe bus current is divided into two parts i respectively when being 0L1And iL2。
On the basis of the above, the bus current decomposition circuit can be as shown in fig. 6, wherein the circuit 10 includes a current sampling module 110, a signal amplifying module 120, a line switching module 130, two low-pass filtering branches 140, and a signal integrating module 150; the current sampling module 110 is connected to the bus current i to be detectedLAnd applying the bus current iLConverting the voltage into an initial voltage signal; the signal amplification module 120 amplifies the initial voltage signal; the line switching module 130 decomposes the initial voltage signal into a first decomposed voltage and a second decomposed voltage by switching, the first decomposed voltage corresponding to the bus current i of the previous half periodL1The second split voltage corresponds to the bus current i of the latter half cycleL2(ii) a The two low-pass filtering branches 140 respectively filter the first decomposition voltage and the second decomposition voltage correspondingly; the signal integration module 150 passes the product of the included products based on the first and second divided voltagesThe divided data are processed to obtain corresponding first decomposition current ie1And a second split current ie2And obtaining the bus current feedback quantity icAnd a commutation error feedback quantity ie。
Wherein, the current sampling module 110 can detect the bus current i to be detectedLConverted into an initial voltage signal, and output to the signal amplification module 120. The signal amplification module 120 can amplify the initial voltage signal to improve the signal-to-noise ratio, so as to improve the accuracy of the feedback quantity. The line switching module 130 can decompose the initial voltage signal into a first decomposition voltage and a second decomposition voltage by switching; wherein the first split voltage corresponds to the bus current i of the previous half periodL1The second split voltage corresponds to the bus current i of the latter half cycleL2(ii) a Thus, the bus current is correspondingly decomposed into two partial currents. The two low-pass filtering branches 140 can respectively and correspondingly filter the first decomposition voltage and the second decomposition voltage to reduce high-frequency noise, so as to improve the accuracy of feedback quantity detection. The signal integration module 150 can correspondingly determine the first split current i based on the first split voltage and the second split voltagee1And a second split current ie2Including the bus current i of the first half period corresponding to the first divided voltageL1Bus current i of the second half period corresponding to the second divided voltageL2Respectively carrying out integration processing, and obtaining a bus current feedback quantity i through subsequent calculationcAnd a commutation error feedback quantity ie. Therefore, through integration processing, the problem of inaccurate integral calculation caused by a small number of sampling points is solved, the precision of the feedback quantity is improved, and the precision of commutation error compensation is improved.
In some embodiments, fig. 7 illustrates a circuit element diagram corresponding to the bus current splitting circuit of fig. 6. With reference to fig. 6 and 7, the bus current decomposition circuit 10 (hereinafter may be referred to simply as "decomposition circuit 10" or "circuit 10") may include a sampling resistor, a differential operational amplifier (or other type of operational amplifier), an analog switch, a filter (including, for example, an operational amplifier, a resistor, and a capacitor); wherein, the sampling resistor RLWill bus current iLConversion to initialAnd the voltage signal is input to the analog switch after being isolated from the power ground through the differential operational amplifier. Then, the analog switch is according to SwinLogic, will bus current iLSplitting into iL1And iL2Two parts are respectively passed through filter and integrated to obtain ie2And ie1. Finally, the bus current feedback quantity is obtained through mathematical operation, for example, after scaling in software, the bus current feedback quantity is obtained through summation of the two (namely ic ═ ie1+ ie2) and is used for current loop control; and obtaining a commutation error feedback quantity by subtracting the two (i.e. ie: ie2-ie1) for commutation error control.
With reference to FIGS. 5 and 7 and the above, it can be understood that SwinIs a 01 digital control signal, when SwinWhen is 1, the analog switch is set to 1, when S iswinWhen 0, the analog switch is set to 2, thereby realizing the decomposition of the current. The scaling is a process of performing reverse-thrust processing on a signal, for example, the bus current to be detected is 10A, the corresponding sampling voltage is 1V, the corresponding digital quantity is 512, and after 512 is obtained, the detection value of the bus current to be detected is obtained through gradual reverse thrust.
In some embodiments, referring to fig. 7, the current sampling module 110 includes a sampling resistor RL(ii) a Sampling resistor RLIs connected in series with a bus current i to be detectedLBetween the access terminal of the signal amplification module 120 and the ground, the signal amplification module is connected in parallel with the sampling resistor RLAt both ends of the same.
By such arrangement, the arrangement mode of the current sampling module 110 is simple, and the whole circuit structure is simplified. When the controller is applied to the motor, the circuit structure in the controller in the motor is simple, the occupied space of the controller is reduced, and the controller and the motor comprising the controller are miniaturized.
In some embodiments, with continued reference to fig. 7, the signal amplification module 120 includes a first operational amplifier OP1A first resistor R1A second resistor R2A third resistor R3And a fourth resistor R4(ii) a A first resistor R1And a second resistor R2Are respectively connected to sampling resistors RLAcross the first resistor R1Is connected to a first operational amplifier OP1The inverting input terminal of (1), the second resistor R2Is connected to a first operational amplifier OP1The non-inverting input terminal of (1); third resistor R3Connected to the first operational amplifier OP1Between the non-inverting input terminal and another ground, a fourth resistor R4Connected to the first operational amplifier OP1Between the inverting input and the output; a first operational amplifier OP1Also connected to the input of the line switching module 130.
Wherein the first operational amplifier OP1The LM124 may be used, and the signal amplifying module 120 can isolate the analog ground from the power ground through the differential operational amplifier, and accurately transmit the amplified voltage signal to the line switching module 130.
In other embodiments, the first operational amplifier OP1Any other type of differential operational amplifier may be used, and is not limited herein.
In some embodiments, with continued reference to fig. 7, the line switching module 130 includes an analog switch SW; the input terminal of the analog switch SW is used as the input terminal of the line switching module 130, and the analog switch SW further includes a control terminal for receiving the control signal SwinA first output terminal 1 and a second output terminal 2; the first output end 1 and the second output end 2 are respectively communicated with the two low-pass filtering branches 140 in a one-to-one correspondence manner; the control end of the analog switch SW controls the first output end 1 to be communicated with the input end in the first half period, and controls the second output end 2 to be communicated with the input end in the second half period.
Wherein the control quantity (i.e., control signal) of the analog switch SW is Swin. When satisfying SwinWhen the bus current is equal to 0, the first output end 1 of the analog switch SW is communicated with the input end thereof, and the voltage signal corresponding to the bus current is output on the circuit through the analog switch to obtain iL1(ii) a When satisfying SwinWhen the bus current is equal to 1, the second output end of the analog switch SW is communicated with the input end thereof, and the voltage signal corresponding to the bus current is output in a down-circuit mode through the analog switch to obtain iL2。
Thus, the bus circuit can be divided into two parts by the analog switch SW.
For example, the analog switch SW may be ET3157 or any other type of analog switch, which is not limited herein.
In some embodiments, with continued reference to fig. 7, the low pass filtering branch 140 includes a second operational amplifier OP2A fifth resistor R5A sixth resistor R6A first capacitor C1And a second capacitor C2(ii) a Fifth resistor R5And a sixth resistor R6Connected in series to the output terminal of the line switching module 130 and the second operational amplifier OP2Between the non-inverting input terminals; a first capacitor C1Is connected to the fifth resistor R5And a sixth resistor R6The other end is connected with a second operational amplifier OP2An output terminal of (a); second capacitor C2Is connected to the sixth resistor R6And a second operational amplifier OP2The other end of the same phase input end of the transformer is grounded; second operational amplifier OP2And the output terminal of the first operational amplifier OP2Is connected to the inverting input terminal.
The low-pass filtering branch 140 can implement the function of a low-pass filter, which can be implemented by an integrated low-pass filter, and the low-pass filtering branch 140 can allow low-frequency signals to pass through and filter high-frequency signals, so that high-frequency noise can be reduced, and accuracy of feedback quantity detection can be improved conveniently.
Exemplarily, the second operational amplifier OP2LM124 or any other type of operational amplifier may be used, without limitation.
In some embodiments, with continued reference to fig. 7, the signal integration module 150 includes a first operation unit 151, a second operation unit 152, and two data processing chips 155; the two data processing chips 155 are respectively connected with the two low-pass filtering branches 140 in a one-to-one correspondence manner, the output ends of the two signal processing chips 155 are both connected with the first arithmetic unit 151, and the output ends of the two signal processing chips 155 are both connected with the second arithmetic unit 152; the two data processing chips 155 reversely derive the first decomposition current i based on the first decomposition voltage and the second decomposition voltage, respectivelye1And a second split current ie2(ii) a First arithmetic unit 151 is based on first split current ie1And a second split current ie2Carrying out addition operation to obtain a bus current feedback quantity ic(ii) a The second arithmetic unit is based on the first decomposition current ie1And a second split current ie2Carrying out subtraction to obtain commutation error feedback quantity ie。
Wherein the data processing chip 155 is configured to perform the scaling process to obtain the corresponding two-part current, i.e. the first decomposition current ie1And a second split current ie2(ii) a The first arithmetic unit 151 can correct the first split current ie1And a second split current ie2Carrying out addition operation to obtain a bus current feedback quantity ic(ii) a The second arithmetic unit can analyze the first decomposition current ie1And a second split current ie2Carrying out subtraction to obtain commutation error feedback quantity ie。
According to the bus current decomposition circuit provided by the embodiment of the disclosure, the analog switch and the low-pass filter are added on the basis of the existing circuit, and the direct current bus current integral is obtained based on the output of the low-pass filter, so that the interference of high-frequency noise is avoided, and the integral value is not required to be calculated in software in a high-frequency sampling mode. Meanwhile, for the traditional integration method, the sampling frequency is low relative to the frequency conversion when the motor is at a high speed, and the problem of inaccurate integral calculation exists, so that the compensation precision of the commutation error is reduced. In view of this, in the embodiment of the present disclosure, the feedback quantity ieIs the product of the current integral and the forward path gain 1/T. Since the forward path gain 1/T is much greater than 1 at high motor speeds, the integral is naturally amplified and the feedback i iseThe method can accurately reflect the change of the commutation error, thereby being beneficial to realizing the high-precision commutation error compensation.
The embodiment of the disclosure also provides a commutation error compensation system, which comprises any one of the decomposition circuits, and can realize more accurate commutation error compensation.
In some embodiments, fig. 8 illustrates a commutation error compensation system provided by embodiments of the present disclosure. Referring to fig. 8, the system further includes a commutation error control loop 220 and a current loop control loop 210; bus current feedback quantityicReturning to the current loop control circuit 210 for realizing the bus current closed loop control of the motor; commutation error feedback quantity ieAnd returns to the commutation error control loop 220 for closed-loop control of the commutation error.
In combination with the above, decomposition circuit 10 converts bus current iLIs divided into two parts iL1And iL2After low-pass filtering, the integral is corresponded to obtain ie1And ie2(ii) a Summing them to obtain the bus current feedback quantity icThe current loop control circuit can be used for a control loop of a current loop to realize current closed-loop control; the difference between them is calculated to obtain the feedback quantity i of commutation erroreThe method can be used for a commutation error control loop to realize commutation error closed-loop control.
Wherein, in the current loop control loop 210, the feedback quantity i is fed back by the bus currentcAnd a reference amount i of bus currentREFThe deviation of (d) is fed into a PI controller to generate a control quantity. Generating a PWM signal for the Buck converter through a PWM generator; the Buck converter generates a bus current i based on the PWM signalLThe decomposition circuit 10 may be accessed so as to achieve closed loop control. Wherein, the bus current reference iREFProvided by a speed ring.
Wherein, in the commutation error control loop 220, the feedback quantity i of commutation erroreAnd a commutation error reference iref(iref0) is fed into the PI controller, the output of the PI controller is input to the phase shift module, where the three commutation signals S are corrected (i.e. compensated for)A、SBAnd SC. Thereafter, the commutation logic generates an inverter control signal T based on the compensated commutation signal1～T6Thus realizing the phase change of the motor.
In the commutation error compensation system provided by the embodiment of the disclosure, not only is the influence of high-frequency noise during bus current sampling avoided, but also when the motor is at high speed, a high-precision current integral value of the bus current in each commutation period can be obtained without corresponding high-frequency sampling, so that the size of the commutation error can be accurately reflected; therefore, high-precision compensation of the commutation error is ensured when the motor does not have a position sensor for commutation.
The embodiment of the disclosure further provides a commutation error compensation method, which can be implemented based on the decomposition circuit or the commutation compensation system, and has corresponding beneficial effects.
In some embodiments, the method may comprise:
determining a commutation error feedback quantity based on any one of the circuits;
and compensating in the commutation error control loop based on the commutation error feedback quantity to realize closed-loop control of the commutation error.
In some embodiments, the method may implement closed-loop control of commutation error based on any of the systems described above.
The commutation error compensation method provided by the embodiment of the disclosure not only avoids the influence of high-frequency noise during bus current sampling, but also can acquire a high-precision current integral value of the bus current in each commutation period without corresponding high-frequency sampling when the motor is at a high speed, so that the size of the commutation error can be accurately reflected; therefore, high-precision compensation of the commutation error is ensured when the motor does not have a position sensor for commutation.
The disclosed embodiment also provides a brushless direct current motor, for example, a brushless direct current motor without a position sensor, which includes any circuit described above, or includes any system described above, or implements commutation error compensation based on any method described above. Therefore, the motor can realize high-precision commutation error compensation and realize the precise control of the motor.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A bus current decomposition circuit is characterized by comprising a current sampling module, a signal amplification module, a line switching module, two low-pass filtering branches and a signal integration module;
the current sampling module is connected to the bus current to be detected and converts the bus current into an initial voltage signal;
the signal amplification module amplifies the initial voltage signal;
the line switching module decomposes the initial voltage signal into a first decomposition voltage and a second decomposition voltage through switch switching, wherein the first decomposition voltage corresponds to the bus current in the first half period, and the second decomposition voltage corresponds to the bus current in the second half period;
the two low-pass filtering branches respectively filter the first decomposition voltage and the second decomposition voltage correspondingly;
the signal integration module obtains corresponding first decomposition current and second decomposition current through data processing including integration based on the first decomposition voltage and the second decomposition voltage, and obtains bus current feedback quantity and commutation error feedback quantity.
2. The circuit of claim 1, wherein the current sampling module comprises a sampling resistor;
the sampling resistor is connected between the access end of the bus current to be detected and the ground in series, and the signal amplification module is connected to two ends of the sampling resistor in parallel.
3. The circuit of claim 2, wherein the signal amplification module comprises a first operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor;
the first resistor and the second resistor are respectively connected to two ends of the sampling resistor, the other end of the first resistor is connected to the inverting input end of the first operational amplifier, and the other end of the second resistor is connected to the non-inverting input end of the first operational amplifier; the third resistor is connected between the non-inverting input end of the first operational amplifier and the other ground, and the fourth resistor is connected between the inverting input end and the output end of the first operational amplifier; the output end of the first operational amplifier is also connected with the input end of the line switching module.
4. The circuit of any of claims 1-3, wherein the line switching module comprises an analog switch; the input end of the analog switch is used as the input end of the line switching module, and the analog switch further comprises a control end, a first output end and a second output end;
the first output end and the second output end are respectively communicated with the two low-pass filtering branches in a one-to-one correspondence manner;
the control end of the analog switch controls the first output end to be communicated with the input end in the first half period, and controls the second output end to be communicated with the input end in the second half period.
5. The circuit of claim 1, wherein the low-pass filtering branch comprises a second operational amplifier, a fifth resistor, a sixth resistor, a first capacitor and a second capacitor;
the fifth resistor and the sixth resistor are connected in series between the output end of the line switching module and the non-inverting input end of the second operational amplifier; one end of the first capacitor is connected between the fifth resistor and the sixth resistor, and the other end of the first capacitor is connected with the output end of the second operational amplifier; one end of the second capacitor is connected between the sixth resistor and the non-inverting input end of the second operational amplifier, and the other end of the second capacitor is grounded; the output end of the second operational amplifier is also connected with the inverting input end of the second operational amplifier.
6. The circuit of claim 1, wherein the signal integration module comprises a first arithmetic unit, a second arithmetic unit and two data processing chips;
the two data processing chips are respectively connected with the two low-pass filtering branches in a one-to-one correspondence manner, the output ends of the two signal processing chips are both connected with the first arithmetic unit, and the output ends of the two signal processing chips are both connected with the second arithmetic unit;
the two data processing chips reversely derive the first decomposition current and the second decomposition current based on the first decomposition voltage and the second decomposition voltage respectively;
the first operation unit performs addition operation based on the first split current and the second split current to obtain the bus current feedback quantity;
the second operation unit performs subtraction operation based on the first split current and the second split current to obtain the commutation error feedback quantity.
7. A commutation error compensation system comprising the circuit of any one of claims 1-6.
8. The system of claim 7, further comprising a commutation error control loop and a current loop control loop;
the bus current feedback quantity returns to the current loop control loop and is used for realizing bus current closed-loop control of the motor;
and the commutation error feedback quantity is returned to the commutation error control loop and is used for realizing closed-loop control of the commutation error.
9. A commutation error compensation method, comprising:
determining a commutation error feedback quantity based on the circuit of any one of claims 1-6;
compensating in a commutation error control loop based on the commutation error feedback quantity to realize closed-loop control of the commutation error;
or
Closed-loop control of commutation errors is achieved on the basis of the system according to claim 7 or 8.
10. A brushless dc motor comprising a circuit according to any of claims 1-6, or comprising a system according to claim 7 or 8, or implementing commutation error compensation based on the method of claim 9.
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