CN113380179A

CN113380179A - Display device

Info

Publication number: CN113380179A
Application number: CN202110660168.5A
Authority: CN
Inventors: 黄书豪; 王贤军; 苏松宇
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2020-12-22
Filing date: 2021-06-15
Publication date: 2021-09-10
Anticipated expiration: 2041-06-15
Also published as: CN113380179B; TWI747678B; TW202226204A

Abstract

A display device comprises a display area and a peripheral area adjacent to the display area. The peripheral area includes a first data writing unit for writing a first data signal into the first node. The first data writing unit comprises a first switch, a second switch, a third switch and a capacitor. The first terminal of the first switch is coupled to the first node. The first terminal of the second switch is coupled to the second terminal of the first switch, and the control terminal of the second switch is coupled to the first node. The first end of the third switch is coupled to the second end of the second switch, the second end of the third switch is coupled to the second end of the first switch, and the control end of the third switch is coupled to the first node. The first end of the capacitor is coupled to the first node. The display area comprises a first light-emitting unit which is used for emitting light according to a first data signal.

Description

Display device

Technical Field

The present disclosure relates to display technologies, and particularly to a display device.

Background

The display device on the substrate of the display may have substrate abnormality due to metal residue, excessive etching, and the like during the manufacturing process. The manufacturing process of light emitting elements such as micro light emitting diodes is complicated and the cost is high. In addition, the current in the current display device may be affected by the switching characteristics and/or the resistance value of the current path, which may cause the brightness of the display to be uneven. Therefore, how to develop a related art capable of overcoming the above problems is an important issue in the art.

Disclosure of Invention

The embodiment of the invention comprises a display device, which comprises a display area and a peripheral area adjacent to the display area. The peripheral area includes a first data writing unit for writing a first data signal into the first node. The first data writing unit comprises a first switch, a second switch, a third switch and a capacitor. The first terminal of the first switch is coupled to the first node. The first terminal of the second switch is coupled to the second terminal of the first switch, and the control terminal of the second switch is coupled to the first node. The first end of the third switch is coupled to the second end of the second switch, the second end of the third switch is coupled to the second end of the first switch, and the control end of the third switch is coupled to the first node. The first end of the capacitor is coupled to the first node. The display area comprises a first light-emitting unit which is used for emitting light according to a first data signal.

Drawings

Fig. 1 is a schematic diagram of a display according to an embodiment of the present disclosure.

Fig. 2 is a circuit diagram of a display device according to an embodiment of the present disclosure.

Fig. 3 is a timing diagram illustrating operations of a display device according to an embodiment of the present disclosure.

Fig. 4 is a circuit diagram of a display device in the display device according to an embodiment of the present disclosure.

Fig. 5 is a circuit diagram of the display device 200 according to an embodiment of the disclosure.

Fig. 6 is a timing diagram illustrating the operation of the display device according to an embodiment of the present disclosure.

Fig. 7 is a schematic diagram of a display area according to an embodiment of the disclosure.

Fig. 8 is a circuit diagram of a display device according to an embodiment of the present disclosure.

Fig. 9 is a timing chart illustrating a detection operation performed by the display device according to an embodiment of the present invention.

Description of reference numerals:

100: display device

110. 200, 400, 500, 700, 800: display device

120: scanning device

130: data input device

112. 210, 410, 510: peripheral region

114. 220, 420, 520: display area

SL (0) to SL (n), 701, 703, 705: scanning line

S (n-1), S (n + 1): scanning signal

DL (1) to DL (m): data line

DT1, DT 2: data signal

L21 to L24, L41, L43, L52, L53, L71 to L75, L81, L83: light emitting element

211. 212, 411, 511, 512, 811, 812: data writing unit

221-224, 421, 422, 522, 523, 710, 730, 740, 821-824: light emitting unit

VSS, VDD: voltage signal

VC: control signal

RST: reset signal

N21 to N27, N41, N42, N44, N54, N51, N59, N58, N81, N83, N84, N86 to N88: node point

V_TH: level of critical voltage

C21, C21 ', C41, C51, C81, C81': capacitor with a capacitor element

T21-T27, T21 '-T27', T41-T48, T51-T53, T51 '-T53', T56, T57, T54 ', T55', T71-T75, T81-T87, T81 '-T87': switch with a switch body

I21, I22, I41, I7: electric current

P31-P36, P61-P66, P91-P93: phases

VGH: enabling voltage level

VGL: forbidden voltage level

VDT 31-VDT 33, VDT 51-VDT 53, VDT91, VDT 92: voltage level

V21: node voltage

VGS: difference in voltage level

729. 759, S81, S83: containing space

M72, M75: conducting wire

720. 750: repair unit

P71-P73: welding point

K: constant number

Detailed Description

When an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "connected" or "coupled" may also be used to indicate that two or more elements are in mutual engagement or interaction. Moreover, although terms such as "first," "second," …, etc., may be used herein to describe various elements, these terms are used merely to distinguish one element or operation from another element or operation described in similar technical terms. Unless the context clearly dictates otherwise, the terms do not specifically refer or imply an order or sequence nor are they intended to limit the invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

In the following description, numerous implementation details are set forth in order to provide a more thorough understanding of the present disclosure. It should be understood, however, that these implementation details should not be used to limit the disclosure. That is, in some embodiments of the disclosure, such practical details are not necessary. In addition, some conventional structures and elements are shown in the drawings in a simple schematic manner for the sake of simplifying the drawings.

Fig. 1 is a schematic diagram of a display according to an embodiment of the present disclosure. Referring to fig. 1, the display 100 includes a display device 110, a scanning device 120, and a data input device 130. The scan device 120 provides a plurality of scan signals, such as the scan signal S (n-1) and the scan signal S (n) shown in fig. 2, to the display device 110 through the scan lines SL (0) to SL (n). The data input device 130 provides a plurality of data signals, such as the data signals DT1 and DT2 shown in fig. 2, to the display device 110 through the data lines DL (1) to DL (m). Wherein n and m are both positive integers. In some embodiments, the display device 110 may be made of a glass substrate or a plastic substrate, but is not limited thereto.

As shown in fig. 1, the display device 110 includes a peripheral region 112 and a display region 114. In some embodiments, the peripheral region 112 abuts the display region 114. In the embodiment shown in FIG. 1, the peripheral region 112 surrounds a display region 114.

In some embodiments, the peripheral region 112 includes a plurality of data writing units, such as the

data writing units

211 and 212 shown in fig. 2. In some embodiments, the display region 114 includes a plurality of light emitting units, such as the light emitting units 221-224 shown in FIG. 2. In some embodiments, the data writing unit and the light emitting unit in the display device 110 perform data writing operation and light emitting operation according to signals provided by the scanning device 120 and the data input device 130.

For example, the peripheral region 210 shown in FIG. 2 is an embodiment of the peripheral region 112, and the display region 220 is an embodiment of the display region 114. As shown in FIG. 2, the data write

units

211 and 212 in the peripheral region 210 are respectively used for writing data signals DT1 and DT 2. The

light emitting units

221 and 222 in the display area 220 perform a light emitting operation according to the scan signal S (n-1) provided by the scanning device 120. The

light emitting units

223 and 224 in the display area 220 emit light according to the scanning signal s (n) provided by the scanning device 120. In some embodiments, at least one voltage level of the data signal DT1 determines the light emitting intensity of the light emitting elements L21 and L23 of the light emitting

cells

221 and 223, and at least one voltage level of the data signal DT2 determines the light emitting intensity of the light emitting elements L22 and L24 of the light emitting

cells

222 and 224.

In some embodiments, the scan signals S (n-1) and S (n) are transmitted to the display region 114 through the scan lines SL (n-1) and SL (n), respectively, and the data signals DT1 and DT2 are transmitted to the peripheral region 112 through the data lines DL (1) and DL (2), respectively, but the present invention is not limited thereto, and the manner of transmitting the scan signals S (n-1), S (n), and DT1 and DT2 to the display device 110 through other conducting wires is within the scope of the present invention.

Fig. 2 is a circuit diagram of a display device 200 according to an embodiment of the disclosure. Referring to fig. 2, a display device 200 is an embodiment of the display device 110. The display device 200 includes peripheral regions 210 and 230 and a display region 220. The peripheral regions 210 and 230 are adjacent to the display region 220. In the embodiment shown in FIG. 2, the display area 220 is disposed between the peripheral areas 210 and 230. In some embodiments, the peripheral regions 210 and 230 each correspond to a portion of the peripheral region 112 in FIG. 1, and the display region 220 corresponds to the display region 114 in FIG. 1.

As shown in FIG. 2, the display area 220 includes light emitting units 221 to 224. The peripheral region 210 includes

data writing units

211 and 212. In various embodiments, at least one of the

data writing units

211 and 212 may also be included in the peripheral region 230.

In some embodiments, the data writing unit 211 is configured to perform a reset operation according to a reset signal RST to reset the node voltage V21 of the node N21. The data write unit 211 is further used for writing the threshold voltage level V of the switch T22 according to the control signal VC_THWrites to node N21 for the compensation operation. The data write unit 211 is further configured to write the data signal DT1 to the node N21 for data write operation. The

light emitting units

221 and 223 are respectively configured to emit light according to the scan signals S (n-1) and S (n).

In some embodiments, the operations of the data writing unit 212 and the

light emitting units

222 and 224 are similar to the operations of the data writing unit 211 and the

light emitting units

221 and 223, and thus, the repeated description is omitted. The difference between the data write unit 212 and the data write unit 211 includes that the data write unit 212 is used for receiving the data signal DT2 instead of the scan signal DT1 for data write operation.

As shown in FIG. 2, the data write unit 211 includes switches T21-T23 and a capacitor C21. In some embodiments, the control terminal of the switch T21 is configured to receive the control signal VC, one terminal of the switch T21 is coupled to the node N21, and the other terminal of the switch T21 is coupled to one terminal of the switch T22. One terminal of the switch T22 is coupled to the switch T21 at the node N22, the other terminal of the switch T22 is for receiving the voltage signal VSS at the node N24, and the control terminal of the switch T22 is coupled to the node N21. One terminal of the capacitor C21 is coupled to the node N21, and the other terminal of the capacitor C21 is configured to receive the data signal DT 1. The switch T23 has a control terminal for receiving the reset signal RST, a terminal of the switch T23 for receiving the voltage signal VDD, and the other terminal of the switch T23 coupled to the node N21.

As shown in fig. 2, the light emitting unit 221 includes a light emitting element L21, switches T24 and T25. In some embodiments, the control terminal of the switch T24 is configured to receive the scan signal S (N-1), one terminal of the switch T24 is coupled to the switch T21 at the node N22, and the other terminal of the switch T24 is coupled to the switch T25 at the node N23. One end and a control end of the switch T25 are coupled to the switch T24 at the node N23, and the other end of the switch T25 is used for receiving the voltage signal VDD. One end of the light emitting device L21 is coupled to the node N23, and the other end of the light emitting device L21 is configured to receive the voltage signal VDD. In some embodiments, the light emitting device L21 is configured to receive the current I21 and is configured to emit light according to a current level of the current I21. A current I21 flows through the switch T22 when the switch T24 is turned on. In some embodiments, switch T25 functions as a diode.

As shown in fig. 2, the light emitting unit 223 includes a light emitting element L23, switches T26 and T27. In some embodiments, the operation of the light emitting unit 223 is similar to that of the light emitting unit 221, and the light emitting element L23, the switch T26 and the switch T27 correspond to the light emitting element L21, the switch T24 and the switch T25, respectively. Therefore, the repeated parts are not described in detail. The difference between the light emitting unit 223 and the light emitting unit 221 includes that the light emitting unit 223 is used for receiving the scan signal S (n) instead of the scan signal S (n-1). The control terminal of the switch T26 is turned on according to the scan signal s (n) to receive the current I22, and the light emitting device L23 emits light according to the current level of the current I22. A current I22 flows through the switch T22 when the switch T26 is turned on.

As shown in fig. 2, the light emitting unit 222 includes a light emitting element L22, switches T24 'and T25'. The light emitting unit 224 includes a light emitting element L24, switches T26 'and T27'. The data write unit 212 includes switches T21 ' to T23 ' and a capacitor C21 '. The operation and configuration of the light emitting elements L22 and L24, the switches T21 ' to T27 ' and the capacitor C21 ' are similar to the operation and configuration of the light emitting elements L21 and L23, the switches T21 to T27 and the capacitor C21, respectively, and thus, the repeated description is omitted.

In various embodiments, light-emitting elements L21-L24 may be micro light-emitting diodes (mLEDs) or other different types of light-emitting elements. In various embodiments, the switches T21-T27, T21 '-T27' may be P-type metal oxide semiconductor field effect transistors (PMOS), N-type metal oxide semiconductor field effect transistors (NMOS), Thin Film Transistors (TFT), or other different types of switching elements.

Fig. 3 is a timing diagram illustrating operations of a display device according to an embodiment of the present disclosure. The timing diagram shown in FIG. 3 includes phases P31-P36 in order. In some embodiments, the timing diagram shown in FIG. 3 corresponds to the operations of the various signals shown in FIG. 2, such as the reset signal RST, the scan signals S (n) and S (n-1), the data signal DT1, and the control signal VC.

As shown in fig. 3, at the phase P31, the reset signal RST has the enabling voltage level VGH, such that the switch T23 is turned on. The switch T23 provides the voltage signal VDD having the voltage level DD to the node N21 at this time, so that the node voltage V21 of the node N21 has the voltage level DD.

In some embodiments, the voltage level DD is an enable voltage level, such that the switch T22 is turned on according to the node voltage V21 having the voltage level DD. In some embodiments, the capacitor C21 is used to store the charge on the node N21 to maintain the node voltage V21 after the switch T23 is turned off, so that the switch T22 is continuously turned on after the switch T23 is turned off (e.g., at stages P32 to P36).

In some embodiments, during the period P31, the node voltage V21 of the data writing unit 211 is reset by the voltage signal VDD, so that the data writing unit 211 can prepare to receive the data signal DT1, and thus the phase P31 is referred to as a reset phase.

In the phase P32, the control signal VC has the enable voltage level VGH, such that the switch T21 is turned on. The charge stored in the capacitor C21 during the phase P31 makes the node voltage V21 still have the enabling voltage level during the phase P32, so that the switch T22 is turned on during the phase P32. The switch T22 receives a voltage signal VSS having a voltage level SS at a node N24. Current flows from node N21 through switch T21 and switch T22 to node N24, causing the node voltage V21 to be pulled to the threshold voltage level V22 of switch T22_TH. The capacitor C21 receives the data signal DT1 having the voltage level VDT31 at the node N25. The voltage level difference between the two ends of the capacitor C21 is (VDT 31-V)_TH)。

In some embodiments, the voltage level of the node voltage V21 is adjusted to V21 by the current flowing from the node N21 to the node N24 through the switch T22 during the phase P32_THTo compensate for the threshold voltage level V of the switch T22 during the data writing phase (e.g., phases P33 and P35) and/or the lighting phase (e.g., phases P34 and P36)_TH. Phase P32 is therefore referred to as the compensation phase.

In the phase P33, the voltage level of the data signal DT1 is pulled to the voltage level VDT 32. The capacitor C21 is used for receiving the data signal DT1 having the voltage level VDT32 at the node N25. The voltage level difference between the two ends of the capacitor C21 is (VDT 31-V)_TH). Correspondingly, the voltage level of the node N21 is (VDT32- (VDT 31-V)_TH) Namely (V)_TH+ (VDT32-VDT 31)). In some embodiments, the voltage level VDT31 is a zero voltage level, and the node N21 has a voltage level (V21)_TH+VDT32)。

In some embodiments, the capacitor C21 writes the voltage level VDT32 of the data signal DT1 to the node N21 during the phase P33. Phase P33 is therefore referred to as the data write phase. In some embodiments, in the phase P33, the data writing unit 212 performs the data writing operation according to the data signal DT 2. In some other embodiments, at stage P33, other data writing units (not shown) in the peripheral region 210 perform data writing operations according to other data signals.

In the phase P34, the scan signal S (n-1) has the enabling voltage level VGH, such that the switch T24 is turned on. The light emitting device L21 is for receiving a voltage signal VDD with a voltage level DD at a node N26. The switch T22 is for receiving a voltage signal VSS having a voltage level SS at a node N24. At this time, a current I21 flows from the node N26 to the node N24 through the light emitting element L21, the switches T24 and T22 in sequence, so that the light emitting element L21 emits light according to the current level of the current I21. In some embodiments, the current level of the current I21 determines the luminous intensity of the light emitting element L21.

In phase P34, the capacitor C21 maintains the voltage level at the node N21 during phase P33, such that the node N21 has a voltage level (V) during phase P34_TH+VDT32)。

In some embodiments, the difference in the gate-to-source voltage levels of the switch T22, that is, the difference in the voltage levels of the node N21 and the node N24 is set as the voltage level difference VGS. The current level of the current I21 through the switch T22 is Kx (VGS-V) at the phase P34 as can be known from the formula in electronics_TH) 2. In phase P34, the voltage level (V) of the node N21 is adjusted_TH+ VDT32) and the voltage level SS of node N24 into a voltage level difference VGS, i.e.The current level of the current I21 is obtained as K x (VDT32-SS ^2, where K is a constant. Therefore, the current level of the current I21 and the threshold voltage level V_THRegardless, the voltage level VDT32 of the data signal DT1 is related to the voltage level SS of the voltage signal VSS.

In some previous approaches, when current passes through different paths in the display, different resistance values on different paths cause different voltage drops, and in addition, the threshold voltage level of the switch also causes voltage drops, so that the current flowing through the light emitting element is difficult to control, resulting in non-uniform brightness of the display.

In contrast to the above, in the embodiment of the present invention, the voltage levels VDT32 and SS are determined by the user. Thus, the current flowing through the light emitting device L21 can be adjusted by the user without being influenced by the current path or the device characteristics of the data writing unit 211, such as the threshold voltage level V of the switch T22_THThe effect is obtained.

In some embodiments, in the phase P34, the light emitting element L21 in the light emitting unit 221 emits light, and thus the phase P34 is referred to as a light emitting phase. In some embodiments, the light emitting unit 222 also performs the light emitting operation according to the scan signal S (n-1) in the phase P34. In some embodiments, at stage P34, other light-emitting cells (not shown) in the light-emitting cell row of the display area 220 including the light-emitting

cells

221 and 222 emit light according to the scan signal S (n-1) and other data signals.

In the phase P35, the voltage level of the data signal DT1 is pulled to the voltage level VDT 33. The capacitor C21 is used for receiving the data signal DT1 having the voltage level VDT33 at the node N25. Node N21 now has a voltage level (V)_TH+VDT33)。

In some embodiments, the capacitor C21 writes the voltage level VDT33 of the data signal DT1 to the node N21 during the phase P35. Phase P35 is therefore referred to as the data write phase. In some embodiments, in the phase P35, the data writing unit 212 performs the data writing operation according to the data signal DT 2. In some embodiments, at stage P35, other data writing units (not shown) in the peripheral region 210 perform data writing operations according to other data signals.

In the phase P36, the scan signal S (n-1) has the disable voltage level VGL, such that the switch T24 is closed. The scan signal s (n) has the enable voltage level VGH, such that the switch T26 is turned on. The light emitting device L23 is for receiving a voltage signal VDD with a voltage level DD at a node N27. The switch T22 is for receiving a voltage signal VSS having a voltage level SS at a node N24. At this time, a current I22 flows from the node N27 to the node N24 through the light emitting element L23, the switches T26 and T22 in sequence, so that the light emitting element L23 emits light according to the current level of the current I22. In some embodiments, the current level of the current I22 determines the luminous intensity of the light emitting element L23.

In phase P36, the capacitor C21 maintains the voltage level at the node N21 during phase P35, such that the node N21 has a voltage level (V) during phase P36_TH+ VDT 33). The voltage level (V) of the node N21_TH+ VDT33) into the above current equation, the current level of current I22 is (VDT33-SS) ^ 2.

In some embodiments, in the phase P36, the light emitting element L23 in the light emitting cell 223 emits light, and thus the phase P36 is referred to as a light emitting phase. In some embodiments, in the phase P36, the light emitting unit 224 also performs the light emitting operation according to the scan signal s (n). In some embodiments, in the phase P36, the light emitting cell rows (not shown) in the display area 220 including the

light emitting cells

223 and 224 emit light according to the scan signal s (n) and other data signals.

In some other embodiments, after the phase P36, more data writing operations and light emitting operations are alternated to write more voltage levels of the data signal DT1 to more light emitting cells (not shown) in the display area 220.

In some other embodiments, the light emitting unit 221 may not include the switch T25. In some embodiments, switch T25 is used to detect operation. More details regarding the detection operation are discussed below with respect to the embodiments of fig. 8 and 9.

Fig. 4 is a circuit diagram of a display device 400 according to an embodiment of the disclosure. Referring to fig. 4, a display device 400 is an embodiment of the display device 110. The display device 400 includes a peripheral area 410 and a display area 420. The peripheral region 410 adjoins the display region 420.

As shown in fig. 4, the display region 420 includes light emitting

units

421 and 422. The peripheral area 410 includes a data writing unit 411. The

light emitting units

421 and 422 and the data writing unit 411 shown in fig. 4 are similar to the

light emitting units

221 and 222 and the data writing unit 211 shown in fig. 2. The switches T41 to T47, the light emitting elements L41, L43 and the capacitor C41 in the display device 400 correspond to the switches T21 to T27, the light emitting elements L21, L23 and the capacitor C21 in the display device 200, and therefore the connection relationship between the elements is not repeated here.

In some embodiments, display device 400 differs from display device 200 in that peripheral region 410 further includes a switch T48. The control terminal of the switch T48 is coupled to the switches T41-T43 at the node N41, one terminal of the switch T48 is coupled to the switches T41 and T42 at the node N42, and the other terminal of the switch T48 is used for receiving the voltage signal VSS at the node N44.

In some embodiments, the display device 400 operates according to the timing diagram shown in FIG. 3. During a light emitting period, such as the period P34, the light emitting unit 421 receives the current I41 flowing through the switch T42 to perform a light emitting operation. At this time, the current I41 flows through the switch T42 and the switch T48.

In some embodiments, current I41 flows through switch T42 and switch T48 simultaneously, such that current I41 has a higher current level. Thus, the light emitting intensity of the light emitting element L41 is correspondingly increased.

Fig. 5 is a circuit diagram of a display device 500 according to an embodiment of the disclosure. Referring to fig. 5, a display device 500 is an embodiment of the display device 110. The display device 500 includes a peripheral area 510 and a display area 520. The peripheral region 510 adjoins the display region 520.

As shown in fig. 5, the display region 520 includes light emitting

units

522 and 523. The peripheral area 510 includes data write

units

511 and 512. Data writing unit 511 couples light emitting unit 523 to node N54. The data writing unit 512 is coupled to the light emitting unit 522 at the node N58. In some embodiments, the display region 520 includes a plurality of light emitting cell rows, each light emitting cell row includes a plurality of light emitting cells, wherein the light emitting cells 522 are included in the light emitting cell rows of the odd-numbered rows, and the light emitting cells 523 are included in the light emitting cell rows of the even-numbered rows, but the embodiment of the invention is not limited thereto.

In some embodiments, the operations of the

data writing units

511 and 512 and the

light emitting units

522 and 523 are similar to the operations of the

data writing units

211 and 212 and the

light emitting units

223 and 222, respectively, and thus the description is omitted here for brevity.

In some embodiments, the data write

units

511 and 512 are respectively used for receiving data signals DT1 and DT2 for data write operations. In some embodiments, the light emitting unit 522 is configured to emit light according to the data signal DT2 and the scan signal S (n-1). The light emitting unit 523 is used for emitting light according to the data signal DT1 and the scan signal s (n).

As shown in fig. 5, the data writing unit 511 includes switches T51 to T53 and a capacitor C51, the data writing unit 512 includes switches T51 ' to T53 ' and a capacitor C51 ', the light emitting unit 522 includes switches T54 ', T55 ' and a light emitting element L52, and the light emitting unit 523 includes switches T56 and T57 and a light emitting element L53. The switches T51 to T53, T56, T57, T51 'to T53', T54 ', T55', and the light emitting elements L52 and L53 correspond to the switches T21 to T23, T26, T27, T21 'to T23', T24 ', T25', and the light emitting elements L22 and L23 shown in fig. 2, respectively, and therefore, the repetition of the element connection relationship is not described here.

Fig. 6 is a timing diagram illustrating the operation of the display device 500 according to an embodiment of the disclosure. The timing diagram shown in FIG. 6 includes phases P61-P66 in order. In some embodiments, the timing diagram shown in FIG. 6 corresponds to the operations of the different signals shown in FIG. 5, such as the reset signal RST, the scan signals S (n) and S (n-1), the data signals DT1, DT2, and the control signal VC. In some embodiments, the operations of the phases P61-P66 are similar to the operations of the phases P31-P36 shown in FIG. 3, and therefore the repetition thereof is not repeated here.

As shown in fig. 6, at the phase P61, the reset signal RST has the enabling voltage level VGH, such that the switches T53 and T53' are turned on. The switches T53 and T53' provide the voltage signal VDD with the voltage level DD to the nodes N51 and N59, respectively, such that the nodes N51 and N59 have the voltage level DD.

In the phase P62, the control signal VC has the enabling voltage level VGH, such that the switches T51 and T51' are turned on. At this time, the nodes N51 and N59 are pulled to the threshold voltage level V of the switches T52 and T52_TH。

In the phase P63, the voltage level of the data signal DT2 is pulled to the voltage level VDT 52. Correspondingly, the voltage level at node N59 is pulled to the voltage level (V)_TH+ VDT 52). In some embodiments, voltage level VDT51 is a zero voltage level.

In the phase P64, the scan signal S (n-1) has the enabling voltage level VGH, such that the switch T54' is turned on. At this time, the current flows through the light emitting device L52, the switches T54 'and T52' in sequence, so that the light emitting device L52 depends on the voltage level (V) of the node N59_TH+ VDT52) emits light.

In the phase P64, the voltage level of the data signal DT1 is pulled to the voltage level VDT 53. Correspondingly, the voltage level at node N51 is pulled to the voltage level (V)_TH+VDT53)。

In the period P65, the scan signal s (n) has the enable voltage level VGH, such that the switch T56 is turned on. At this time, the current flows through the light emitting device L53, the switches T56 and T52 in sequence, so that the light emitting device L53 depends on the voltage level (V) of the node N51_TH+ VDT53) emits light. Meanwhile, the scan signal S (n-1) has an enable voltage level VGH, and the data signal DT2 has a voltage level VDT 52. The light emitting element L52 depends on the voltage level (V) of the node N59_TH+ VDT52) emits light. In other words, in the phase P65, the light emitting elements L52 and L53 emit light simultaneously according to the data signals DT2 and DT1, respectively.

In the phase P66, the scan signal s (n) has the enable voltage level VGH, and the data signal DT1 has the voltage level VDT 53. The light emitting element L53 depends on the voltage level (V) of the node N51_TH+ VDT53) emits light.

In some embodiments, through the operations described in the phases P61 to P66, the light emitting elements L52 and L53 can emit light simultaneously with a longer light emitting time, so that the light emitting intensity of the display device 500 is increased.

Fig. 7 is a schematic diagram of a display area 700 according to an embodiment of the disclosure. Referring to FIG. 7, a display area 700 is an embodiment of the display area 114 shown in FIG. 1.

As shown in fig. 7, the display area 700 includes

scan lines

701 and 703

light emitting units

710 and 730 and a repair unit 720. The

scan lines

701 and 703 are used for transmitting scan signals S (n-1) and S (n), respectively.

Light emitting cells

710 and 730 are embodiments of light emitting

cells

221 and 223 in FIG. 2, respectively. The light emitting

cells

710 and 730 are used for emitting light according to the current I7. The repair unit 720 is used to replace the abnormal light emitting unit 710 and/or the abnormal light emitting unit 730 to receive the current I7 for performing the light emitting operation when at least one of the

light emitting units

710 and 730 is abnormal, so that the display area 700 can emit light normally.

As shown in fig. 7, the light emitting unit 710 includes a switch T71 and a light emitting element L71. In some embodiments, the control terminal of the switch T71 is for receiving the scan signal S (n-1) on the scan line 701, one terminal of the switch T71 is coupled to the light emitting device L71, and the other terminal of the switch T71 is coupled to the repair unit 720 and the light emitting unit 730, and is for receiving the current I7. The light emitting device L71 emits light according to the current I7 when the switch T71 is turned on.

As shown in fig. 7, the light emitting unit 730 includes a switch T73 and a light emitting element L73. In some embodiments, the control terminal of the switch T73 is configured to receive the scan signal s (n) on the scan line 703, one terminal of the switch T73 is coupled to the light emitting device L73, and the other terminal of the switch T73 is coupled to the repair unit 720 and the light emitting unit 710 and configured to receive the current I7. The light emitting device L73 emits light according to the current I7 when the switch T73 is turned on.

As shown in fig. 7, the repair unit 720 includes a switch T72, a receiving space 729, a conductive wire M72, and solder joints P71 and P72. The control terminal of the switch T72 is coupled to the wire M72, one terminal of the switch T72 is coupled to the accommodating space 729, and the other terminal of the switch T73 is coupled to the

light emitting units

710 and 720. The conductive line M72 crosses the

scan lines

701 and 703. In some embodiments, the conductive line M72 is stacked on the

scan lines

701 and 703. The welding point P71 is located at the intersection of the conducting wire M72 and the scanning line 701. The pad P72 is located at the intersection of the lead M72 and the scan line 703.

In some embodiments, the conductive line M72 is used to couple the scan line 701 through the pad P71 when the light emitting cell 710 is abnormal and/or to couple the scan line 703 through the pad P72 when the light emitting cell 730 is abnormal. The accommodating space 729 is configured to accommodate the light emitting device L72 when at least one of the

light emitting units

710 and 730 is abnormal, such that the light emitting device L72 is coupled to the switch T72.

For example, when the switch T71 and/or the light emitting device L71 malfunctions to cause the light emitting unit 710 to malfunction, the conductive wire M72 is coupled to the scan line 701 at the welding point P71 by laser welding or other welding methods, and the light emitting device L72 is disposed in the accommodating space 729. At this time, one end of the light emitting device L72 is coupled to the switch T72, and the other end of the light emitting device L72 is used for receiving the voltage signal VDD. The control terminal of the switch T72 is for receiving the scan signal S (n-1), and one terminal of the switch T72 is for receiving the current I7, so that the light emitting device L72 performs a light emitting operation according to the scan signal S (n-1) and the current I7.

In other words, the arrangement of the switch T72 and the light emitting element L72 is the same as the arrangement of the switch T72 and the light emitting element L72. Thus, the repairing unit 720 replaces the function of the light emitting unit 710, thereby repairing the abnormality of the display area 700. Similarly, when the light emitting unit 730 is abnormal, the repair unit 720 is coupled to the scan line 703 through the pad P72 to replace the function of the light emitting unit 730.

In some embodiments, the display area 700 further includes a scan line 705 light emitting unit 740 and a repair unit 750. The scan line 705 is used for transmitting a scan signal S (n + 1). The light emitting unit 740 is used for emitting light according to the current I7. The repair unit 750 is configured to replace the abnormal light emitting unit 740 to receive the current I7 for a light emitting operation when the light emitting unit 740 is abnormal, so that the display area 700 can emit light normally.

As shown in fig. 7, the light emitting unit 740 includes a switch T74 and a light emitting element L74. In some embodiments, the control terminal of the switch T74 is configured to receive the scan signal S (n +1) on the scan line 705, one terminal of the switch T74 is coupled to the light emitting device L74, and the other terminal of the switch T74 is coupled to the repair unit 750 and configured to receive the current I7. The light emitting device L74 emits light according to the current I7 when the switch T74 is turned on.

As shown in fig. 7, the repair unit 750 includes a switch T75, a receiving space 759, a conducting wire M75, and a welding point P73. The control terminal of the switch T75 is coupled to the wire M75, one terminal of the switch T75 is coupled to the accommodating space 759, and the other terminal of the switch T75 is coupled to the light emitting unit 740. The conductive line M75 crosses the scanning line 705. In some embodiments, the conductive line M75 is stacked on the scan line 705. The pad P73 is located at the intersection of the lead M75 and the scan line 705.

In some embodiments, the conductive line M75 is used to couple the scan line 705 through the pad P73 when the light emitting cell 740 is abnormal. The accommodating space 759 is used for accommodating the light emitting device L75 when the light emitting unit 740 is abnormal, such that the light emitting device L75 is coupled to the switch T75.

In this way, when the light emitting unit 740 is abnormal, the repairing unit 750 replaces the light emitting unit 740 to perform the light emitting operation, so that the display area 700 can maintain the normal operation.

Fig. 8 is a circuit diagram of a display device 800 according to an embodiment of the disclosure. Referring to fig. 8, a display device 800 is an embodiment of the display device 110.

As shown in fig. 8, the display device 800 includes light emitting

units

821 and 822 and

data writing units

811 and 812. The light emitting units 821 to 824 and the

data writing units

811 and 812 shown in FIG. 8 are similar to the light emitting units 221 to 224 and the

data writing units

211 and 212 shown in FIG. 2. The switches T81 to T87, T81 'to T87' and the capacitors C81 and C81 'in the display device 800 correspond to the switches T21 to T27, T21' to T27 'and the capacitors C21 and C21' in the display device 200, respectively, and therefore the connection relationship between the elements is not repeated here.

In some embodiments, the display device 800 is different from the display device 200 in that the display device 800 further includes accommodating spaces S81 to S84. The accommodating spaces S81-S84 are respectively coupled to the light emitting units 821-824. The accommodating space S81 is coupled to the switch T84 at the node N83, and the accommodating space S83 is coupled to the switch T86 at the node N88. The accommodating spaces S81 and S83 are respectively used for accommodating the light emitting elements L81 and L83 after the inspection operation, so that the light emitting elements L81 and L83 are respectively coupled to the nodes N83 and N88. Similarly, in some embodiments, the accommodating spaces S82 and S84 are used for accommodating the light emitting elements after the detection operation. More details regarding the detection operation are discussed below with respect to the embodiment of FIG. 9.

Fig. 9 is a timing chart illustrating a detection operation performed by the display device according to an embodiment of the present invention. The timing diagram shown in FIG. 9 includes phases P91-P93 in order. In some embodiments, the timing diagram shown in fig. 9 corresponds to the operations of the different signals shown in fig. 8, such as the reset signal RST, the scan signals S (n) and S (n-1), and the data signal DT 1.

As shown in fig. 9, at the phase P91, the reset signal RST has the enabling voltage level VGH, such that the switch T83 is turned on. The switch T83 provides the voltage signal VSS having the voltage level SS1 to the node N81 at this time, so that the node N81 has the voltage level SS.

In some embodiments, the voltage level SS is a disable voltage level, such that the capacitor C81 discharges from the node N81 through the switch T83. In some embodiments, when the switch T83 is abnormal, the capacitor C81 cannot discharge through the switch T83, so that the voltage level at the node N81 is abnormal, and thus the current through the switch T82 is abnormal. In some embodiments, it may be detected whether switch T83 is abnormal by measuring the current through switch T82.

In the phase P92, the scan signal S (n-1) has the enabling voltage level VGH, such that the switch T84 is turned on. The capacitor C81 writes the data signal DT1 having the voltage level VDT91 into the node N81 to turn on the switch T82. The switch T85 is for receiving a voltage signal VSS having a voltage level SS at a node N86. The switch T82 is for receiving a voltage signal VDD having a voltage level DD at a node N84. At this time, current flows from the node N84 to the node N86 through the switches T82, T84, and T85 in sequence.

In some embodiments, an anomaly in at least one of the switches T85, T84, and T82 would cause an anomaly in the current through the switch T85. In some embodiments, it may be detected whether at least one of the switches T85, T84, and T82 is abnormal by measuring the current through the switch T85. For example, when the switch T85 fails to conduct due to an abnormality, the current level of the current passing through the switch T85 is zero.

In the period P93, the scan signal s (n) has the enable voltage level VGH, such that the switch T86 is turned on. The capacitor C81 writes the data signal DT1 having the voltage level VDT92 into the node N81 to turn on the switch T82. The switch T87 is for receiving a voltage signal VSS having a voltage level SS at a node N87. The switch T82 is for receiving a voltage signal VDD having a voltage level DD at a node N84. At this time, current flows from the node N84 to the node N87 through the switches T82, T86, and T87 in sequence.

In some embodiments, an anomaly in at least one of the switches T87, T86, and T82 would cause an anomaly in the current through the switch T87. In some embodiments, it may be detected whether at least one of the switches T87, T86, and T82 is abnormal by measuring the current through the switch T87.

Whether the

light emitting units

821 and 823 are abnormal is sequentially detected by the operations described in the stages P91 to P93. In some other embodiments, after the period P93, other scan signals (not shown) are pulled to the enabling voltage level VGH to sequentially detect whether other light-emitting units (not shown) in the display device 800 are abnormal.

In some previous approaches, the light emitting elements are already coupled to the display device when the detection signal is provided to the display device to test whether the display device is abnormal. In this case, the manufacturing cost of the display device includes the manufacturing cost of the light emitting element.

In contrast to the above, the embodiment of the invention provides a display device 800 that can perform detection before the light emitting elements L81 and L83 are coupled to the

light emitting units

821 and 823, as shown in fig. 8. The display device 800 is a display device before the light emitting elements are coupled, so the manufacturing cost of the display device 800 is low.

In some embodiments, after performing the detecting operation described in fig. 9, L81 and L83 may be coupled to the accommodating spaces S81 and S83, i.e., the light emitting elements L81 and L83 may be coupled to the display apparatus 800, so that the display apparatus 800 can perform the light emitting operation described in fig. 3.

In some embodiments, the detection operations of the

light emitting units

822 and 824 are similar to those of the

light emitting units

821 and 823, and thus the description thereof is not repeated.

The various detection modes described above are illustrative and other detection modes and signal manipulation modes are within the scope of the present disclosure.

In summary, in the embodiments of the inventionWhen the light emitting element L21 emits light, the threshold voltage level V of the switch T22_THIs compensated so that the critical voltage level V_THThe magnitude of (d) does not affect the light emission intensity of the light emitting element L21. In addition, the data signal DT1 and the voltage signal VSS determined by the user do not influence the light emission intensity of the light emitting element L21 by the resistance value of the current path. In addition, the display device 800 may sequentially inspect 821 and 823 before coupling the light emitting elements L81 and L82, thereby reducing manufacturing costs.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A display device comprises a display area and at least one peripheral area adjacent to the display area

The at least one peripheral region includes a first data writing unit for writing a first data signal into a first node, the first data writing unit including:

a first switch, a first terminal of which is coupled to the first node;

a second switch, a first terminal of the second switch being coupled to a second terminal of the first switch, a control terminal of the second switch being coupled to the first node;

a third switch, a first end of the third switch being coupled to a second end of the second switch, a second end of the third switch being coupled to the second end of the first switch, and a control end of the third switch being coupled to the first node; and

a capacitor, a first end of the capacitor is coupled to the first node; and

the display area comprises a first light-emitting unit which is used for emitting light according to the first data signal.

2. The display device of claim 1, wherein the first light emitting unit comprises:

a fourth switch, a first end of the fourth switch is used for receiving a current flowing through the second switch; and

a fifth switch, a first end of the fifth switch and a control end of the fifth switch are coupled to a second end of the fourth switch.

3. The display device of claim 2, wherein the first light emitting unit further comprises:

and the accommodating space is coupled with the second end of the fourth switch and is used for accommodating a light-emitting element after the current flows through the fourth switch and the fifth switch, so that the light-emitting element is coupled with the first light-emitting unit.

4. The display device of claim 1, wherein the display area is disposed between two peripheral areas of the at least one peripheral area.

5. The display device according to claim 1, wherein the first switch and the second switch are turned on before the first data signal is written into the first node to pull a voltage level of the first node to a threshold voltage level of the second switch.

6. The display device of claim 1, wherein the display area further comprises:

and the second light-emitting unit is coupled with the first light-emitting unit and the first end of the second switch and is used for emitting light according to the first data signal after the first light-emitting unit emits light.

7. The display device of claim 1, wherein

The display area further includes:

the second light-emitting unit is used for emitting light according to a second data signal when the first light-emitting unit emits light; and

the at least one peripheral region further comprises:

and a second data writing unit coupled to the second light emitting unit and the second end of the second switch for receiving the second data signal.

8. The display device of claim 7, wherein the display area further comprises a first row of light-emitting cells and a second row of light-emitting cells arranged along a first direction,

the first light-emitting unit is included in the first row of light-emitting units, the second light-emitting unit is included in the second row of light-emitting units, and

the at least one peripheral region and the display region are arranged along the first direction.

9. The display device of claim 1, wherein

The display area further includes:

a first scan line coupled to the first light emitting unit;

a second light emitting unit coupled to the first light emitting unit;

a second scan line coupled to the second light emitting unit;

a third light-emitting unit coupled to the first light-emitting unit and the second light-emitting unit; and

a wire coupled to the third light emitting unit and stacked on the first scan line and the second scan line.

10. The display device of claim 9, wherein

The third light emitting unit includes:

a fourth switch, a first end of which is coupled to the first light-emitting unit and the second light-emitting unit, and a control end of which is coupled to the wire; and

an accommodating space coupled to a second end of the fourth switch and used for accommodating a light emitting element when one of the first light emitting unit and the second light emitting unit is abnormal, so that the light emitting element is coupled to the display area, and

the wire is used for coupling the first scanning line or the second scanning line corresponding to one of the first light-emitting unit and the second light-emitting unit which is abnormal when the other one of the first light-emitting unit and the second light-emitting unit is abnormal.