CN113378505B - Wiring layout adjustment method and device, electronic equipment and storage medium - Google Patents
Wiring layout adjustment method and device, electronic equipment and storage medium Download PDFInfo
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- CN113378505B CN113378505B CN202010161449.1A CN202010161449A CN113378505B CN 113378505 B CN113378505 B CN 113378505B CN 202010161449 A CN202010161449 A CN 202010161449A CN 113378505 B CN113378505 B CN 113378505B
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Abstract
The invention discloses a wiring layout adjustment method, a wiring layout adjustment device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a line sequence network of a printed circuit board, and determining the tail end of a signal to be modified in the line sequence network to obtain the coordinates of the termination position of the wiring to be modified; the signal is transmitted through a wire, and the position of the tail end of the signal corresponds to the position of the termination of the wire; determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the wiring to be modified; and determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin. By adopting the technical scheme, the pin signal can be more efficiently and accurately adjusted when the printed circuit board is difficult to be outgoing.
Description
Technical Field
The present invention relates to electronic industry technologies, and in particular, to a method and apparatus for adjusting a routing layout, an electronic device, and a storage medium.
Background
PCB (Printed circuit boards, printed circuit board) is one of the important components of the electronics industry, and PCB is used for almost every kind of electronic equipment. Small to electronic watches, calculators, large to computers, communications electronics, military weapon systems, and the like.
In complex PCB designs, it is often found that partial chip out-of-order leads to difficult wire routing during the place or route stage. This is solved in the following way: punching a through hole to forcibly exchange layers and wire out; adjusting the layout of the chip or the interface end, and straightening out wires; checking the chip data and adjusting the signal definition. However, the above-mentioned scheme is too much in human factor, is prone to error and is inefficient in adjusting speed.
Therefore, a method for rapidly adjusting the definition of the signal is needed, so that the pin signal can be adjusted more efficiently and accurately when the outgoing line is difficult.
Disclosure of Invention
The invention provides a wiring layout adjustment method, a wiring layout adjustment device, electronic equipment and a storage medium, so as to realize more efficient and accurate adjustment of pin signals.
In a first aspect, an embodiment of the present invention provides a routing layout adjustment method, including:
acquiring a line sequence network of a printed circuit board, and determining the tail end of a signal to be modified in the line sequence network to obtain the coordinates of the termination position of the wiring to be modified; the signal is transmitted through a wire, and the position of the tail end of the signal corresponds to the position of the termination of the wire;
determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the wiring to be modified;
and determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
In a second aspect, an embodiment of the present invention further provides a routing layout adjustment apparatus, including:
the wiring termination position coordinate determining module is used for obtaining a line sequence network of the printed circuit board, determining the tail end of a signal to be modified in the line sequence network and obtaining wiring termination position coordinates to be modified; the signal is transmitted through a wire, and the position of the tail end of the signal corresponds to the position of the termination of the wire;
the to-be-selected pin determining module is used for determining at least one to-be-selected pin on the printed circuit board according to the to-be-modified wiring termination position coordinates;
and the signal conduction pin determining module is used for determining a target pin meeting preset conditions from the at least one pin to be selected and determining the target pin as a signal conduction pin.
In a third aspect, an embodiment of the present invention further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the processor implements the routing layout adjustment method according to any one of the embodiments of the present invention when executing the program.
In a fourth aspect, an embodiment of the present invention further provides a storage medium having stored thereon a computer program, which when executed by a processor implements the routing layout adjustment method according to any of the embodiments of the present invention.
According to the embodiment of the invention, the functional tail end wiring of the to-be-modified line sequence network is determined by acquiring the to-be-modified line sequence network of the printed circuit board, so that the wiring termination coordinates are obtained; determining at least one pin to be selected on a printed circuit board according to the wiring termination coordinates of the wire sequence network to be modified; and determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin. The technical scheme of the invention can enable the pin signal to be more efficiently and accurately adjusted when the outgoing line is difficult.
Drawings
Fig. 1 is a flowchart of a routing layout adjustment method according to a first embodiment of the present invention;
fig. 2 is a flow chart of a routing layout adjustment method provided in the second embodiment of the present invention;
FIG. 3 is a schematic diagram of a tool interface provided in a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a routing layout adjustment device according to a third embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example 1
Fig. 1 is a schematic flow chart of a routing layout adjustment method provided in an embodiment of the present invention, where the embodiment is applicable to a situation of difficult wire outgoing in a PCB board design process, and the method may be performed by a routing layout adjustment device, and the device may be implemented in a software and/or hardware manner and may be integrated in an electronic device, and specifically includes the following steps:
step 110, acquiring a line sequence network of a printed circuit board, and determining the tail end of a signal to be modified in the line sequence network to obtain the termination position coordinate of the wiring to be modified; the signal is transmitted through the wiring, and the tail end position of the signal corresponds to the termination position of the wiring.
In this embodiment, the printed circuit board, also called a printed circuit board, is a platform for electrical connection of electronic components. The design of the printed circuit board is mainly layout design, and in the layout design, a line sequence network meeting corresponding functions needs to be designed, and the line sequence network is usually composed of a plurality of groups of wiring. Further, the signals are generally transmitted through wires, the functions of the signals are correspondingly arranged with the wires, the connection modes of the wires are different, and the corresponding functions of the signals are different. In the design phase, it is often necessary to modify the signal, corresponding to the modified connection pins, which are actually traces. The tail end of the signal to be modified refers to the position where the signal function is finished, and the position of the tail end of the signal corresponds to the termination position of the corresponding wiring. However, the coordinates of the termination position of the trace are usually positions where the trace cannot be wired out, or positions where forced wired out may cause confusion of the trace. In this embodiment, after the end of the signal to be modified is obtained, the position where the line sequence function ends is determined in the printed circuit board, the coordinates of the line termination position where the line cannot be outgoing are determined, the pin to which the line is originally connected is obtained, and the pin is marked as G.
And 120, determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the routing to be modified.
In this embodiment, the pin to be selected is a pin to which a line with the coordinates of the termination position of the routing can be reconnected. And determining a pin group according to the specific position of the wiring termination position coordinate and the pin G and combining the information of the preset pin group, wherein the pins in the pin group can be connected with signals identical to the pin G. Traversing the pins in the pin group, and taking the idle pins in the pin group as pins to be selected.
In this technical scheme, optionally, determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the routing to be modified includes:
judging whether an idle pin exists in a target area on the printed circuit board according to the coordinates of the wiring termination position to be modified;
if yes, determining the idle pins existing in the target area as pins to be selected.
In this embodiment, the target area is an area with a distance from the coordinates of the trace termination position meeting a preset condition, and the target area includes pins. Specifically, the method for determining the target area may be to determine the pin in the range by taking the coordinates of the termination position of the trace as the center of a circle and taking the preset distance as the radius. The idle pin is a pin which is not connected with the wiring, and further, the idle pin can have a signal conducting function and can also have a plurality of signal conducting functions.
In this technical scheme, optionally, determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the routing to be modified includes:
acquiring idle pins existing in a non-target area on the printed circuit board and coordinates of the idle pins,
determining the distance between the idle pin coordinates and the wiring termination position coordinates according to the wiring termination position coordinates to be modified and the idle pin coordinates;
and determining a pin to be selected from the idle pins according to the distance.
In the present embodiment, the coordinates of the trace termination position are set to (x, y), and the coordinates of the idle pins in the non-target area are set to (z i ,w i ) Wherein i is used for distinguishing different idle pins, and the coordinates of the termination position and the coordinates of the idle pins are determined according to the wiringCalculating the distance d between the two i It can be seen that
Will d i Sorting d in order of small to large i The selection of the pin to be selected meeting the preset condition is that the pin to be selected is in a non-target area d i The first three in the ordering.
And 130, determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
In this embodiment, the target pin is a pin of the trace which is determined from the pins to be selected and is finally used for connecting with the coordinates of the termination position of the trace. In this embodiment, the preset condition may be a preset distance condition, where the preset distance condition may be that the distance between the routing termination position coordinate and the idle pin coordinate is the smallest, that is, the value of d between the idle pin coordinate and the routing termination position coordinate is the smallest, and then the corresponding idle pin is determined to be the target pin. Of course, the preset condition may be signal strength, signal function, etc., which are not listed here.
According to the technical scheme, the wiring termination position coordinates of a to-be-modified line sequence network are determined by acquiring the to-be-modified line sequence network of a printed circuit board; determining at least one pin to be selected on a printed circuit board according to the wiring termination position coordinates of the to-be-modified line sequence network; and determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin. The pin signal can be adjusted more efficiently and accurately when the printed circuit board is difficult to be outgoing.
Example two
Fig. 2 is a schematic flow chart of a routing layout adjustment method provided in the second embodiment of the present invention, and the present embodiment is further optimized based on the foregoing embodiment, and is specifically: how to further determine the target pin specifically comprises the following steps:
step 210, obtaining a line sequence network of the printed circuit board, and determining the tail end of a signal to be modified in the line sequence network to obtain the termination position coordinate of the wiring to be modified.
The signal is transmitted through the wiring, and the tail end position of the signal corresponds to the termination position of the wiring.
And 220, determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the routing to be modified.
And 230, determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
In this embodiment, the preset condition is preferably a preset distance condition.
Step 240, if the target pin determined by at least two signals is a candidate pin, determining whether the at least two signals have a preset priority difference.
In this embodiment, the signal may be a data signal or a pulse signal, where the data signal may be a plurality of different data signals. The signals are conducted through the traces of the trace termination location coordinates, with different signals being conducted by different traces. The priorities of the different signals can be preset, and the signals with high priorities are conducted preferentially. Specifically, the manner of determining the priority may be preset in a tool interface, which may be referred to as a schematic diagram of a tool interface shown in fig. 3, where the interface includes: signal priority setting, signal information and output information of a line sequence network, and the like.
If yes, go to step 250; if not, go to step 260.
And 250, determining the target pin as the target pin of the high-priority signal in the at least two signals according to the preset priority difference.
When the different signals have the preset priority difference, the target pin of the high-priority signal is processed preferentially. For example, if the signal a is a data signal and the signal B is a pulse signal, and the priority of the data signal is set to be higher than that of the pulse signal, if the target pin determined by the signal a and the signal B is the same pin C to be selected, the pin C to be selected is the target pin of the signal a because the signal a is higher than the signal B.
And 260, determining the target pin as the target pin of the signal which best meets the preset distance condition in the at least two signals.
Specifically, if the a signal is a data signal, the B signal is also a data signal, and the priority between the a signal and the B signal is the same. If the target pins determined by the signal A and the signal B are the same pin D to be selected, signals more conforming to the preset distance condition between the signal A and the signal B are compared, and the pin D to be selected is used as the target pin of the signal. Wherein f is the distance between the wiring termination position coordinate of the signal A and the pin D to be selected, and g is the distance between the wiring termination position coordinate of the signal B and the pin D to be selected. Specifically, when the preset distance condition is that the distance is minimum, if f is smaller than g, the pin D to be selected is used as the target pin of the A signal.
And 270, outputting the coordinates of the wiring termination position, the target pin and the signals of the target pin.
In this embodiment, after determining the target pin, the routing termination position coordinate, and the signal of the target pin may be output in a table form, and further, information of the pin to which the routing of the routing termination position coordinate is originally connected may also be output, so as to modify the schematic diagram.
In the technical solution of this embodiment, if the target pin determined by at least two signals is a pin to be selected, it is determined whether a preset priority difference exists between the at least two signals. If yes, determining the target pin as the target pin of the high-priority signal in the at least two signals according to the preset priority difference. By processing the signals with high priority, the layout of the line sequence network is more reasonable on the basis of solving the problem of difficult line outgoing of the PCB.
Example III
Fig. 4 is a schematic structural diagram of a routing layout adjustment device according to a third embodiment of the present invention. The wiring layout adjustment device provided by the embodiment of the invention can execute the wiring layout adjustment method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. As shown in fig. 4, the apparatus includes:
the routing termination position coordinate determining module 401 is configured to obtain a wire-sequence network of a printed circuit board, determine a signal end to be modified in the wire-sequence network, and obtain routing termination position coordinates to be modified; the signal is transmitted through a wire, and the position of the tail end of the signal corresponds to the position of the termination of the wire;
the to-be-selected pin determining module 402 is configured to determine at least one to-be-selected pin on the printed circuit board according to the to-be-modified routing termination position coordinate;
and the signal conducting pin determining module 403 is configured to determine a target pin meeting a preset condition from the at least one to-be-selected pin, and determine the target pin as a signal conducting pin.
The apparatus further comprises:
a preset priority difference determining module 404, configured to determine whether a preset priority difference exists between at least two signals if the target pin determined by the at least two signals is a pin to be selected;
and a target pin allocation module 405, configured to allocate, if yes, the target pin as a target pin of a high priority signal in the at least two signals according to the preset priority difference.
The pin determination module 402 for standby is specifically configured to:
judging whether an idle pin exists in a target area on the printed circuit board according to the coordinates of the wiring termination position to be modified;
if yes, determining the idle pins existing in the target area as pins to be selected.
The pin determination module 402 is specifically configured to obtain an idle pin existing in a non-target area on the printed circuit board and the coordinates of the idle pin,
determining the distance between the idle pin coordinates and the wiring termination position coordinates according to the wiring termination position coordinates to be modified and the idle pin coordinates;
and determining a pin to be selected from the idle pins according to the distance.
The device comprises:
and an output module 406, configured to output the routing termination position coordinates, the target pin and the signals of the target pin.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.
Example IV
Fig. 5 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention, and fig. 5 shows a schematic structural diagram of an exemplary device suitable for implementing the embodiment of the present invention. The electronic device 12 shown in fig. 5 is merely an example and should not be construed as limiting the functionality and scope of use of embodiments of the present invention.
As shown in fig. 5, the electronic device 12 is in the form of a general purpose computing device. Components of the electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, a bus 18 that connects the various system components, including the system memory 28 and the processing units 16.
The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 30 and/or cache memory 32. The electronic device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 5, commonly referred to as a "hard disk drive"). Although not shown in fig. 5, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In such cases, each drive may be coupled to bus 18 through one or more data medium interfaces. The system memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored in, for example, system memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 42 generally perform the functions and/or methods of the embodiments described herein.
The electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), one or more devices that enable a user to interact with the electronic device 12, and/or any devices (e.g., network card, modem, etc.) that enable the electronic device 12 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 22. Also, the electronic device 12 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through a network adapter 20. As shown in fig. 5, the network adapter 20 communicates with other modules of the electronic device 12 over the bus 18. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 12, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
The processing unit 16 executes various functional applications and data processing by running a program stored in the system memory 28, for example, to implement a routing layout adjustment method provided in an embodiment of the present invention, including:
acquiring a line sequence network of a printed circuit board, and determining the tail end of a signal to be modified in the line sequence network to obtain the coordinates of the termination position of the wiring to be modified; the signal is transmitted through a wire, and the position of the tail end of the signal corresponds to the position of the termination of the wire;
determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the wiring to be modified;
and determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
Example five
A fifth embodiment of the present invention further provides a storage medium having stored thereon a computer program (or called computer executable instructions) that when executed by a processor implements a routing layout adjustment method according to any of the foregoing embodiments, including:
acquiring a line sequence network of a printed circuit board, and determining the tail end of a signal to be modified in the line sequence network to obtain the coordinates of the termination position of the wiring to be modified; the signal is transmitted through a wire, and the position of the tail end of the signal corresponds to the position of the termination of the wire;
determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the wiring to be modified;
and determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin.
The storage media of embodiments of the present invention may take the form of any combination of one or more computer-readable media. The readable medium may be a computer readable signal medium or a computer readable storage medium. Take the example of a computer storage medium. The storage medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for embodiments of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (9)
1. The wiring layout adjustment method is characterized by comprising the following steps:
acquiring a line sequence network of a printed circuit board, and determining the tail end of a signal to be modified in the line sequence network to obtain the coordinates of the termination position of the wiring to be modified; the signal is transmitted through a wire, and the position of the tail end of the signal corresponds to the position of the termination of the wire;
determining at least one pin to be selected on the printed circuit board according to the coordinates of the termination position of the wiring to be modified;
determining a target pin meeting preset conditions from the at least one pin to be selected, and determining the target pin as a signal conduction pin;
according to the coordinates of the termination position of the routing to be modified, determining at least one pin to be selected on the printed circuit board comprises the following steps:
acquiring an idle pin existing in a non-target area on the printed circuit board and the coordinates of the idle pin;
determining the distance between the idle pin coordinates and the wiring termination position coordinates according to the wiring termination position coordinates to be modified and the idle pin coordinates;
and determining a pin to be selected from the idle pins according to the distance.
2. The method of claim 1, wherein determining at least one pin to be selected on a printed circuit board based on the trace termination location coordinates to be modified comprises:
judging whether an idle pin exists in a target area on the printed circuit board according to the coordinates of the wiring termination position to be modified;
if yes, determining the idle pins existing in the target area as pins to be selected.
3. The method according to any one of claims 1-2, wherein after determining a target pin meeting a preset condition from the at least one candidate pin, the method further comprises:
if the target pins determined by at least two signals are the same pin to be selected, judging whether the at least two signals have preset priority or not;
if yes, determining the target pin as the target pin of the high-priority signal in the at least two signals according to the preset priority.
4. The method of claim 1, further comprising, after determining the target pin as a signaling pin:
outputting the coordinates of the wiring termination position, the target pin and the signals of the target pin.
5. The utility model provides a wiring overall arrangement adjusting device which characterized in that includes:
the wiring termination position coordinate determining module is used for obtaining a line sequence network of the printed circuit board, determining the tail end of a signal to be modified in the line sequence network and obtaining wiring termination position coordinates to be modified; the signal is transmitted through a wire, and the position of the tail end of the signal corresponds to the position of the termination of the wire;
the to-be-selected pin determining module is used for determining at least one to-be-selected pin on the printed circuit board according to the to-be-modified wiring termination position coordinates;
the signal conduction pin determining module is used for determining a target pin meeting preset conditions from the at least one pin to be selected and determining the target pin as a signal conduction pin;
the pin determination module to be selected is specifically configured to: acquiring idle pins existing in a non-target area on the printed circuit board and coordinates of the idle pins,
determining the distance between the idle pin coordinates and the wiring termination position coordinates according to the wiring termination position coordinates to be modified and the idle pin coordinates;
and determining a pin to be selected from the idle pins according to the distance.
6. The apparatus of claim 5, wherein the pin determination module to be selected is specifically configured to:
judging whether an idle pin exists in a target area on the printed circuit board according to the coordinates of the wiring termination position to be modified;
if yes, determining the idle pins existing in the target area as pins to be selected.
7. The apparatus according to claim 5 or 6, characterized in that the apparatus further comprises:
the preset priority determining module is used for judging whether the preset priorities exist in the at least two signals if the target pins determined by the at least two signals are the same to-be-selected pin;
and the target pin allocation module is used for allocating the target pin as the target pin of the high-priority signal in the at least two signals according to the preset priority if the target pin is the target pin.
8. An electronic device comprising a memory, a processor and a program stored on the memory and executable on the processor, wherein the processor implements the routing layout adjustment method of any of claims 1-4 when the program is executed by the processor.
9. A storage medium having a program stored thereon, which when executed by a processor implements the wiring layout adjustment method as claimed in any one of claims 1-4.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107592728A (en) * | 2017-09-26 | 2018-01-16 | 郑州云海信息技术有限公司 | A kind of method and structure of PCB placement-and-routings |
| CN110378062A (en) * | 2019-07-26 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of the pin wiring inspection method and relevant apparatus of differential lines |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0836596A (en) * | 1994-07-26 | 1996-02-06 | Oki Electric Ind Co Ltd | Wiring board wiring method and device therefor |
| JP2003279624A (en) * | 2002-03-26 | 2003-10-02 | Fujitsu Ltd | Device for testing electronic component |
| JP4018994B2 (en) * | 2003-02-17 | 2007-12-05 | 株式会社Ｎｅｃ情報システムズ | Substrate layer number estimation system, method and program |
| CN103153001B (en) * | 2013-02-05 | 2016-11-16 | 浙江宇视科技有限公司 | A kind of pcb board processing method |
| US10289796B2 (en) * | 2016-12-06 | 2019-05-14 | Synopsys, Inc. | Automated place-and-route method for HBM-based IC devices |
| CN106648007B (en) * | 2016-12-09 | 2020-06-19 | 浙江宇视科技有限公司 | Universal slot position implementation method and device and communication equipment |
| CN110567468A (en) * | 2018-06-06 | 2019-12-13 | 百度在线网络技术（北京）有限公司 | Road track acquisition method, equipment and storage medium |
-
2020
- 2020-03-10 CN CN202010161449.1A patent/CN113378505B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107592728A (en) * | 2017-09-26 | 2018-01-16 | 郑州云海信息技术有限公司 | A kind of method and structure of PCB placement-and-routings |
| CN110378062A (en) * | 2019-07-26 | 2019-10-25 | 苏州浪潮智能科技有限公司 | A kind of the pin wiring inspection method and relevant apparatus of differential lines |
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