CN113378504B - Logic encryption-based integrated circuit low-controllability node protection method - Google Patents
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Abstract
The invention provides a logic encryption-based integrated circuit low-controllability node protection method, and belongs to the field of hardware safety. Aiming at the screened low-controllability nodes, n-level maximum correlation nodes of the original low-controllability nodes are firstly searched, on the premise of the found n-level maximum correlation nodes, whether the n-level maximum correlation nodes are located in a critical path of the circuit needs to be judged, the n-level maximum correlation nodes on a non-critical path are screened out, and a key gate is inserted for encryption. And for the n-level maximum associated nodes on the critical path, searching the n-level minimum associated nodes of the original low controllable nodes corresponding to the n-level maximum associated nodes, and performing logic encryption on the n-level minimum associated nodes. The invention can not only prevent the low controllability of the key path node from causing the low controllability of the non-key path node in the lower-level logic unit, but also reduce the hardware overhead of the circuit, avoid the redundancy of the circuit and improve the encryption efficiency.
Description
Technical Field
The invention belongs to the field of hardware security, and relates to a logic encryption-based integrated circuit low-controllability node protection method.
Background
All stages of the supply chain of modern integrated circuits are possibly threatened by security, and all links of design, manufacture, test, deployment and application have security vulnerabilities aiming at hardware, and an attacker can insert hardware trojans into the vulnerabilities to cause irreversible damage to the integrated circuits.
In the stage of functional design and physical design of an integrated circuit, a built-in locking mechanism is implanted in the original design of the integrated circuit, so that the circuit can execute correct operation only under the condition of inputting a correct key to obtain correct output, an attacker can be effectively prevented from implanting a hardware trojan in the circuit or performing reverse engineering on the circuit, but the logic encryption technology can cause larger circuit redundancy and hardware overhead and has larger influence on the performance of the circuit.
When a hardware trojan which utilizes the destruction function of the low controllable node is defended, the low controllable node of the circuit needs to be screened out, and a proper encryption position is selected to be inserted into a key gate according to the low controllable node, so that the circuit structure is mixed up, and the low controllable node in the circuit is hidden. The encryption method mainly comprises two types, namely avoiding the key path node or directly encrypting the key path node. The low controllability of the non-critical path nodes in the lower logic units is caused by the low controllability of the critical path nodes caused by the condition that the critical path nodes are encrypted; the key path nodes are directly encrypted, and because the insertion of the hardware trojans in the key paths does not conform to the concealment of the hardware trojans, circuit redundancy is caused and the frequency of the circuit is influenced.
Disclosure of Invention
In order to overcome the technical problem, the invention provides a logic encryption-based integrated circuit low-controllability node protection method, which specifically adopts the following technical scheme:
a logic encryption-based integrated circuit low-controllability node protection method comprises the following steps:
step 1: sequentially numbering output nodes (except output ports of the integrated circuit) of all logic units in the integrated circuit, screening original low-controllability nodes in the integrated circuit to form an original low-controllability node set, and recording the numbers of the original low-controllability nodes;
step 2: finding a final associated node corresponding to each original low-controllability node in the set:
searching n-level maximum associated nodes of each original low-controllability node, judging the positions of the n-level maximum associated nodes, and if the n-level maximum associated nodes are positioned on a non-critical path of a circuit, taking the n-level maximum associated nodes as final associated nodes of the original low-controllability nodes; if the node is located on the key path of the circuit, continuously searching n-level minimum associated nodes of the original low-controllability node, and taking the n-level minimum associated nodes as final associated nodes of the original low-controllability node;
traversing each original low-controllability node in the set, so that each original low-controllability node corresponds to a final associated node;
and step 3: and inserting a key gate at a final associated node corresponding to all the original low-controllability nodes to logically encrypt the integrated circuit.
Further, the original low-controllability node is obtained by screening with the turnover probability as a measurement standard;
the turning probability obtaining mode is as follows: the method comprises the steps of performing function simulation on an input random vector of an integrated circuit to obtain a waveform diagram of each node in the circuit under the input random vector, converting the waveform diagram into waveform data of each node, obtaining the turning probability of each node in the circuit by using the waveform data, and taking the node with the turning probability lower than a preset threshold value as an original low-controllability node.
Further, the method for searching the n-level maximum associated nodes comprises the following steps:
recording the original low controllability node as S0;
searching an input port S1 with the lowest turnover probability in the input ends of the logic units with the node S0 as the output, and taking the node S1 as a primary maximum association node of the node S0;
judging whether the turnover probability of the node S1 is greater than a preset low-controllability node threshold, if so, searching an input port S2 with the lowest turnover probability in the input end of the logic unit with the node S1 as the output, and taking the node S2 as a secondary maximum associated node of the original low-controllability node S0;
and repeating the process until the node Sn is found and obtained, the turnover probability of the node Sn is greater than the preset low-controllability node threshold value, the turnover probability of the node Sn-1 is less than or equal to the preset low-controllability node threshold value, and the node Sn is used as the n-level maximum associated node of the original low-controllability node.
Further, after n-level maximum associated nodes corresponding to all the original low-controllability nodes are obtained, the duplicate nodes are deleted.
Further, the method for searching the n-level minimum associated nodes comprises the following steps:
recording the original low controllability node as S0;
searching an input port S1 'with the highest turnover probability in the input ends of the logic units with the node S0 as an output, and taking the node S1' as a primary minimum associated node of the node S0;
judging whether the node S1 'is located on a critical path of the circuit, if so, searching an input port S2' with the highest turnover probability in the input ends of the logic units taking the node S1 'as the output, and taking the node S2' as a secondary minimum associated node of the original low-controllability node S0;
and repeating the process until the node Sn 'is found, the node Sn' is positioned on a non-critical path, the node Sn-1 'is positioned on a critical path, and the node Sn' is used as the n-level minimum associated node of the original low-controllability node.
Further, after n-level minimum associated nodes corresponding to all original low-controllability nodes to be searched are obtained, the repeated nodes are deleted.
Further, the key gate is an exclusive or gate.
Furthermore, a logic unit with the final associated node as an output end is used as a logic unit to be encrypted, one input end of the exclusive or gate is used as an encrypted key input end, the other input end of the exclusive or gate is connected with the output end of the logic unit to be encrypted, and the output end of the exclusive or gate replaces the output end of the logic unit to be encrypted.
Compared with the prior art, the method and the device can prevent the low controllability of the non-critical path node in the lower-level logic unit caused by the low controllability of the critical path node, reduce the hardware overhead of the circuit, avoid the redundancy of the circuit and improve the encryption efficiency.
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FIG. 1 is a schematic flow diagram of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, the method for protecting a low-controllability node of an integrated circuit based on logic encryption provided by the present invention mainly includes two parts:
firstly, aiming at the screened low-controllability nodes, searching n-level maximum associated nodes of the original low-controllability nodes.
In this embodiment, the low controllability of the node is measured by the turning probability of the node, and first, the input random vector of the circuit needs to be subjected to functional simulation, a waveform diagram of each node in the circuit under the input random vector is obtained through simulation, and is converted into waveform data of each node, and the turning probability of each node in the circuit is calculated by using the waveform data and is used as a basis for screening the low controllability node.
Then, among the preliminarily screened original low-controllability nodes, for one of the original low-controllability nodes S0, the input port S1 with the lowest rollover probability among the input ports of the logic unit with the node as the output is found, and is defined as the one-level maximum-associated node of the original low-controllability node S0, and whether the rollover probability of S1 is greater than a preset low-controllability node threshold is determined, and if the rollover probability is less than or equal to the threshold, the input port S2 with the lowest probability of rollover among the inputs of the logic unit whose output is the node S1 is sought, which is defined as the secondary maximum associated node of the original low controllability node S0, according to the index rule, until the maximum associated node Sn is found, the turning probability of Sn is larger than the preset threshold value of the low controllable node, and the turning probability of Sn-1 is smaller than or equal to the selected threshold value, Sn is defined as the n-level maximum associated node of the original low controllable node S0. Due to the connection relation of hardware logic, one low-controllability node may cause low controllability of a logic unit node connected in a later stage, and in order to avoid repeated encryption, the node leading to the original low-controllability node is found, so that the hardware overhead of logic encryption can be reduced.
Secondly, on the premise of the found n-level maximum correlation nodes, whether the positions of the nodes to be encrypted of the found n-level maximum correlation nodes are located in a critical path of the circuit needs to be judged, the critical path refers to a path with the longest delay in the circuit and relates to characteristics of the circuit such as delay, frequency and the like, and the characteristic that a hardware Trojan does not accord with concealment of the hardware Trojan is inserted into the critical path, so that the n-level maximum correlation nodes of a non-critical path need to be screened out and a key gate needs to be inserted for encryption.
In this embodiment, the key gate is an exclusive or gate, and the process of encrypting the node is as follows: and taking the logic unit with the node as an output end as a logic unit to be encrypted, taking one input end of the exclusive-OR gate as an encrypted key input end, connecting the other input end of the exclusive-OR gate with the output end of the logic unit to be encrypted, and replacing the connection relation of the output end of the logic unit to be encrypted by the output end of the exclusive-OR gate.
Thirdly, for the n-level maximum associated nodes in the critical path, in order to prevent the low controllable nodes on the critical path from affecting the low controllability of the nodes in the lower-level logic units, and also avoid inserting a key gate in the critical path, it is necessary to find the n-level minimum associated nodes of the original low controllable nodes corresponding to the n-level maximum associated nodes, among the preliminarily screened low controllability nodes, with respect to one of the original low controllability nodes S0 ' (i.e. the originally screened low controllability node S0 corresponding to the n-level maximum associated node in the critical path), find the input port S1 ' with the highest rollover probability in the input end of the upper-level logic unit, define it as the one-level minimum associated node of S0 ', determine whether S1 ' is the critical path node, if S1 ' is the critical path node, find the input port S2 ' with the highest rollover probability in the input end of the upper-level logic unit of S1 ', defining the node as a secondary minimum associated node of S0 'and judging whether the node is a critical path node or not until a minimum associated node Sn' is found, so that Sn 'is a non-critical path node and Sn-1' is a critical path node, and defining Sn 'as n-level minimum associated nodes of S0'.
Encrypting the found minimum associated node by using a key gate, wherein in the embodiment, the key gate is an exclusive or gate, and the process of encrypting the node is as follows: and taking the logic unit with the node as an output end as a logic unit to be encrypted, taking one input end of the exclusive-OR gate as an encrypted key input end, connecting the other input end of the exclusive-OR gate with the output end of the logic unit to be encrypted, and replacing the connection relation of the output end of the logic unit to be encrypted by the output end of the exclusive-OR gate. The method can avoid the low controllability of the non-critical path nodes at the rear stage caused by the low controllability of the critical path nodes, and improve the encryption efficiency.
In one embodiment of the present invention, as shown in fig. 1, the method specifically comprises the following steps:
1) and calculating the turnover probability of the internal node of the circuit.
2) The circuit information is stored.
3) And searching the maximum associated node of the n levels and deleting the duplicate nodes.
4) Judging whether the searched n-level maximum associated nodes are key path nodes or not, if not, performing logic encryption on the maximum associated nodes, if so, searching n-level minimum associated nodes of the original low controllable nodes and the non-key path pairs, deleting repeated nodes, and performing logic encryption on the n-level minimum associated nodes.
6) And traversing all original low controllable nodes to realize the encryption protection of the low controllable nodes in the integrated circuit.
The invention tests the circuits S1423, S1494, S1196 and S9234 in the ISCA 89 circuit, and the test results are shown in Table 1.
And defining an index A, namely the number of the key gates/the number of the low controllable nodes before encryption, which represents the circuit redundancy condition.
And defining an index B, namely the number of the low controllable nodes after encryption/the number of the low controllable nodes before encryption, which represents the encryption efficiency condition. The experimental results shown in table 2 were obtained.
The indicators A, B are compared to conventional encryption schemes, respectively, in table 2. The indexes A, B are all as small as possible, and as can be seen from the comparison of the above tables: the invention better balances the contradiction between the encryption efficiency and the circuit redundancy, not only can prevent the low controllability of the non-key path node in the lower-level logic unit caused by the low controllability of the key path node, but also can reduce the hardware overhead of the circuit, avoid the circuit redundancy and improve the encryption efficiency.
The foregoing lists merely illustrate specific embodiments of the invention. It is obvious that the invention is not limited to the above embodiments, but that many variations are possible. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the present invention are to be considered within the scope of the invention.
Claims (6)
1. A logic encryption-based integrated circuit low-controllability node protection method is characterized by comprising the following steps:
step 1: except for the output port of the integrated circuit, sequentially numbering the output nodes of all logic units in the integrated circuit, screening out original low-controllability nodes in the integrated circuit to form an original low-controllability node set, and recording the numbering of the original low-controllability nodes;
step 2: finding a final associated node corresponding to each original low-controllability node in the set:
searching the n-level maximum associated nodes of each original low-controllability node, wherein the method comprises the following steps:
recording the original low controllability node as S0;
searching an input port S1 with the lowest turnover probability in the input ends of the logic units with the node S0 as the output, and taking the node S1 as a primary maximum association node of the node S0;
judging whether the turnover probability of the node S1 is greater than a preset low-controllability node threshold, if so, searching an input port S2 with the lowest turnover probability in the input end of the logic unit with the node S1 as the output, and taking the node S2 as a secondary maximum associated node of the original low-controllability node S0;
repeating the process until the node Sn is found and obtained, the turnover probability of the node Sn is larger than a preset low-controllability node threshold value, the turnover probability of the node Sn-1 is smaller than or equal to the preset low-controllability node threshold value, and the node Sn is used as an n-level maximum associated node of the original low-controllability node;
judging the position of the n-level maximum correlation node, and if the position is on a non-critical path of the circuit, taking the n-level maximum correlation node as a final correlation node of the original low-controllability node; if the node is located on the critical path of the circuit, continuously searching the n-level minimum associated nodes of the original low-controllability node, wherein the method comprises the following steps:
recording the original low controllability node as S0;
searching an input port S1 'with the highest turnover probability in the input ends of the logic units with the node S0 as an output, and taking the node S1' as a primary minimum associated node of the node S0;
judging whether the node S1 'is located on a critical path of the circuit, if so, searching an input port S2' with the highest turnover probability in the input ends of the logic units taking the node S1 'as the output, and taking the node S2' as a secondary minimum associated node of the original low-controllability node S0;
repeating the process until the node Sn 'is found, the node Sn' is positioned on a non-critical path, the node Sn-1 'is positioned on a critical path, and the node Sn' is used as the n-level minimum associated node of the original low-controllability node;
taking the n-level minimum associated node as a final associated node of the original low-controllability node;
traversing each original low-controllability node in the set, so that each original low-controllability node corresponds to a final associated node;
and step 3: and inserting a key gate at a final associated node corresponding to all the original low-controllability nodes to logically encrypt the integrated circuit.
2. The logic encryption-based integrated circuit low-controllability node protection method according to claim 1, wherein the original low-controllability node is obtained by screening with a turnover probability as a measure;
the turning probability obtaining mode is as follows: the method comprises the steps of performing function simulation on an input random vector of an integrated circuit to obtain a waveform diagram of each node in the circuit under the input random vector, converting the waveform diagram into waveform data of each node, obtaining the turning probability of each node in the circuit by using the waveform data, and taking the node with the turning probability lower than a preset threshold value as an original low-controllability node.
3. The method according to claim 1, wherein after n-level maximum associated nodes corresponding to all original low-controllability nodes are obtained, the duplicate nodes are deleted.
4. The logic encryption-based integrated circuit low-controllability node protection method according to claim 1, wherein after n-level minimum associated nodes corresponding to all original low-controllability nodes to be searched are obtained, duplicate nodes are deleted.
5. The method of claim 1, wherein the key gate is an exclusive-or gate.
6. The logic encryption-based integrated circuit low-controllability node protection method according to claim 5, wherein a logic unit with the final associated node as an output end is used as a logic unit to be encrypted, one input end of an exclusive-or gate is used as an encrypted key input end, the other input end of the exclusive-or gate is connected with the output end of the logic unit to be encrypted, and the output end of the exclusive-or gate replaces the output end of the logic unit to be encrypted.
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