CN113364564A - Data transmission method, microprocessor, data transmission device and storage medium - Google Patents
Data transmission method, microprocessor, data transmission device and storage medium Download PDFInfo
- Publication number
- CN113364564A CN113364564A CN202110624282.2A CN202110624282A CN113364564A CN 113364564 A CN113364564 A CN 113364564A CN 202110624282 A CN202110624282 A CN 202110624282A CN 113364564 A CN113364564 A CN 113364564A
- Authority
- CN
- China
- Prior art keywords
- data packet
- current data
- external processor
- current
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000012795 verification Methods 0.000 claims description 41
- 238000012546 transfer Methods 0.000 claims description 10
- 238000004891 communication Methods 0.000 claims description 9
- 238000013461 design Methods 0.000 description 14
- 230000006870 function Effects 0.000 description 13
- 238000012545 processing Methods 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1829—Arrangements specially adapted for the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1867—Arrangements specially adapted for the transmitter end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
- H04L43/0829—Packet loss
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
- H04L43/0847—Transmission error
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Environmental & Geological Engineering (AREA)
- Communication Control (AREA)
Abstract
The application discloses a data transmission method, a microprocessor, data transmission equipment and a storage medium, relates to the technical field of computers, and can avoid the problems of packet loss or data transmission errors and the like when the microprocessor receives data packets transmitted by an external processor. The method comprises the following steps: the microprocessor receives a current data packet in a preset format sent by an external processor; then, the microprocessor determines the receiving progress of the current data packet; and then, the microprocessor controls the data packet sending state of the external processor according to the receiving progress of the current data packet and/or a checking result for checking the content in the current data packet.
Description
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a data transmission method, a microprocessor, data transmission equipment and a storage medium.
Background
The operation of the embedded microprocessor depends on program code, which is generally stored in a Flash (Flash EEPROM Memory) area of the microprocessor, and when the program code needs to be updated, new program code needs to be stored in the Flash area. Conventionally, program codes are generally copied from an external processor to a Flash area of a microprocessor through a communication protocol such as Universal Synchronous/Asynchronous Receiver/Transmitter (USART) or Integrated Circuit bus (IIC).
However, in the existing data transmission process of copying the program code from the external processor to the Flash area of the microprocessor, packet loss or data transmission errors are easy to occur.
Disclosure of Invention
The application provides a data transmission method, a microprocessor, data transmission equipment and a storage medium, which can avoid the problems of packet loss or data transmission errors and the like when the microprocessor receives data packets transmitted by an external processor.
In order to achieve the purpose, the technical scheme is as follows:
in a first aspect, the present application provides a data transmission method, applied to a microprocessor, including: the microprocessor receives a current data packet in a preset format sent by an external processor; then, the microprocessor determines the receiving progress of the current data packet; and then, the microprocessor controls the data packet sending state of the external processor according to the receiving progress of the current data packet and/or a checking result for checking the content in the current data packet.
In the technical scheme provided by the application, the receiving progress of the current data packet can represent whether the microprocessor receives the complete current data packet, and the verification result for verifying the content in the current data packet can represent whether the received current data packet has errors such as packet loss and the like. Therefore, the sending state of the data packet of the external processor is controlled by the receiving progress of the current data packet and/or the checking result of checking the content in the current data packet, and the problems of packet loss or data transmission errors and the like when the microprocessor receives the data packet transmitted by the external processor can be avoided.
Optionally, in a possible design, the "controlling the sending state of the data packet of the external processor according to the receiving progress of the current data packet and/or the checking result of checking the content in the current data packet" may include:
and controlling the data packet transmission state of the external processor to be stopped transmission under the condition that the receiving progress of the current data packet is determined as receiving completion.
Optionally, in another possible design, the "controlling the sending state of the data packet of the external processor according to the receiving progress of the current data packet and/or the verification result of verifying the content in the current data packet" may include:
and under the condition that the verification result of verifying the content in the current data packet is determined to be that the verification is passed, writing the current data packet, and controlling the data packet sending state of the external processor to be a new data packet continuously sent after writing.
Optionally, in another possible design, the "controlling the data packet sending state of the external processor according to the receiving progress of the current data packet and/or a verification result of verifying the content in the current data packet" may include:
and under the condition that the verification result of verifying the content in the current data packet is determined to be that the verification fails, controlling the data packet sending state of the external processor to be that the current data packet is retransmitted.
Optionally, in another possible design, the microprocessor is connected to the external processor through a general input/output interface, and the "controlling the packet sending status of the external processor" may include:
the level of the general input/output interface is controlled to control the data packet sending state of the external processor.
Optionally, in another possible design, the "determining the receiving progress of the current packet" may include: and under the condition that the receiving progress of the current data packet is determined to be receiving completion, triggering to execute content verification operation.
Optionally, in another possible design, the "determining the receiving progress of the current packet" may include: and under the condition that the cutoff field in the current data packet is detected, determining the receiving progress of the current data packet as receiving completion.
In a second aspect, the present application provides a microprocessor comprising: the device comprises a receiving module, a determining module and a control module;
the receiving module is used for receiving a current data packet in a preset format sent by an external processor;
the determining module is used for determining the receiving progress of the receiving module for receiving the current data packet;
and the control module is used for controlling the data packet sending state of the external processor according to the receiving progress of the current data packet determined by the determination module and/or a verification result for verifying the content in the current data packet.
Optionally, in a possible design, the control module is specifically configured to:
and under the condition that the determining module determines that the receiving progress of the current data packet is receiving completion, controlling the data packet sending state of the external processor to be sending stop.
Optionally, in another possible design, the control module is specifically configured to:
and under the condition that the determining module determines that the checking result of checking the content in the current data packet is that the checking is passed, writing the current data packet, and controlling the data packet sending state of the external processor to be a new data packet continuously sent after the writing.
Optionally, in another possible design, the control module is specifically configured to:
and under the condition that the determining module determines that the checking result of checking the content in the current data packet is that the checking is not passed, controlling the data packet sending state of the external processor to be that the current data packet is sent again.
Optionally, in another possible design, the microprocessor is connected to the external processor through a general input/output interface, and the control module is further specifically configured to:
the level of the general input/output interface is controlled to control the data packet sending state of the external processor.
Optionally, in another possible design manner, the determining module is specifically configured to:
and under the condition that the receiving progress of the current data packet is determined to be receiving completion, triggering to execute content verification operation.
Optionally, in another possible design manner, the determining module is specifically configured to:
and under the condition that the cutoff field in the current data packet is detected, determining the receiving progress of the current data packet as receiving completion.
In a third aspect, the present application provides a data transmission device, comprising a memory, a processor, a bus, and a communication interface; the memory is used for storing computer execution instructions, and the processor is connected with the memory through a bus; the processor executes computer-executable instructions stored by the memory to cause the data transfer device to perform the data transfer method as provided above in the first aspect when the data transfer device is in operation.
Further optionally, the data transmission device may be a physical machine for implementing data transmission, or may be a part of a device in the physical machine, for example, a system-on-chip in the physical machine. The system-on-chip is adapted to support the data transmission device to perform the functions referred to in the first aspect, e.g. to receive, transmit or process data and/or information referred to in the data transmission method described above. The chip system includes a chip and may also include other discrete devices or circuit structures.
In a fourth aspect, the present application provides a computer-readable storage medium having instructions stored therein, which when executed by a computer, cause the computer to perform the data transmission method as provided in the first aspect.
In a fifth aspect, the present application provides a computer program product comprising computer instructions which, when run on a computer, cause the computer to perform the data transmission method as provided in the first aspect.
It should be noted that all or part of the computer instructions may be stored on the computer readable storage medium. The computer-readable storage medium may be packaged with a processor of the data transmission device, or may be packaged separately from the processor of the data transmission device, which is not limited in this application.
For the descriptions of the second, third, fourth and fifth aspects in this application, reference may be made to the detailed description of the first aspect; in addition, for the beneficial effects described in the second aspect, the third aspect, the fourth aspect and the fifth aspect, reference may be made to beneficial effect analysis of the first aspect, and details are not repeated here.
In the present application, the names of the above-mentioned data transmission devices do not limit the devices or functional modules themselves, and in actual implementation, these devices or functional modules may appear by other names. Insofar as the functions of the respective devices or functional modules are similar to those of the present application, they fall within the scope of the claims of the present application and their equivalents.
These and other aspects of the present application will be more readily apparent from the following description.
Drawings
Fig. 1 is a schematic architecture diagram of a data transmission system according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a data transmission method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of another data transmission method according to an embodiment of the present application;
fig. 4 is a schematic flowchart of another data transmission method according to an embodiment of the present application;
fig. 5 is a schematic flowchart of another data transmission method according to an embodiment of the present application;
fig. 6 is a schematic flowchart of another data transmission method according to an embodiment of the present application;
FIG. 7 is a block diagram illustrating a microprocessor according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a data transmission device according to an embodiment of the present application.
Detailed Description
The data transmission method, the microprocessor, the data transmission device, and the storage medium provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.
The terms "first" and "second" and the like in the description and drawings of the present application are used for distinguishing different objects or for distinguishing different processes for the same object, and are not used for describing a specific order of the objects.
Furthermore, the terms "including" and "having," and any variations thereof, as referred to in the description of the present application, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the description of the present application, the meaning of "a plurality" means two or more unless otherwise specified.
The operation of the embedded microprocessor depends on program codes, the program codes are generally stored in a Flash area of the microprocessor, and when the program codes need to be updated, new program codes need to be stored in the Flash area. Conventionally, program codes are generally copied from an external processor to a Flash area of a microprocessor through a communication protocol such as USART or IIC.
However, in the existing data transmission process of copying the program code from the external processor to the Flash area of the microprocessor, packet loss or data transmission errors are easy to occur.
In view of the problems in the prior art, embodiments of the present application provide a data transmission method, a microprocessor, a data transmission device, and a storage medium, where a data packet sending state of an external processor is controlled by a receiving progress of a current data packet and/or a verification result of verifying content in the current data packet, so that problems such as packet loss or data transmission error occurring when the microprocessor receives the data packet transmitted by the external processor can be avoided.
The data transmission method provided by the embodiment of the application can be suitable for a data transmission system. Fig. 1 shows a structure of the data transmission system. As shown in fig. 1, the data transmission system includes a microprocessor 01 and an external processor 02. The microprocessor 01 is connected to an external processor 02.
The microprocessor 01 is used for receiving a current data packet in a preset format sent by the external processor 02 and determining the receiving progress of the current data packet; the microprocessor 01 is further configured to control a packet sending state of the external processor 02 according to a receiving progress of the current packet and/or a verification result of verifying a content in the current packet.
The external processor 02 is used for sending a current data packet in a preset format to the microprocessor 01; the external processor 02 is also used for sending the data packet to the microprocessor 01 according to the data packet sending state.
The data transmission method provided by the present application is described below with reference to the data transmission system shown in fig. 1.
Referring to fig. 2, the data transmission method provided in the embodiment of the present application includes S201 to S203:
s201, the microprocessor receives a current data packet in a preset format sent by the external processor.
The preset format is a data packet format determined in advance. For example, the current data packet in the preset format may include fields such as a command prompt, a field length, data, and a checksum.
In order to determine that the microprocessor receives the complete current data packet and distinguish the current data packet from other data packets, the current data packet in the preset format may further include a start-stop field for instructing the microprocessor to start receiving the current data packet and an end field for instructing the microprocessor to end receiving the current data packet.
As an example, the format of the current packet may be: start (start-stop field) + cmd (command prompt) + len (field length) + data.. data (data) + checksum) + stop (cutoff field).
It can be understood that, the application scenarios of the data transmission process provided in the embodiment of the present application may be: when the program code of the microprocessor needs to be updated, the external processor sends a data packet to which the program code belongs to the microprocessor through a communication protocol such as USART or IIC. Therefore, optionally, before the microprocessor receives the current data packet in the preset format sent by the external processor, the system of the microprocessor needs to initialize the USART or IIC when being powered on or reset, so that the external processor can send the data packet to which the program code belongs to the microprocessor through the USART or IIC, that is, control the USART or IIC to be in a receiving state.
S202, the microprocessor determines the receiving progress of the current data packet.
Optionally, in a possible implementation manner, the microprocessor may detect a field in the current data packet during the process of receiving the current data packet, and may determine that the reception progress of the current data packet is reception completion when the cutoff field in the current data packet is detected.
For example, when the start-stop field start is detected by the microprocessor, the current packet starts to be received, and when the stop field stop is detected by the microprocessor, the receiving progress of the current packet is determined as the receiving completion.
In order to enable the microprocessor to control the data packet sending state of the external processor based on the verification result of the complete current data packet, optionally, in a possible implementation process, the microprocessor triggers to execute a content verification operation under the condition that the receiving progress of the current data packet is determined to be the completion of receiving, so as to implement verification of the content in the current data packet.
S203, the microprocessor controls the data packet sending state of the external processor according to the receiving progress of the current data packet and/or the checking result of checking the content in the current data packet.
Optionally, in a possible implementation manner, the microprocessor may control a packet sending state of the external processor according to a receiving progress of the current packet. Specifically, the microprocessor controls the data packet transmission state of the external processor to stop transmission when determining that the reception progress of the current data packet is reception completion. Therefore, under the condition that the microprocessor determines that the receiving progress of the current data packet is receiving completion, the processing operation such as verification or writing can be carried out on the current data packet, and the data transmission error of the current data packet caused by the fact that the current data packet is covered by a new data packet sent by an external processor in the process of processing the current data packet by the microprocessor is avoided.
Optionally, in a possible implementation manner, the microprocessor may control a packet sending state of the external processor according to a verification result of verifying a content in the current packet. Specifically, the microprocessor writes the current data packet in the case that it is determined that the result of checking the content in the current data packet is a check pass, and controls the data packet transmission state of the external processor to continue to transmit the new data packet after the writing. In this way, the external processor can send a new data packet after the microprocessor writes the current data packet which is verified to be correct, so that the continuity of data transmission can be ensured under the condition that the transmission is ensured to be error-free.
The microprocessor writes the current data packet when determining that the checking result of the content in the current data packet is that the checking is passed, so that the phenomena of packet loss and the like when the external processor sends the current data packet can be avoided, and the wrong current data packet is prevented from being written.
For example, the check of the content in the current packet by the microprocessor may include checking fields such as cmd (command prompt) + len (field length) + data.. data (data) + checksum) in the current packet. It can be understood that, when the preset format further includes other fields, the microprocessor may also check the other fields in the current data packet, which is not limited in this embodiment of the present application.
It can be understood that the operating program of the microprocessor generally writes the data packet to which the program code belongs from the external processor into the Flash area of the microprocessor, so, optionally, the microprocessor may write the current data packet into the Flash area if it is determined that the verification result of verifying the content in the current data packet is that the verification passes.
Optionally, in another possible implementation manner, the microprocessor may control the data packet sending state of the external processor to be that the current data packet is resent, when it is determined that the verification result of verifying the content in the current data packet is that the verification fails.
When the microprocessor determines that the check result of checking the content in the current data packet is that the check fails, the packet loss or transmission error may occur in the process of receiving the current data packet, and at this time, the data packet sending state of the external processor is controlled to be that the current data packet is sent again, so that the external processor can send the current data packet again until the microprocessor determines that the check result of checking the content in the current data packet is that the check passes, namely, until the microprocessor receives the correct current data packet.
Optionally, in a possible implementation manner, the microprocessor may be connected to the external processor through a General-purpose input/output (GPIO) interface, and then control a packet transmission state of the external processor by controlling a level of the GPIO interface.
For example, the embodiment of the present application provides a method for controlling the packet transmission state of an external processor through the levels of two GPIO interfaces (GPIO1 interface and GPIO2 interface). The initial levels of the GPIO1 interface and the GPIO2 interface are both high level 1, and when the external processor detects that the levels of the GPIO1 interface and the GPIO2 interface are both 1, the current data packet can be normally sent to the microprocessor. When the microprocessor determines that the receiving progress of the current data packet is receiving completion, the electrical average of the GPIO1 interface and the GPIO2 interface may be set to 0, and when the external processor detects that the levels of the GPIO1 interface and the GPIO2 interface are both 0, the microprocessor indicates that the microprocessor starts processing or is analyzing the current data packet, and the data packet sending state of the external processor is sending stop, at which time, the external processor stops sending data packets to the microprocessor. After the microprocessor finishes checking the content in the current data packet, if the checking result is that the checking is passed, the electrical average of the GPIO1 interface and the GPIO2 interface can be set to 1, and when the external processor detects that the electrical levels of the GPIO1 interface and the GPIO2 interface are both 1, the microprocessor can continue to send new data packets. If the checking result is that the data packet is not verified, the GPIO1 interface level may be set to 1, the GPIO2 interface level may be set to 0, and when the external processor detects that the GPIO1 interface level is 1 and the GPIO2 interface level is 0, it indicates that a packet loss or a transmission error may occur in the current data packet received by the microprocessor, and the data packet sending state of the external processor is to resend the current data packet, at this time, the external processor needs to resend the current data packet to the microprocessor.
It should be understood that the control of the packet sending state of the external processor by controlling the level of the GPIO interface provided in this embodiment is merely an example, and in practical applications, the level of the GPIO interface may also be in other states, which is not limited in this embodiment.
In summary, in the data transmission method provided in the embodiment of the present application, the receiving progress of the current data packet may represent whether the microprocessor receives the complete current data packet, and the verification result for verifying the content in the current data packet may represent whether the received current data packet has errors such as packet loss. Therefore, in the embodiment of the application, the sending state of the data packet of the external processor is controlled by the receiving progress of the current data packet and/or the checking result of checking the content in the current data packet, so that the problems of packet loss or data transmission errors and the like when the microprocessor receives the data packet transmitted by the external processor can be avoided. .
In summary, as shown in fig. 3, step S203 in fig. 2 may be replaced with S2031:
s2031, the microprocessor controls the external processor to stop transmitting the data packet when determining that the current data packet reception progress is reception completion.
Alternatively, as shown in fig. 4, step S203 in fig. 2 may be replaced with S2032 to S2033:
s2032, the microprocessor writes the current data packet under the condition that the verification result of the content in the current data packet is determined to be passing the verification, and controls the data packet sending state of the external processor to be continuously sending the new data packet after the data packet is written.
S2033, the microprocessor controls the data packet sending state of the external processor to resend the current data packet under the condition that the verification result of verifying the content in the current data packet is determined to be that the verification fails.
Alternatively, as shown in fig. 5, step S203 in fig. 2 may be replaced with S2034:
s2034, the microprocessor controls the sending state of the data packet of the external processor by controlling the level of the general input/output interface according to the receiving progress of the current data packet and/or the verification result of verifying the content in the current data packet.
Optionally, to more clearly illustrate the data transmission method provided in the embodiment of the present application, referring to fig. 6, an embodiment of the present application further provides a data transmission method, which may be applied to the data transmission system shown in fig. 1, as shown in fig. 6, the method includes S601-S6012:
s601, initializing USART or IIC to be in a receiving state under the condition that the microprocessor is powered on or reset.
S602, the external processor sends the current data packet with the preset format to the microprocessor.
S603, the microprocessor receives the current data packet and judges whether the receiving progress of the current data packet is receiving completion.
The microprocessor executes step S604 when determining that the reception progress of the current packet is reception completion; and the microprocessor continues to repeatedly execute the step S603 under the condition that the receiving progress of the current data packet is determined to be not completed, until the receiving progress of the current data packet is determined to be completed.
S604, the microprocessor sets the level of the GPIO1 interface and the GPIO2 interface to 0 and starts to check the content in the current data packet.
And S605, detecting whether the levels of the GPIO1 interface and the GPIO2 interface are both 0 by the external processor.
The external processor executes step S606 in the case that it is determined that both the GPIO1 interface and the GPIO2 interface levels are detected to be 0; in the case that the external processor determines that the level of the GPIO1 interface or the GPIO2 interface is detected to be not 0, the external processor continues to repeatedly perform step S605 until the levels of the GPIO1 interface and the GPIO2 interface are detected to be 0.
And S606, stopping sending the data packet to the microprocessor by the external processor.
It can be understood that, in the embodiment of the present application, the order of the steps S605 and S606 and other steps (for example, S603 and S604) is not limited, and the steps S605 and S606 may be executed after S602.
S607, the microprocessor judges whether the checking result of the content in the current data packet is a check pass.
The microprocessor performs step S608 if it is determined that the result of the verification of the content in the current packet is a verification pass, and performs step S609 if it is determined that the result of the verification of the content in the current packet is a verification fail.
And S608, the microprocessor sets the level of the GPIO1 interface and the GPIO2 interface to be 1.
And S609, setting the level of the GPIO1 interface to be 1 and setting the level of the GPIO2 interface to be 0 by the microprocessor.
S6010, the external processor detects whether the level of the GPIO1 interface is 1 and whether the level of the GPIO2 interface is 0.
The external processor performs step S6011 in a case where it is determined that the level of the GPIO1 interface is detected to be 1 and the GPIO2 interface level is 0. The external processor performs step S6012 in a case where it is determined that the level of the GPIO1 interface is detected to be not 1 or the GPIO2 interface level is not 0.
S6011, the external processor resends the current data packet to the microprocessor.
S6012, the external processor sends a new data packet to the microprocessor.
It can be understood that, in the embodiment of the present application, the sequence of step S6010 and other steps (for example, step S607, step S608, and step S609) is not limited, and step S6010 may be executed after step S606.
As shown in fig. 7, an embodiment of the present application further provides a microprocessor, which may be the microprocessor in the data transmission system according to fig. 1 in the foregoing embodiment. The microprocessor includes: a receiving module 11, a determining module 12 and a control module 13.
The receiving module 11 executes S201 in the above method embodiment, the determining module 12 executes S202 in the above method embodiment, and the control module 13 executes S203 in the above method embodiment.
Specifically, the receiving module 11 is configured to receive a current data packet in a preset format sent by an external processor;
a determining module 12, configured to determine a receiving progress of the receiving module 11 receiving the current data packet;
and a control module 13, configured to control a data packet sending state of the external processor according to the receiving progress of the current data packet determined by the determination module 12 and/or a verification result obtained by verifying content in the current data packet.
Optionally, in a possible implementation manner, the control module 13 is specifically configured to:
in the case where the determination module 12 determines that the reception progress of the current packet is reception completion, the packet transmission state of the external processor is controlled to stop transmission.
Optionally, in another possible implementation manner, the control module 13 is specifically configured to:
in the case that the determination module 12 determines that the verification result of verifying the content in the current data packet is that the verification passes, the current data packet is written, and the data packet sending state of the external processor is controlled to continue sending the new data packet after the writing.
Optionally, in another possible implementation manner, the control module 13 is specifically configured to:
and under the condition that the determining module 12 determines that the checking result of checking the content in the current data packet is that the checking fails, controlling the data packet sending state of the external processor to be that the current data packet is sent again.
Optionally, in another possible implementation manner, the microprocessor is connected to the external processor through a general purpose input/output interface, and the control module 13 is further specifically configured to:
the level of the general input/output interface is controlled to control the data packet sending state of the external processor.
Optionally, in another possible implementation manner, the determining module 12 is specifically configured to:
and under the condition that the receiving progress of the current data packet is determined to be receiving completion, triggering to execute content verification operation.
Optionally, in another possible implementation manner, the determining module 12 is specifically configured to:
and under the condition that the cutoff field in the current data packet is detected, determining the receiving progress of the current data packet as receiving completion.
Optionally, the microprocessor may further include a storage module for storing a program code of the microprocessor, and the like.
As shown in fig. 8, an embodiment of the present application further provides a data transmission device, which includes a memory 41, a processor 42, a bus 43, and a communication interface 44; the memory 41 is used for storing computer execution instructions, and the processor 42 is connected with the memory 41 through a bus 43; when the data transfer device is operating, the processor 42 executes computer-executable instructions stored by the memory 41 to cause the data transfer device to perform the data transfer method applied to the microprocessor as provided in the above-described embodiments.
In particular implementations, processor 42(42-1 and 42-2) may include one or more Central Processing Units (CPUs), such as CPU0 and CPU1 shown in FIG. 8, as one example. And as an example, the data transmission device may include a plurality of processors 42, such as processor 42-1 and processor 42-2 shown in fig. 8. Each of the processors 42 may be a single-Core Processor (CPU) or a multi-Core Processor (CPU). Processor 42 may refer herein to one or more devices, circuits, and/or processing cores that process data (e.g., computer program instructions).
The memory 41 may be, but is not limited to, a read-only memory 41 (ROM) or other type of static storage device that can store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory 41 may be self-contained and coupled to the processor 42 via a bus 43. The memory 41 may also be integrated with the processor 42.
In a specific implementation, the memory 41 is used for storing data in the present application and computer-executable instructions corresponding to software programs for executing the present application. The processor 42 may perform various functions of the data transfer device by running or executing software programs stored in the memory 41, and by invoking data stored in the memory 41.
The communication interface 44 is any device, such as a transceiver, for communicating with other devices or communication networks, such as a control system, a Radio Access Network (RAN), a Wireless Local Area Network (WLAN), and the like. The communication interface 44 may include a receiving unit implementing a receiving function and a transmitting unit implementing a transmitting function.
The bus 43 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an extended ISA (enhanced industry standard architecture) bus, or the like. The bus 43 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 8, but this is not intended to represent only one bus or type of bus.
As an example, in connection with fig. 7, the function implemented by the receiving module in the microprocessor is the same as the function implemented by the receiving unit in the data transmission device in fig. 8, the function implemented by the processing module in the microprocessor is the same as the function implemented by the processor in the data transmission device in fig. 8, and the function implemented by the storage module in the microprocessor is the same as the function implemented by the memory in the data transmission device in fig. 8.
For the explanation of the related contents in this embodiment, reference may be made to the above method embodiments, which are not described herein again.
Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.
The embodiment of the present application further provides a computer-readable storage medium, in which instructions are stored, and when the computer executes the instructions, the computer is enabled to execute the data transmission method applied to the microprocessor provided in the foregoing embodiment.
The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a RAM, a ROM, an erasable programmable read-only memory (EPROM), a register, a hard disk, an optical fiber, a CD-ROM, an optical storage device, a magnetic storage device, any suitable combination of the foregoing, or any other form of computer readable storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC). In embodiments of the present application, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A data transmission method applied to a microprocessor is characterized by comprising the following steps:
receiving a current data packet in a preset format sent by an external processor;
determining the receiving progress of the current data packet;
and controlling the data packet sending state of the external processor according to the receiving progress of the current data packet and/or a checking result of checking the content in the current data packet.
2. The method according to claim 1, wherein the controlling the packet sending status of the external processor according to the receiving progress of the current packet and/or the checking result of checking the content in the current packet comprises:
and under the condition that the receiving progress of the current data packet is determined to be receiving completion, controlling the data packet sending state of the external processor to be sending stop.
3. The method according to claim 1, wherein the controlling the packet sending status of the external processor according to the receiving progress of the current packet and/or the checking result of checking the content in the current packet comprises:
and under the condition that the verification result of verifying the content in the current data packet is determined to be that the verification is passed, writing the current data packet, and controlling the data packet sending state of the external processor to be a new data packet continuously sent after writing.
4. The method according to claim 1, wherein the controlling the packet sending status of the external processor according to the receiving progress of the current packet and/or the checking result of checking the content in the current packet comprises:
and under the condition that the verification result of verifying the content in the current data packet is determined to be that the verification fails, controlling the data packet sending state of the external processor to be that the current data packet is sent again.
5. The method of claim 1, wherein the microprocessor is connected to the external processor through a general purpose input/output interface; the controlling of the packet transmission state of the external processor includes:
and controlling the data packet sending state of the external processor by controlling the level of the general input/output interface.
6. The method of claim 1, wherein determining the reception progress of the current packet comprises:
and triggering to execute content verification operation under the condition that the receiving progress of the current data packet is determined to be receiving completion.
7. The method of claim 1, wherein determining the reception progress of the current packet comprises:
and under the condition that the cutoff field in the current data packet is detected, determining the receiving progress of the current data packet as receiving completion.
8. A microprocessor, comprising:
the receiving module is used for receiving a current data packet in a preset format sent by an external processor;
the determining module is used for determining the receiving progress of the receiving module for receiving the current data packet;
and the control module is used for controlling the data packet sending state of the external processor according to the receiving progress of the current data packet determined by the determination module and/or a verification result for verifying the content in the current data packet.
9. A data transmission device comprising a memory, a processor, a bus and a communication interface; the memory is used for storing computer execution instructions, and the processor is connected with the memory through the bus;
a processor executes the computer-executable instructions stored by the memory when the data transfer device is operating to cause the data transfer device to perform the data transfer method of any one of claims 1-7.
10. A computer-readable storage medium having stored therein instructions, which when executed by a computer, cause the computer to perform a data transmission method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110624282.2A CN113364564A (en) | 2021-06-04 | 2021-06-04 | Data transmission method, microprocessor, data transmission device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110624282.2A CN113364564A (en) | 2021-06-04 | 2021-06-04 | Data transmission method, microprocessor, data transmission device and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113364564A true CN113364564A (en) | 2021-09-07 |
Family
ID=77532134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110624282.2A Pending CN113364564A (en) | 2021-06-04 | 2021-06-04 | Data transmission method, microprocessor, data transmission device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113364564A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316833A (en) * | 2000-04-06 | 2001-10-10 | 三星电子株式会社 | Data receiving processing method for communication equipment supporting blue-tooth radio communication |
| WO2010137178A1 (en) * | 2009-05-25 | 2010-12-02 | Hitachi,Ltd. | Storage subsystem |
| CN107135671A (en) * | 2015-06-17 | 2017-09-05 | 华为技术有限公司 | Car networking data transmission method and device |
| CN108052474A (en) * | 2018-01-02 | 2018-05-18 | 上海壹账通金融科技有限公司 | Conversion method of data format, device, equipment and computer readable storage medium |
| CN111641638A (en) * | 2020-05-28 | 2020-09-08 | 浪潮(北京)电子信息产业有限公司 | Data transmission method and related device |
| CN112261106A (en) * | 2020-10-16 | 2021-01-22 | 天津津航计算技术研究所 | File transmission method suitable for satellite communication mode |
| CN112380157A (en) * | 2020-11-26 | 2021-02-19 | 北京工业大学 | IIC bus communication device with FIFO cache and check function |
-
2021
- 2021-06-04 CN CN202110624282.2A patent/CN113364564A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316833A (en) * | 2000-04-06 | 2001-10-10 | 三星电子株式会社 | Data receiving processing method for communication equipment supporting blue-tooth radio communication |
| WO2010137178A1 (en) * | 2009-05-25 | 2010-12-02 | Hitachi,Ltd. | Storage subsystem |
| CN107135671A (en) * | 2015-06-17 | 2017-09-05 | 华为技术有限公司 | Car networking data transmission method and device |
| CN108052474A (en) * | 2018-01-02 | 2018-05-18 | 上海壹账通金融科技有限公司 | Conversion method of data format, device, equipment and computer readable storage medium |
| CN111641638A (en) * | 2020-05-28 | 2020-09-08 | 浪潮(北京)电子信息产业有限公司 | Data transmission method and related device |
| CN112261106A (en) * | 2020-10-16 | 2021-01-22 | 天津津航计算技术研究所 | File transmission method suitable for satellite communication mode |
| CN112380157A (en) * | 2020-11-26 | 2021-02-19 | 北京工业大学 | IIC bus communication device with FIFO cache and check function |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2474916B1 (en) | Device identifier selection | |
| CN111930676B (en) | Method, device, system and storage medium for communication among multiple processors | |
| US9473273B2 (en) | Memory system capable of increasing data transfer efficiency | |
| CN102541469A (en) | Method, equipment and system for protecting data in firmware storage system | |
| CN108647131B (en) | Output system of running log | |
| CN114826542B (en) | Data transmission method, device, equipment and medium based on asynchronous serial communication | |
| KR20180110482A (en) | System and method for testing memory | |
| CN113364564A (en) | Data transmission method, microprocessor, data transmission device and storage medium | |
| US20110200059A1 (en) | BIT Inversion For Communication Interface | |
| CN115129509A (en) | Data transmission method, device and medium | |
| CN111371799B (en) | Method, device and equipment for controlling data receiving and transmitting of MCTP (Multi-channel media Port) controller | |
| CN115454896A (en) | SMBUS-based SSD MCTP control message verification method and device, computer equipment and storage medium | |
| CN112311425B (en) | Method, device and storage medium for automatic detection of Bluetooth HCI mode | |
| CN111490919A (en) | Master-slave machine system, equipment terminal and communication verification method thereof | |
| CN111782531A (en) | Method and system for detecting firmware integrity of chip | |
| KR101660180B1 (en) | Ic card, portable electronic apparatus, and ic card processing apparatus | |
| CN117170704B (en) | Remote upgrading method and device based on hardware IIC | |
| CN115599408B (en) | Data burning method, equipment and storage medium of processor | |
| CN102455970B (en) | Multi-peripheral-equipment boot implementation method, equipment and system with reliability detection function | |
| CN110492979B (en) | Incremental data transmission method and device, slave and storage medium | |
| CN113220331A (en) | Program updating method, microprocessor, program updating device and storage medium | |
| CN117828574A (en) | Data reading method and device, electronic equipment and storage medium | |
| CN116521435A (en) | Serial port initialization method and device, electronic equipment and storage medium | |
| JP2023145216A (en) | Communication control apparatus and communication method | |
| CN117785782A (en) | Data detection method, device, equipment and medium based on NVMe 2.0 protocol |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210907 |