CN113364455A

CN113364455A - Phase-locked loop control circuit and phase-locked control method

Info

Publication number: CN113364455A
Application number: CN202010150397.8A
Authority: CN
Inventors: 熊江
Original assignee: Actions Technology Co Ltd
Current assignee: Actions Technology Co Ltd; Juxin Technology Co Ltd
Priority date: 2020-03-06
Filing date: 2020-03-06
Publication date: 2021-09-07

Abstract

The embodiment of the invention provides a phase-locked loop control circuit and a phase-locked control method, which are used for preventing the clock output by a phase-locked loop module from being abnormal, improving the operation efficiency and saving the power consumption. The circuit comprises: the phase-locked loop comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a loop frequency divider which are sequentially connected, wherein the voltage-controlled oscillator comprises a first oscillator and a second oscillator; the locking detection module is respectively connected with the switching module, the voltage-controlled oscillator and the loop frequency divider and used for detecting the locking state of the voltage-controlled oscillator, adjusting the state of the voltage-controlled oscillator according to the locking state and sending a selection signal to the switching module according to the locking state; and the switching module is connected with the voltage-controlled oscillator and used for selecting signal output from the output signal of the first oscillator and the output signal of the second oscillator according to the selection signal output by the locking detection module.

Description

Phase-locked loop control circuit and phase-locked control method

Technical Field

The invention relates to the field of integrated circuit design, in particular to a phase-locked loop control circuit and a phase-locked control method.

Background

A Phase-Locked Loop (PLL) is a feedback control circuit that controls the frequency and Phase of an oscillation signal inside a Loop using an externally input reference signal. In the process of processing electronic signals, the phase-locked loop can realize automatic tracking of the frequency of an output signal to the frequency of an input signal, so the phase-locked loop is widely applied to a closed-loop tracking circuit. In the field of clocks, clock phase-locked loops are widely used for clock generation.

A clock phase-locked loop generally consists of several parts: a Phase Detector (PD), a Low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a Loop divider (lpdi). In the prior art, a post-divider PSTDIV is usually cascaded to an output terminal of a PLL, so that a clock output range can be larger, or a working range of a voltage controlled oscillator VCO can be greatly reduced, thereby reducing design difficulty and improving reliability. Although the cascaded post-divider does not belong to a PLL per se, it can be treated as a source usually as a part of a clock phase-locked loop, since it has a large influence on the clock received by the post-stage system.

The phase detector PD is a unit that performs phase comparison, and functions to compare the phase difference between the input signal Fin and the feedback signal Fback, and its output average value, such as voltage, is proportional to the phase difference between the two input signals. The LPF is an active or passive low pass filter, and functions to filter out high frequency components in the output voltage of the phase detector, including mixing and other high frequency noise, to perform smoothing filtering, and finally output a control signal Vc, and generally consists of a resistor, a capacitor, or an inductor, and sometimes includes an operational amplifier. The voltage-controlled oscillator VCO is an oscillator whose oscillation frequency is controlled by a control voltage Vc, and the oscillation frequency and the control voltage have a monotonic relation, and the VCO outputs a corresponding oscillation frequency Fosc according to the control signal Vc.

As shown in fig. 1, in the phase-locked loop structure shown in fig. 1, a loop divider lpdi, which determines the multiplying factor of the input and output clocks, the multiplying factor may be an integer or a decimal, the relationship between the input and output clocks can be expressed by equation 1, and for a general PLL, the output frequency Fout is the oscillator frequency Fosc, where n (lpdi) is the dividing coefficient of lpdi:

fosc ═ N (LPDIV) Fin formula 1

Generally, after the PLL clock is locked, the phase difference between the feedback clock and the input clock is stable, and therefore a stable clock can be output. When we want to change the output frequency Fout of the PLL, we only need to change the corresponding coefficients of the divider.

However, for a PLL with a post-divider, as shown in fig. 2, the post-divider (PSTDIV will divide Fosc by an adjustment factor, which may be an integer or a decimal number, and the final clock output Fout may be represented by equation 2, where n (lpdi) is the division factor of lpdi and n (PSTDIV) is the division factor of PSTDIV:

fout [ N (LPDIV)/N (PSTDIV) ] & Fin formula 2

As is well known, the equation describing the second-order pll is a second-order nonlinear differential equation, and the VCO in the second-order pll system can be regarded as an ideal integrator. So from a system point of view, if the low pass filter LPF is first order, the phase locked loop PLL can be seen as a second order system. For a second-order system, a natural frequency omegan and a damping coefficient xi exist, and if parameters inside the system are suddenly changed, the system generates an intrinsic damping oscillation according to the characteristics of the system. Under the same LPF condition, the higher the VCO sensitivity is, the smaller ξ is, the locking is fast, but the larger the amplitude of the damped oscillation is; the larger ξ the smaller the amplitude of the ringing, the more 1 it is, the less ringing there is, but the lock-up time becomes very long. Since the damping factor cannot be accurately controlled and usually the PLL needs to lock as fast as possible, there is a certain amplitude of damped oscillation at the output.

When the system changes the frequency dividing ratio, the PLL needs to be locked again, and the locking action needs a certain time. The lock time is affected by the loop bandwidth, the frequency at which the lock begins and ends, the damping factor, etc. If a typical PLL is chosen, its second order response characteristic in the lock range is characterized by a damping factor. The locking is fast, the damping factor is small, and large overshoot occurs; even with the usual damping factor of 0.45 to 0.7, there is still some degree of overshoot.

As shown in fig. 3, in a PLL clock system variation characteristic, where the input reference frequency is 12.5 megahertz (MHz), and the divider coefficient is changed from 31 to 60, the output frequency should be changed from 387.5MHz (12.5 × 31) to 750MHz (12.5 × 60). The second order damped oscillation characteristic is clearly seen in fig. 3 and due to the overshoot that occurs with the oscillation, there is an output frequency of 780MHz during this period, which is greater than the target value of 750 MHz.

In the system on chip soc (system on chip), a dynamic Adaptive Voltage scaling (davs) technique is generally used for low power consumption. Within a certain range, the higher the voltage, the higher the highest frequency that a Central Processing Unit (CPU) can run, the higher the computing processing capacity, and the higher the power consumption. The requirements of different tasks on the computing power of a CPU are different, a simple control task only needs very low frequency, a complex video coding and decoding algorithm needs very high frequency, the frequency is continuously adjusted according to the task category, the voltage is reduced, and the power consumption can be greatly reduced. If the CPU operating voltage is at 1 volt (V) and the maximum operating frequency is only 770MHz, the PLL overshoot 780MH will cause system error and require a high voltage to avoid system collapse. The voltage is adjusted to a value that allows the system to operate at a higher frequency, such as 1.05V, 800MHz, with a margin of safety, but such a process results in increased power consumption.

If the pll clock can be prevented from overshooting, the above-mentioned system error can be avoided or power consumption can be reduced. Theoretically and in practice, the conventional overshoot will not be very large, e.g. 10% -20%, and therefore it will not be too problematic if the system provides a sufficient safety margin.

However, in many practical designs, the clock range can be wider by cascading a post-divider PSTDIV to the output of the conventional PLL, or the working range of the voltage-controlled oscillator VCO can be reduced, so that the design difficulty can be reduced, and the reliability can also be improved. Although the post-divider does not belong to a PLL per se, it is also usually treated as part of a phase locked loop due to its large influence. But the postdivider has a very distinct feature: because the output Fout is not in a loop and does not have the loop bandwidth characteristic of a second-order system, the relative output Fout is an impulse type instant response, so the output is directly influenced, and a serious overshoot problem is caused in many cases.

As shown in fig. 4, the system requires the clock to be raised from 375MHz to 387.5MHz, only 12.5MHz, but causes a severe overshoot due to the change in the post-divider coefficient. The loop division factor before switching is 60, and the loop division factor after switching is 2, so that the Fosc oscillation frequency is 750MHz, and the Fout output frequency is 375 MHz. Wherein the switching is achieved by changing the coefficients, the loop division coefficient becomes 31, and the post division coefficient becomes 1.

It can be seen from fig. 4 that the system settles to 387.5MHz after a long and massive overshoot. The reason for the overshoot is that the frequency of Fosc can only be changed gradually through the loop, the loop filter has a fixed bandwidth, the Vc controlled oscillator needs to gradually change from 750MHz to 387.5MHz, and then the division factor can change from 2 to 1 instantaneously, which results in Fout changing directly from the current 375MHz to 750 MHz. If the latter stage CPU cannot operate at such a high frequency, for example, it can only operate at a frequency of 500MHz at most, it will directly cause a dead halt. If the CPU is at 1V and the maximum operating frequency is only 500MHz, the overshoot frequency 750MH caused by the switching output of the PLL will inevitably cause the system to malfunction. In order to prevent the system from collapsing, the voltage needs to be adjusted high. However, in many cases, even if the voltage is adjusted high, the CPU operating speed cannot be increased all the time, for example, cannot be increased by 100%. In this case, the problem cannot be avoided by greatly increasing the power consumption, and the problem must be solved by adding extra hardware, and in order to prevent the system from making mistakes, the overshoot must be prevented.

In the prior art system, before the PLL clock frequency is increased, the clock required by the CPU is switched to a fixed lower frequency in advance, for example, another 32.768K or 12M low frequency oscillator is provided, and then the software waits for a safer specified time in order to allow the PLL sufficient time to stabilize the output. After the system clock is stabilized, the clock required by the CPU is switched back to the target frequency that the PLL has achieved.

This way of preventing the phase locked loop clock from overshooting is not a constant value in terms of time, e.g. the time required for the PLL frequency to switch is completely different from the time required from 50M to 700M. Even if the same switching requirements, such as start and stop frequencies, are the same, the chips will be different in the presence of variations in operating supply voltage, ambient temperature and manufacturing process, so the software can only assume a maximum time that is safe enough based on system test data. From the aspect of cost, the software needs an additional hardware clock resource if the software is to run under another safe clock. Because the voltages are different, the safe clocks are different, and only conservative lower clocks can be selected uniformly under the condition that the lowest value of the safe clocks cannot be determined.

In summary, the method adopted in the prior art to prevent the clock of the pll from being abnormal has long switching time and poor software running performance.

Disclosure of Invention

The embodiment of the invention provides a phase-locked loop control circuit and a phase-locked control method, which are used for preventing the clock output by a phase-locked loop module from being abnormal, improving the operation efficiency and saving the power consumption.

In a first aspect, an embodiment of the present invention provides a phase-locked loop control circuit, including: the phase-locked loop module comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a loop frequency divider which are sequentially connected, wherein the voltage-controlled oscillator comprises a first oscillator and a second oscillator, the loop frequency divider is used for feeding back an output signal of the oscillator connected with the low-pass filter in the voltage-controlled oscillator to the phase discriminator, wherein,

the locking detection module is respectively connected with the switching module, the voltage-controlled oscillator and the loop frequency divider and used for detecting the locking state of the voltage-controlled oscillator, adjusting the state of the voltage-controlled oscillator according to the locking state and sending a selection signal to the switching module according to the locking state, wherein the locking state comprises the locking state of the first oscillator and the locking state of the second oscillator;

and the switching module is connected with the voltage-controlled oscillator and used for selecting signal output from the output signal of the first oscillator and the output signal of the second oscillator according to the selection signal output by the locking detection module.

The phase-locked loop control circuit provided by the embodiment of the invention comprises: the phase-locked loop module comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a loop frequency divider which are sequentially connected, wherein a first oscillator and a second oscillator voltage-controlled oscillator are arranged in the voltage-controlled oscillator, the lock detection module is used for detecting the lock state of the voltage-controlled oscillator, the state of the voltage-controlled oscillator is adjusted according to the lock state, and a selection signal is sent to the switching module according to the lock state, the lock state comprises the lock state of the first oscillator and the lock state of the second oscillator, the switching module is used for outputting the selection signal according to the lock detection module, and the selection signal is output in the output signal of the first oscillator and the output signal of the second oscillator. Compared with the prior art, the switching time point of the switching module is the locking time point of the phase-locked loop module, so that each switching time is self-adaptive and shortest, and a system does not need redundant long-time unified waiting; and during the switching period, the system can be provided with a safe clock with the same frequency as the original clock, the CPU processing capacity is exerted, the clock output by the phase-locked loop module is prevented from being abnormal, the running efficiency is improved, and the power consumption is saved.

In a possible implementation, the lock detection module adjusts a state of the voltage-controlled oscillator according to the lock state, and is specifically configured to:

when the fact that the locking state of the voltage-controlled oscillator is changed into the unlocking state is detected, the connection between the target oscillator and the low-pass filter is controlled to be disconnected, the non-target oscillator and the low-pass filter are connected, the target oscillator is controlled to keep the current oscillation frequency, the target oscillator is an oscillator which is in a working state when the locking state of the voltage-controlled oscillator is locked, and the non-target oscillator is another oscillator except the target oscillator in the voltage-controlled oscillator.

The phase-locked loop control circuit provided by the embodiment of the invention controls to disconnect the target oscillator from the low-pass filter and connect the non-target oscillator with the low-pass filter when adjusting the output signal of the phase-locked loop module, namely, the target oscillator is separated from the phase-locked loop module and the non-target oscillator is connected into the phase-locked loop module, and the locking detection module is also used for controlling the clock output by the target oscillator to maintain the original stable frequency, so that the damped oscillation clock in the locking period is not output, and the clock is switched to a new clock after the internal damped oscillation clock is stable, thereby preventing the clock output by the phase-locked loop module from being abnormal, such as overshoot.

In a possible implementation manner, the lock detection module sends a selection signal to the switching module according to the lock status, and is specifically configured to:

and detecting whether the frequency of the output signal fed back by the loop frequency divider and the frequency of the input signal of the phase discriminator reach a locking characteristic condition or not, and sending a selection signal to the switching module according to a detection result.

In a possible implementation, the lock detection module is specifically configured to:

when the input signal of the phase discriminator and the output signal fed back by the loop frequency divider are determined not to reach the locking characteristic condition according to the detection result, the output signal used for indicating the selection of the target oscillator is sent to the switching module as the output selection signal; and

and when the input signal of the phase discriminator and the output signal fed back by the loop frequency divider reach the locking characteristic condition according to the detection result, sending a selection signal for indicating to select the output signal of the non-target oscillator as the output to the switching module.

In a possible implementation, the lock detection module detects a lock state of the voltage controlled oscillator, and is specifically configured to:

if the difference between the phase of the output signal fed back by the loop frequency divider and the phase of the input signal of the phase discriminator is larger than a preset threshold value, determining that the locking state of the voltage-controlled oscillator is detected to be changed into out-of-lock; and

and if the difference between the phase of the output signal fed back by the loop frequency divider and the phase of the input signal of the phase discriminator is smaller than or equal to a preset threshold value, determining that the locking state of the voltage-controlled oscillator is detected to be changed into locking.

In one possible implementation, the phase-locked loop control circuit further includes:

the phase-locked loop module further includes: the post frequency divider is connected with the voltage-controlled oscillator and comprises a first frequency divider and a second frequency divider, the first frequency divider is connected with the first oscillator, and the second frequency divider is connected with the second oscillator;

the circuit further comprises: the control detection module is respectively connected with the locking detection module and the phase-locked loop module, and is used for receiving a control signal of a frequency divider in the phase-locked loop module and sending a lock losing detection signal to the locking detection module when the control signal changes;

the switching module is connected with the post-frequency divider and is specifically used for: and selecting an output signal from the output signal of the first oscillator and the output signal of the second oscillator according to the selection signal output by the locking detection module.

In the phase-locked loop control circuit provided by the embodiment of the invention, the phase-locked loop module can also comprise a post-frequency divider, and when the phase-locked loop control circuit comprises the post-frequency divider, the circuit also comprises a control detection module. When the coefficient of the post-frequency divider is changed, the control detection module detects the change and resets the locking detection module instantly, so that the safety output control mechanism is started immediately to avoid accidental overshoot caused by the change of the frequency division coefficient of the post-frequency divider.

In one possible implementation, the control detection module comprises a first delay unit and an exclusive-nor operator connected in sequence, wherein,

the first delay unit is used for adjusting the size of the delay unit according to the change of the control signal to generate a delay signal and inputting the delay signal into the XNOR gate arithmetic unit;

and the same or gate arithmetic unit generates an unlocking detection signal according to the delay signal and transmits the unlocking detection signal to the locking detection module.

In one possible embodiment, the lock detection module comprises:

the second delay unit is used for delaying the input signal of the phase discriminator and sending the delayed input signal of the phase discriminator to the first trigger;

the third delay unit is used for delaying the output signal fed back by the loop frequency divider and sending the delayed output signal fed back by the loop frequency divider to the second trigger;

the first trigger is used for comparing an output signal fed back by the loop frequency divider with an input signal of the phase discriminator after time delay and generating a first comparison signal according to a comparison result;

the second trigger is used for comparing the input signal of the phase discriminator with the output signal fed back by the delayed loop frequency divider and generating a second comparison signal according to the comparison result;

and the arithmetic unit is used for carrying out logical AND operation on the first comparison signal and the second comparison signal to generate a selection signal.

In a second aspect, an embodiment of the present invention provides an electronic device, including the phase-locked loop control circuit provided in the first aspect of the embodiment of the present invention.

In a third aspect, an embodiment of the present invention provides a phase-locked control method, which is applied to a phase-locked loop control circuit provided in the first aspect of the embodiment of the present invention, and includes:

detecting a locking state of a voltage-controlled oscillator in a phase-locked loop control circuit, and adjusting the state in the voltage-controlled oscillator according to the locking state, wherein the locking state comprises a locking state of a first oscillator and a locking state of a second oscillator;

and generating a selection signal according to the locking state, wherein the selection signal is used for selecting signal output from the output signal of the first oscillator and the output signal of the second oscillator.

In one possible embodiment, adjusting the state in the voltage controlled oscillator based on the lock state comprises:

when the situation that the locking state of the voltage-controlled oscillator changes to be out-of-lock is detected, the target oscillator is disconnected from the low-pass filter, the non-target oscillator and the low-pass filter are connected, the target oscillator is controlled to keep the current oscillation frequency, the target oscillator is an oscillator which is in a working state when the locking state of the voltage-controlled oscillator is locked, and the non-target oscillator is another oscillator except the target oscillator in the voltage-controlled oscillator.

In one possible embodiment, generating the selection signal according to the lock state includes:

and detecting whether the frequency of the output signal fed back by the loop frequency divider and the frequency of the input signal of the phase discriminator reach a locking characteristic condition or not, and generating a selection signal according to a detection result.

In a possible implementation, generating the selection signal according to the detection result includes:

when the frequency of the output signal fed back by the loop frequency divider and the frequency of the input signal of the phase discriminator do not reach the locking characteristic condition according to the detection result, generating a selection signal for indicating to select the output signal of the target oscillator as output; and

and generating a selection signal for indicating to select the output signal of the non-target oscillator as an output when the frequency of the output signal fed back by the loop frequency divider and the frequency of the input signal of the phase discriminator reach the locking characteristic condition according to the detection result.

In a fourth aspect, an embodiment of the present invention provides a phase-locked control apparatus, which is applied to the phase-locked loop control circuit provided in the first aspect of the embodiment of the present invention, and includes:

the detection module is used for detecting the locking state of a voltage-controlled oscillator in the phase-locked loop control circuit and adjusting the state in the voltage-controlled oscillator according to the locking state, wherein the locking state comprises the locking state of a first oscillator and the locking state of a second oscillator;

and the selection module is used for generating a selection signal according to the locking state, and the selection signal is used for selecting signal output from the output signal of the first oscillator and the output signal of the second oscillator.

In a possible implementation, the detection module is specifically configured to:

In a possible implementation, the selection module is specifically configured to:

when the input signal of the input phase discriminator and the output signal fed back by the loop frequency divider are determined to not reach the locking characteristic condition according to the detection result of the detection module, generating a selection signal for indicating to select the output signal of the target oscillator as the output; and

and when the input signal of the detection phase discriminator and the output signal fed back by the loop frequency divider reach the locking characteristic condition according to the detection result of the detection module, generating a selection signal for indicating to select the output signal of the non-target oscillator as the output.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

FIG. 1 is a circuit schematic of a prior art phase locked loop;

FIG. 2 is a circuit schematic of another prior art PLL;

FIG. 3 is a diagram illustrating a variation characteristic of a PLL clock system according to the prior art;

FIG. 4 is a diagram illustrating varying characteristics of another PLL clock system of the prior art;

fig. 5 is a schematic diagram of a pll control circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram illustrating clock variation characteristics of a pll control circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a lock detection module according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another PLL control circuit according to an embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating clock variation characteristics of another PLL control circuit according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of a control detection module according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of a switching module according to an embodiment of the present invention;

fig. 12 is a schematic flowchart of a phase-locked loop control method according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a phase-locked loop control device according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention will be described in conjunction with the accompanying drawings, and it should be understood that the embodiments described herein are only for the purpose of illustrating and explaining the present invention, and are not intended to limit the present invention.

In view of the problems of long switching time and poor software running efficiency of the prior art, embodiments of the present invention provide a pll control circuit and a pll control scheme thereof for preventing the pll clock from being abnormal, improving the running efficiency and saving power consumption.

The circuit provided by the embodiment of the invention is explained in detail below with reference to the accompanying drawings.

As shown in fig. 5, an embodiment of the present invention provides a phase-locked loop control circuit, including:

the phase-locked loop comprises a phase detector 511, a low-pass filter 512, a voltage-controlled oscillator 513 and a loop divider 514, wherein the phase-locked loop module 51, the switching module 52 and the lock detection module 53 are sequentially connected, the voltage-controlled oscillator 513 comprises a first oscillator 513a and a second oscillator 513b, and the loop divider 514 is used for feeding back an output signal of an oscillator connected with the low-pass filter 512 in the voltage-controlled oscillator 513 to the phase detector 511.

And a lock detection module 53, connected to the switching module 52, the voltage controlled oscillator 513 and the loop divider 514, for detecting a lock state of the voltage controlled oscillator 513, adjusting a state of the voltage controlled oscillator 513 according to the lock state, and sending a selection signal to the switching module 52 according to the lock state, where the lock state includes a lock state of the first oscillator 513a and a lock state of the second oscillator 513 b.

And a switching module 52 connected to the voltage-controlled oscillator 513, for selecting a signal output from the output signal of the first oscillator 513a and the output signal of the second oscillator 513b according to the selection signal output by the lock detection module 53.

The lock detection module 53 is specifically configured to, when it is detected that the lock state of the voltage controlled oscillator 513 is out-of-lock, control to disconnect the target oscillator from the low-pass filter 512, connect the non-target oscillator with the low-pass filter 512, and control the target oscillator to maintain the current oscillation frequency, where the target oscillator is an oscillator in a working state when the lock state of the voltage controlled oscillator is locked, and the non-target oscillator is another oscillator in the voltage controlled oscillator except the target oscillator.

In specific implementation, when the lock detection module adjusts an output signal of the phase-locked loop module, the lock detection module controls to disconnect the target oscillator from the low-pass filter, connect the non-target oscillator with the low-pass filter, namely, the target oscillator is separated from the phase-locked loop module, and the non-target oscillator is connected to the phase-locked loop module.

In specific implementation, the lock detection module 53 sends a selection signal to the switching module 52 according to the lock state, and is specifically configured to:

whether the frequency of the output signal fed back by the loop divider 514 and the frequency of the input signal of the phase detector 511 reach the lock characteristic condition or not is detected, and a selection signal is sent to the switching module 52 according to the detection result.

In specific implementation, the lock detection module 53 is specifically configured to:

when the input signal of the phase detector 511 and the output signal fed back by the loop frequency divider 514 are determined not to reach the locking characteristic condition according to the detection result, a selection signal for indicating to select the output signal of the target oscillator as the output is sent to the switching module 52; and

when it is determined that the input signal of the phase detector 511 and the output signal fed back by the loop divider 514 reach the lock characteristic condition according to the detection result, a selection signal for instructing to select the output signal of the non-target oscillator as an output is sent to the switching module 52.

In specific implementation, the lock detection module 53 detects a lock state of the voltage controlled oscillator 513, and is specifically configured to: if the difference between the phase of the output signal fed back by the loop divider 514 and the phase of the input signal of the phase detector 511 is detected to be greater than a preset threshold, determining that the change of the locking state of the voltage-controlled oscillator 513 into out-of-lock is detected; and if it is detected that the difference between the phase of the output signal fed back by the loop divider 514 and the phase of the input signal of the phase detector 511 is smaller than or equal to a preset threshold, determining that the lock state of the voltage-controlled oscillator 513 is detected to be changed into lock, where the preset threshold may be set according to practical experience, and this is not limited in the embodiment of the present invention, for example, the preset threshold is 5 degrees.

As shown in fig. 6, it can be seen from the simulation result of the pll control circuit provided in the embodiment of the present invention that there is no overshoot at all during the locking period. After the system sends out the instruction of adjusting the clock at 150 microseconds (mus), the frequency of the output signal of the phase-locked loop module is still maintained to be around 387.5MHz, at this time, the first oscillator is separated from the phase-locked loop module and becomes open-loop oscillation, but because the input control port of the first oscillator becomes a high-impedance state, the output clock generates a little deviation due to parasitic effect; at the moment of 168 mus, the phase-locked loop module is locked again, and the output signal of the switching module is immediately switched to the accurate target value of 750MHz, namely the locking value of the second oscillator. But in practice, the clock performance of the second oscillator in the pll module is still the same as the original clock performance, and 780MHz clock overshoot still exists, but the clock overshoot is not output by the switching module.

As shown in fig. 7, the lock detection module includes:

the second delay unit 71 is configured to delay an input signal of the phase detector and send the delayed input signal of the phase detector to the first flip-flop;

a third delay unit 72, configured to delay an output signal fed back by the loop frequency divider, and send the delayed output signal fed back by the loop frequency divider to the second trigger;

the first flip-flop 73 is configured to compare an output signal fed back by the loop frequency divider with the delayed input signal of the phase discriminator, and generate a first comparison signal according to a comparison result;

a second flip-flop 74, configured to compare an input signal of the phase discriminator with an output signal fed back by the delayed loop frequency divider, and generate a second comparison signal according to a comparison result;

and operator 75 for performing a logical and operation on the first comparison signal and the second comparison signal to generate a selection signal.

In specific implementation, the lock detection module may be implemented by using the structure of the cross-delay latch in fig. 7. Assuming that the rising edges of the input signal Fin of the phase detector and the output signal Fback fed back by the loop frequency divider are aligned during the locking period of the phase-locked loop module, that is, the phase difference is constant, the rising edge of any delayed one can capture the high level of the other, and the outputs of the two flip-flops are always 1. When the loop divider is changed, its output signal Fback will change, and the new rising edge will differ from the input signal Fin of the phase detector by one or N oscillation periods. When the PLL is to increase the output frequency, the division factor of the loop divider is increased. E.g. from N to N + K, the output signal Fback fed back by the loop divider will be delayed by K cycles from the input signal Fin of the phase detector.

In specific implementation, if it is detected that a difference between a phase of an output signal fed back by the loop frequency divider and a phase of an input signal of the phase detector is greater than a preset threshold, it is determined that the lock state of the voltage-controlled oscillator is detected to be out-of-lock, for example, a difference between an input signal Fin of the phase detector and a rising edge of an output signal Fback fed back by the loop frequency divider is within an oscillation period, an output of the first flip-flop outputs 0, and sends out a selection signal LCK. The output signal of the second oscillator is gradually accelerated under the action of the phase-locked loop module until overshoot occurs, at this time, the edge of an output signal Fback fed back by the loop frequency divider leads the edge of an input signal Fin of the phase discriminator, and the second trigger outputs 0 again. If the difference between the phase of the output signal fed back by the loop frequency divider and the phase of the input signal of the phase discriminator is smaller than or equal to a preset threshold value, the locking state of the voltage-controlled oscillator is determined to be locked, namely when the edges of the input signal Fin of the phase discriminator and the output signal Fback fed back by the loop frequency divider are realigned within a certain range, the selection signal output by the locking detection module returns to 1.

As shown in fig. 8, another pll control circuit according to an embodiment of the present invention includes:

the phase-locked loop comprises a phase detector 811, a low-pass filter 812, a voltage-controlled oscillator 813, a loop frequency divider 814 and a post-frequency divider 815 connected with the voltage-controlled oscillator, wherein the phase detector is connected with the phase detector 811, the low-pass filter 812, the voltage-controlled oscillator 813, the loop frequency divider 814 and the control detection module 84 in sequence. The voltage-controlled oscillator 813 comprises a first oscillator 813a and a second oscillator 813b, and the loop divider 814 is configured to feed back an output signal of an oscillator connected to the low-pass filter 812 in the voltage-controlled oscillator 813 to the phase detector 811; the post-divider 815 includes a first divider 815a and a second divider 815b, the first divider 815a being coupled to a first oscillator 813a, and the second divider 815b being coupled to a second oscillator 813 b.

And the lock detection module 83 is connected to the switching module 82, the voltage controlled oscillator 813 and the loop divider 814 respectively, and is configured to detect a lock state of the voltage controlled oscillator 813, adjust a state of the voltage controlled oscillator 813 according to the lock state, and send a selection signal to the switching module 82 according to the lock state, where the lock state includes a lock state of the first oscillator 813a and a lock state of the second oscillator 813 b.

And the control detection module 84 is connected to the lock detection module 83 and the phase-locked loop module 81, and is configured to receive a control signal of a frequency divider in the phase-locked loop module 81, and send a lock loss detection signal to the lock detection module 83 when the control signal changes.

It should be noted that the control signal received by the control detection module may include an in-loop frequency division control signal for controlling the loop frequency divider and an out-of-loop frequency division control signal for controlling the post frequency divider, or may only include an out-of-loop frequency division control signal for controlling the post frequency divider.

The switching module 82 is connected to the post-divider 815, and is specifically configured to select an output signal from the output signal of the first oscillator and the output signal of the second oscillator according to the selection signal output by the lock detection module 83.

As shown in fig. 9, it can be seen from the simulation result of another pll control circuit provided in the embodiment of the present invention that there is no overshoot at all during the locking period. After the 129.4 mus time system sends out the instruction of adjusting the clock, the loop frequency division coefficient is changed from 60 to 31, the frequency division coefficient is changed from 2 to 1, the frequency of the output signal of the phase-locked loop module is still maintained to be about 387MHz, at the moment, the first oscillator is separated from the phase-locked loop module and is changed into open-loop oscillation, but because the input control port of the first oscillator is changed into a high-impedance state, the output clock generates a little deviation due to parasitic effect; at 144 mus the phase locked loop module has locked again and the output signal of the switching module switches immediately to the accurate target value of 387.5MHz, i.e. the locking value of the second oscillator. But actually, the clock performance of the second oscillator in the pll module is still the same as the original clock performance, and there is still a clock overshoot of 750MHz, but there is no output from the switching module.

When the phase-locked loop module containing the post-frequency divider needs to increase the clock, besides a mode of independently increasing the loop frequency division coefficient, other coefficient adjustment modes exist, and when the loop frequency division coefficient is smaller, the post-frequency divider coefficient is also smaller. For example, when the clock is increased from 375MHz to 12.5MHz, the loop division factor is decreased, i.e., from 60 to 31, and thereafter the division factor is also decreased, i.e., from 2 to 1. After the adjustment of the coefficient, the first frequency division result causes that the output signal Fback fed back by the loop frequency divider will be 29 cycles earlier than the input signal Fin of the phase detector. As long as the delay period of the third delay unit in fig. 7 is designed within a reasonable range, the output of the second flip-flop will output 0 and send out the selection signal LCK. The output signal of the second frequency divider is gradually reduced under the action of the phase-locked loop module. And when the input signal Fin of the phase detector and the edge of the output signal Fback fed back by the loop frequency divider are realigned to be within a certain range, the selection signal output by the locking detection module is changed back to 1.

As shown in fig. 10, the control detection module includes:

the first delay unit 101 is used for adjusting the size of the delay unit according to the change of the control signal to generate a delay signal, and inputting the delay signal into the exclusive-nor operator;

the exclusive-nor operator 102 generates an out-of-lock detection signal according to the delay signal and transmits the out-of-lock detection signal to the lock detection module.

In a specific implementation, the control signal received by the control detection module may include an intra-loop frequency division control signal for controlling the loop frequency divider and an extra-loop frequency division control signal for controlling the post-frequency divider, or may only include an extra-loop frequency division control signal for controlling the post-frequency divider. Because the in-loop divide control signal of the control loop divider can be detected by the lock detect module by affecting the edge of the output signal Fback fed back by the loop divider even if it does not enter the control detect module. However, if the out-of-loop frequency division control signal of the controlled frequency divider changes, an out-of-lock detection signal needs to be sent to the lock detection module immediately, and the selection signal LCK output by the lock detection module starts the on-line selection mode of the switching module, the voltage-controlled oscillator and the frequency divider behind the voltage-controlled oscillator. The out-of-lock detection signal sent by the control detection module may be a single pulse signal, or may be a plurality of more complex timing control signals, and fig. 10 shows a circuit implemented by a first delay unit and an exclusive or nor logic circuit, and when the intra-loop frequency division control signal and/or the intra-loop frequency division control signal are/is changed, a negative pulse with a time width equal to the size of the delay unit is generated.

In specific implementation, the switching module may adopt a simpler manner, such as a multiplexer, but may have an error in the switching process; an interdigitated feedback dual latch output configuration, as shown in fig. 11, may also be used, which is more secure than a multiplexer. The intercrossing feedback double-latch output structure can safely switch two asynchronous clocks without intentionally generating narrow pulses. Of course, other similar functions may be performed, and the present invention is not limited thereto.

The embodiment of the invention also provides electronic equipment which comprises the phase-locked loop control circuit provided by the embodiment of the invention.

Based on the same inventive concept, an embodiment of the present invention further provides a phase-locked control method, which is applied to the phase-locked loop control circuit provided in the embodiment of the present invention, as shown in fig. 12, and the phase-locked control method may include the following steps:

and step 121, detecting a locking state of a voltage-controlled oscillator in the phase-locked loop control circuit, and adjusting the state in the voltage-controlled oscillator according to the locking state, wherein the locking state comprises a locking state of a first oscillator and a locking state of a second oscillator.

And step 122, generating a selection signal according to the locking state, wherein the selection signal is used for selecting signal output from the output signal of the first oscillator and the output signal of the second oscillator.

Based on the same inventive concept, the embodiment of the invention also provides a phase-locked control device.

As shown in fig. 13, an embodiment of the present invention further provides a phase-locked control device, which is applied to the phase-locked loop control circuit provided in the embodiment of the present invention, and includes:

the detection module 131 detects a locking state of a voltage-controlled oscillator in the phase-locked loop control circuit, and adjusts a state in the voltage-controlled oscillator according to the locking state, wherein the locking state includes a locking state of a first oscillator and a locking state of a second oscillator;

and a selection module 132, configured to generate a selection signal according to the lock state, where the selection signal is used to select a signal output from the output signal of the first oscillator and the output signal of the second oscillator.

In a possible implementation, the detection module 131 is specifically configured to:

In a possible implementation, the selection module 132 is specifically configured to:

when the input signal of the input phase discriminator and the output signal fed back by the loop frequency divider are determined not to reach the locking characteristic condition according to the detection result of the detection module 131, a selection signal for indicating to select the output signal of the target oscillator as the output is generated; and

when it is determined according to the detection result of the detection module 132 that the input signal of the detection phase detector and the output signal fed back by the loop frequency divider reach the lock characteristic condition, a selection signal for instructing to select the output signal of the target oscillator as an output is generated.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A phase-locked loop control circuit, comprising: the phase-locked loop comprises a phase discriminator, a low-pass filter, a voltage-controlled oscillator and a loop frequency divider which are sequentially connected, wherein the voltage-controlled oscillator comprises a first oscillator and a second oscillator, the loop frequency divider is used for feeding back an output signal of an oscillator connected with the low-pass filter in the voltage-controlled oscillator to the phase discriminator, wherein,

the locking detection module is respectively connected with the switching module, the voltage-controlled oscillator and the loop frequency divider, and is configured to detect a locking state of the voltage-controlled oscillator, adjust a state of the voltage-controlled oscillator according to the locking state, and send a selection signal to the switching module according to the locking state, where the locking state includes a locking state of a first oscillator and a locking state of a second oscillator;

2. The circuit of claim 1, wherein the lock detection module adjusts the state of the voltage controlled oscillator according to the lock status, and is specifically configured to:

when the fact that the locking state of the voltage-controlled oscillator is changed into the unlocking state is detected, controlling to disconnect a target oscillator from the low-pass filter, connecting a non-target oscillator and the low-pass filter, and controlling the target oscillator to keep the current oscillation frequency, wherein the target oscillator is an oscillator which is in a working state when the locking state of the voltage-controlled oscillator is locked, and the non-target oscillator is another oscillator except the target oscillator in the voltage-controlled oscillator.

3. The circuit according to claim 2, wherein the lock detection module sends a selection signal to the switching module according to the lock status, specifically configured to:

4. The circuit of claim 3, wherein the lock detection module is specifically configured to:

when the frequency of the output signal fed back by the loop frequency divider and the frequency of the input signal of the phase discriminator do not reach the locking characteristic condition according to the detection result, sending a selection signal for indicating to select the output signal of the target oscillator as the output to the switching module; and

and when the frequency of the output signal fed back by the loop frequency divider and the frequency of the input signal of the phase discriminator reach a locking characteristic condition according to the detection result, sending a selection signal for indicating to select the output signal of the non-target oscillator as output to the switching module.

5. The circuit of claim 1, wherein the lock detection module detects a lock state of the voltage controlled oscillator, and is specifically configured to:

if the difference between the phase of the output signal fed back by the loop frequency divider and the phase of the input signal of the phase discriminator is larger than a preset threshold value, determining that the change of the locking state of the voltage-controlled oscillator is the loss of lock; and

and if the difference between the phase of the output signal fed back by the loop frequency divider and the phase of the input signal of the phase discriminator is smaller than or equal to the preset threshold, determining that the change of the locking state of the voltage-controlled oscillator is locking.

6. The circuit of claim 1,

the switching module is connected with the post-frequency divider, and is specifically configured to: and selecting an output signal from the output signal of the first oscillator and the output signal of the second oscillator according to the selection signal output by the locking detection module.

7. The circuit of claim 6, wherein the control detection module comprises a first delay cell, an exclusive-OR gate operator, connected in sequence, wherein,

and the exclusive OR gate arithmetic unit is used for generating the out-of-lock detection signal according to the delay signal and transmitting the out-of-lock detection signal to the lock detection module.

8. The circuit of claim 1, wherein the lock detection module comprises:

and the and operator is used for carrying out logic and operation on the first comparison signal and the second comparison signal to generate a selection signal.

9. An electronic device, characterized in that the electronic device comprises a phase locked loop control circuit according to any of claims 1-8.

10. A phase-locked control method applied to a phase-locked loop control circuit according to any one of claims 1 to 8, comprising:

detecting a locking state of a voltage-controlled oscillator in the phase-locked loop control circuit, and adjusting the state of the voltage-controlled oscillator according to the locking state, wherein the locking state comprises a locking state of a first oscillator and a locking state of a second oscillator;

and generating a selection signal according to the locking state, wherein the selection signal is used for selecting signal output from the output signals of the first oscillator and the second oscillator.

11. The method of claim 10, wherein the adjusting the state in the voltage controlled oscillator according to the lock state comprises:

when the situation that the locking state of the voltage-controlled oscillator changes to be out-of-lock is detected, disconnecting a target oscillator from the low-pass filter, connecting a non-target oscillator with the low-pass filter, and controlling the target oscillator to keep the current oscillation frequency, wherein the target oscillator is an oscillator which is in a working state when the locking state of the voltage-controlled oscillator is locked, and the non-target oscillator is another oscillator except the target oscillator in the voltage-controlled oscillator.

12. The method of claim 11, wherein generating a select signal based on the lock status comprises:

13. The method of claim 12, wherein generating the selection signal according to the detection result comprises:

when the frequency of the output signal fed back by the loop frequency divider and the frequency of the input signal of the phase discriminator do not reach the locking characteristic condition according to the detection result, generating a selection signal for indicating to select the output signal of the target oscillator as the output; and

and when the frequency of the output signal fed back by the loop frequency divider and the frequency of the input signal of the phase discriminator reach a locking characteristic condition according to the detection result, generating a selection signal for indicating to select the output signal of the non-target oscillator as an output.