CN113361134B - Simulation verification method for uniform charge transfer dynamic line period imaging - Google Patents
Simulation verification method for uniform charge transfer dynamic line period imaging Download PDFInfo
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Abstract
The invention discloses a simulation verification method for uniform charge transfer dynamic line period imaging, relates to the technical field of simulation verification of charge transfer dynamic line period imaging, and solves the problems that the work time sequence designed by the existing method has jumping along the position, so that the charge transfer is not output, and the abnormality occurs. By the characteristics of the imaging system, the accurate positioning of the abnormal line period possibly occurring is carried out, the judgment of the state can be carried out quickly, and the design verification period is saved; the line cycle length is automatically changed at equal intervals through the controller equipment, judgment is carried out through the quick-vision equipment, the phenomenon that the judgment is missed due to fatigue caused by manpower is avoided, and meanwhile, the judgment speed is increased.
Description
Technical Field
The invention relates to a simulation verification system for uniform charge transfer dynamic line period imaging, in particular to a simulation verification system for uniform charge transfer dynamic line period imaging under the condition that an asynchronous working mode has a camera synchronization requirement at the same time.
Background
Mapping camera application, requiring that the deviation of the full-color spectrum shooting synchronicity of all detectors is not more than 1 pixel clock; the deviation of the camera synchronism of the multispectral spectral bands of all the detectors does not exceed 1 pixel clock; the camera synchronicity between all panchromatic and multispectral varies by no more than 1 pixel clock on a fixed time delay basis. For the application of a CMOS detector for outputting serial image data, the working frequency of the CMOS detector is integral multiple of the pixel clock frequency, the requirement on jitter is high, and the problem of training failure easily occurs when common cables are adopted for transmission; for 5-spectral-band-in-one detector applications, where the multispectral line period length is four times the panchromatic length, abrupt changes in the drive signal transition edges may occur during variations in the line period length.
Disclosure of Invention
The invention provides a simulation verification method for uniform charge transfer dynamic line period imaging, which aims to solve the problems that in the working time sequence designed by the existing method, the jump occurs along the position of a jump edge, so that the charge transfer is not output, the abnormity occurs and the like.
The simulation verification method of the uniform charge transfer dynamic line period imaging is realized by the following steps:
firstly, outputting, transferring and controlling a driving signal to be transmitted to a detector by a driving and level conversion circuit in an imaging unit;
in the process of transferring and controlling the line period length change of the driving signal, when the jump edge of the driving signal is suddenly changed,
setting the corresponding relation among the line cycle length line _ length _ tubulan, the exposure start time pos _ start _ expose, the initial jump edge position pos _ default and the default line cycle length line _ default of the drive signal corresponding to the jump edge position of the drive signal as follows:
setting the line period corresponding to the edge position pos _ sense of the transfer and control driving signal sensitive area as follows:
Setting the line period at the center pos _ sense _ center of the transfer and control driving signal sensitive area to be:
Step two, outputting a hard line period by adopting a controller simulation device, and designing line period combinations of nine combination modes for the current period as the input of an imaging unit according to the corresponding relation set in the step one; the nine combination modes are as follows:
(1) Four identical current line periods;
(2) Current line period-1, current line period;
(3) Current line period, current line period-1, current line period;
(4) Current line period, current line period-1, current line period;
(5) Current line period, current line period-1;
(6) Current line period +1, current line period;
(7) Current line period, current line period + -1, current line period;
(8) Current line period, current line period +1, current line period;
(9) Current line period, current line period +1;
and thirdly, judging the image gray scale of the image output by the imaging unit through a quick vision device, and judging that an image meeting the requirement is output when the deviation of the image gray scale exceeds 50DN, wherein DN is the gray scale.
The invention has the beneficial effects that: the invention designs the test case according to the mechanism and the test condition from the aspects of simulation excitation and test verification and from the mechanism of possible abnormal phenomena, thereby finding possible problems in the design in advance, shortening the design period and reducing the engineering risk.
1. By the characteristics of the imaging system, the accurate positioning of the abnormal line period possibly occurring is carried out, the judgment of the state can be carried out quickly, and the design verification period is saved;
2. the line cycle length is automatically changed at equal intervals through the controller device, judgment is carried out through the quick-vision device, the condition that the judgment is missed due to fatigue caused by manual work is avoided, and meanwhile, the judgment speed is accelerated.
Drawings
FIG. 1 is a functional block diagram of an imaging system in a simulation verification system for uniform charge transfer dynamic line cycle imaging according to the present invention;
FIG. 2 is a schematic block diagram of a simulation verification system for uniform charge transfer dynamic line cycle imaging according to the present invention.
Detailed Description
The simulation verification method of the uniform charge transfer dynamic line period imaging is realized by a simulation verification system which comprises a controller simulation device, an imaging unit and a quick-view device;
the controller simulation equipment outputs a hard-line periodic signal to the imaging unit, and the parallel image output by the imaging unit is subjected to image gray level judgment through the quick-vision equipment, so that the simulation verification of the image is realized.
The imaging unit comprises a driving and level conversion circuit, a detector, a 2711 module and an imaging FPGA; the imaging FPGA comprises a line period processing module, a time sequence driving module and a data training and integrating module; an asynchronous system is arranged between the imaging controller and the imaging unit;
the imaging controller outputs a main backup line periodic signal, a backup line periodic signal and a main backup identification signal to the camera imaging unit; the line period processing module selects and uses the main backup line period signal or the backup line period signal to generate a panchromatic line starting pulse, a multispectral line starting pulse, panchromatic line period length data and multispectral line period length data required by the time sequence driving module according to the received main backup identification signal;
setting the period length of the panchromatic row starting pulse to be the same as the panchromatic row period signal length, setting the panchromatic row period signal length to be the same as the main backup row period signal length or the backup row period signal length selected according to the main backup identification signal, setting the width of the panchromatic row starting pulse to be equal to or more than 1 pixel clock period, and setting the rising edge position time of the panchromatic row starting pulse to lag the panchromatic row period length data updating time;
the multispectral row starting pulse has the same period length as the multispectral row periodic signal length, and the multispectral row periodic signal length is the same as the accumulated value of the four adjacent main backup row periodic signal lengths or the accumulated value of the four adjacent backup row periodic signal lengths selected according to the main backup identification signals;
the width of the multispectral row starting pulse is equal to or more than 1 pixel clock period, and the rising edge position time lags behind the multispectral row period length data updating time;
the lag time is greater than or equal to 1 pixel clock cycle and less than 20 pixel clock cycles.
The transfer and control level signal output by the time sequence driving module is converted into a transfer and control driving signal through a driving and level conversion circuit and then is sent to a detector;
the serial image data output by the detector is output to the 2711 module through the data training and integrating module and is finally output through the data transmission interface.
The simulation verification method described in this embodiment specifically includes:
firstly, outputting, transferring and controlling a driving signal to be transmitted to a detector by a driving and level conversion circuit in an imaging unit;
the possibility of abrupt transitions in the position of signal transitions in the vicinity of the update position of the transition and control drive signal occurs, when, during the variation of the line period length of the transition and control drive signal, abrupt transitions in the edge of the drive signal occur,
setting the corresponding relation among the line cycle length line _ length _ tubulan, the exposure start time pos _ start _ expose, the initial jump edge position pos _ default and the default line cycle length line _ default of the drive signal corresponding to the jump edge position of the drive signal as follows:
setting the line period corresponding to the edge position pos _ sense of the transfer and control driving signal sensitive area as follows:
Setting the line period at the transfer and control drive signal sensitive area center pos _ sense _ center as:
Step two, adopting a controller simulation device to output a hard line period, and testing the line period change of the excitation into incremental increase, decremental decrease and large step distance change according to the corresponding relation set in the step one; designing line period combination of nine combination modes as the input of the imaging unit for the current period; the nine combination modes are as follows:
(1) Four identical current line periods;
(2) Current line period-1, current line period;
(3) Current line period, current line period-1, current line period;
(4) Current line period, current line period-1, current line period;
(5) Current line period, current line period-1;
(6) Current line period +1, current line period;
(7) Current line period, current line period +1, current line period;
(8) Current line period, current line period +1, current line period;
(9) Current line period, current line period +1;
and thirdly, judging the image gray level of the image output by the imaging system through a quick-vision device, and judging that an image meeting the requirement is output when the deviation of the image gray level exceeds 50DN, wherein DN is the gray level.
In this embodiment, the controller analog device outputs a hard line period signal, the line period signal length is increased by 1 and decreased by 1 under the condition of continuous same length, and the large step distance is increased and decreased, and the image gray scale is judged by the quick-view device according to the fact that the gray scale value of the image has large deviation and the image output is in accordance with the requirement when the deviation exceeds 50 DN.
In this embodiment, the multispectral line-period signal length B1There are two possible values; when the length of the panchromatic line periodic signal is a constant value, the length of the multispectral line periodic signal is B1=4p; multispectral line periodic signal length B when panchromatic line periodic signal length is different value1＝p1+p2+p3+p4；
p1、p2、p3、p4Respectively, the lengths of the four adjacent panchromatic line periodic signals, and p is the length of the constant panchromatic line periodic signal.
In this embodiment, the panchromatic row start pulse and the multispectral row start pulse respectively reset a panchromatic time sequence counter and a multispectral time sequence counter in the time sequence driving module; the jumping edge updating time of each panchromatic driving control signal is the time when the count value of the panchromatic time sequence counter is 0; and the updating time of the jumping edge of each multispectral driving control signal is the time when the counting value of the multispectral time sequence counter is 0.
In this embodiment, the position of the transition edge of each transition and control driving signal output by the driving and level converting circuit is determined according to the length p of the currently input panchromatic line periodic signal and the length B of the multispectral line periodic signal1The position area of the jump edge available for the panchromatic transfer and control drive signal is (3,p), and the position area of the jump edge available for the multispectral transfer and control drive signal is (3,B)1-3); when the jump edge position of the panchromatic image obtained by calculation is between 0 and 3, setting the jump edge position to be 3; when the jump edge position of the panchromatic image obtained through calculation is in the range from p-3 to p-1, setting the jump edge position as p-3;
when the position of the hopping edge of the multispectral obtained by calculation is between 0 and 3, setting the position of the hopping edge as 3; when the position of the jump edge of the multispectral obtained by calculation is in B1-3～B11, then set the position of the jump edge toB1-3。
In the embodiment, the detector adopts a TDICMOS detector of a long-light-core company; the 2711 module adopts a TLK2711 chip; the driving and level conversion circuit is mainly based on a level conversion chip ISL7457; the imaging controller mainly adopts an FPGA and a refreshing chip of Shanghai Compound denier microelectronics company; the imaging FPGA uses XQ5VFX100T from Xilinx.
Claims (7)
1. The simulation verification method of the uniform charge transfer dynamic line period imaging is characterized by comprising the following steps: the method is realized by the following steps:
firstly, outputting, transferring and controlling a driving signal to be transmitted to a detector by a driving and level conversion circuit in an imaging unit;
in the process of transferring and controlling the line period length change of the driving signal, when the jump edge of the driving signal is suddenly changed,
setting the corresponding relation among the line cycle length line _ length _ tubulan, the exposure start time pos _ start _ expose, the initial jump edge position pos _ default and the default line cycle length line _ default of the drive signal corresponding to the jump edge position of the drive signal as follows:
setting the line period corresponding to the edge position pos _ sense of the transfer and control driving signal sensitive area as follows:
Setting the line period at the center pos _ sense _ center of the transfer and control driving signal sensitive area to be:
Step two, outputting a hard line period by adopting a controller simulation device, and designing line period combinations of nine combination modes for the current period as the input of an imaging unit according to the corresponding relation set in the step one; the nine combination modes are as follows:
(1) Four identical current line periods;
(2) Current line period-1, current line period;
(3) Current line period, current line period-1, current line period;
(4) Current line period, current line period-1, current line period;
(5) Current line period, current line period-1;
(6) Current line period +1, current line period;
(7) Current line period, current line period +1, current line period;
(8) Current line period, current line period +1, current line period;
(9) Current line period, current line period +1;
and thirdly, judging the image gray scale of the image output by the imaging unit through a quick vision device, and judging that an image meeting the requirement is output when the deviation of the image gray scale exceeds 50DN, wherein DN is the gray scale.
2. The simulation verification system of the simulation verification method of uniform charge transfer dynamic row cycle imaging according to claim 1, characterized in that: the system comprises a controller simulation device, an imaging unit and a quick-look device;
the controller simulation equipment outputs a hard-line periodic signal to the imaging unit, and the parallel image output by the imaging unit is subjected to image gray level judgment through the quick-vision equipment, so that the simulation verification of the image is realized.
3. The simulation verification system of claim 2, wherein:
the imaging unit comprises a driving and level conversion circuit, a detector, a 2711 module and an imaging FPGA; the imaging FPGA comprises a line period processing module, a time sequence driving module and a data training and integrating module;
an asynchronous system is arranged between the imaging controller and the imaging unit, and the imaging controller outputs a main backup line periodic signal, a backup line periodic signal and a main backup identification signal to the camera imaging unit; a line period processing module in the camera imaging unit selects and uses a main backup line period signal or a backup line period signal to generate a panchromatic line starting pulse, a multispectral line starting pulse, panchromatic line period length data and multispectral line period length data required by a time sequence driving module according to the received main backup identification signal; the transfer and control level signal output by the time sequence driving module is converted into a transfer and control driving signal through a driving and level conversion circuit and then is sent to a detector;
the serial image data output by the detector is output to the 2711 module through the data training and integrating module and is finally output through the data transmission interface.
4. The simulation verification system of claim 3, wherein:
setting the cycle length of the panchromatic row starting pulse to be the same as the panchromatic row cycle signal length, setting the panchromatic row cycle signal length to be the same as the main backup row cycle signal length or the backup row cycle signal length selected according to the main backup identification signal, setting the width of the panchromatic row starting pulse to be equal to or more than 1 pixel clock cycle, and setting the rising edge position time of the panchromatic row starting pulse to lag the panchromatic row cycle length data updating time;
the multispectral row starting pulse has the same period length as the multispectral row periodic signal length, and the multispectral row periodic signal length is the same as the accumulated value of the four adjacent main backup row periodic signal lengths or the accumulated value of the four adjacent backup row periodic signal lengths selected according to the main backup identification signals;
the width of the multispectral row starting pulse is equal to or more than 1 pixel clock period, and the rising edge position time lags behind the multispectral row period length data updating time;
the lag time is greater than or equal to 1 pixel clock cycle and less than 20 pixel clock cycles.
5. The simulation verification system of claim 4, wherein:
multispectral line-periodic signal length B1There are two values; when the length of the panchromatic line periodic signal is a constant value, the length of the multispectral line periodic signal is B1=4p; multispectral line periodic signal length B when panchromatic line periodic signal length is different value1＝p1+p2+p3+p4；
p1、p2、p3、p4Respectively, the lengths of the four adjacent panchromatic line periodic signals, and p is the length of the constant panchromatic line periodic signal.
6. The simulation verification system of claim 3, wherein:
the panchromatic row starting pulse and the multispectral row starting pulse respectively reset a panchromatic time sequence counter and a multispectral time sequence counter in the time sequence driving module; the jumping edge updating time of each panchromatic driving control signal is the time when the count value of the panchromatic time sequence counter is 0; and the updating time of the jumping edge of each multispectral driving control signal is the time when the counting value of the multispectral time sequence counter is 0.
7. The simulation verification system of claim 3, wherein:
the drive and level conversion circuitThe jump edge position of each output transfer and control drive signal is determined according to the length p of the currently input panchromatic row periodic signal and the length B of the multispectral row periodic signal1The position area of the jump edge available for the panchromatic transfer and control drive signal is (3,p), and the position area of the jump edge available for the multispectral transfer and control drive signal is (3,B)1-3); when the calculated jump edge position of the panchromatic image is 0-3, setting the jump edge position to be 3; when the jump edge position of the panchromatic image obtained through calculation is in the range from p-3 to p-1, setting the jump edge position as p-3;
when the position of the jump edge of the multispectral transfer and control driving signal obtained by calculation is between 0 and 3, setting the position of the jump edge to be 3; when the position of the jump edge of the multispectral transfer and control driving signal obtained by calculation is in B1-3～B1When the position of the jump edge is 1, the position of the jump edge is set to be B1-3。
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