CN113347283A - Method and system for distributing node addresses - Google Patents
Method and system for distributing node addresses Download PDFInfo
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- CN113347283A CN113347283A CN202110618333.0A CN202110618333A CN113347283A CN 113347283 A CN113347283 A CN 113347283A CN 202110618333 A CN202110618333 A CN 202110618333A CN 113347283 A CN113347283 A CN 113347283A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/50—Address allocation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
Abstract
The embodiment of the invention discloses a method for distributing node addresses, wherein at least one main node and a plurality of slave nodes are cascaded between an initial module and a finish module, and the method comprises the following steps: the initial module transmits the signal instruction to each node in sequence through a sequential signal line; after receiving the signal instruction, the node generates an ID address of the node and sends the ID address to a bus, and meanwhile, the ending module records the time for the node to receive the signal instruction; and after receiving the signal instruction, the ending module feeds the ID address of each slave node back to the corresponding master node, so that the master node performs address allocation according to the ID address of each slave node. The embodiment of the invention also discloses a system for distributing the node address. The invention can realize the automatic distribution of the ID address of the equipment through the sequential transmission of the signal instructions.
Description
Technical Field
The invention relates to the technical field of industrial control, in particular to a method and a system for distributing node addresses.
Background
In the field of industrial control, various modularized systems are mainly formed by combining a main control node and a plurality of function expansion modules, and the modules need to be addressed due to the fact that addressing communication is needed between the main control node and the modules. In the related art, the module address is usually set by a dial switch or assigned by a software configuration tool. However, these methods are too cumbersome and prone to error.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a method and a system for allocating node addresses, which can realize automatic allocation of device ID addresses through sequential transmission of signal commands.
The embodiment of the invention provides a method for distributing node addresses, wherein at least one main node and a plurality of slave nodes are cascaded between an initial module and a finishing module, and the method comprises the following steps:
the initial module transmits the signal instruction to each node in sequence through a sequential signal line;
after receiving the signal instruction, the node generates an ID address of the node and sends the ID address to a bus, and meanwhile, the ending module records the time for the node to receive the signal instruction;
and after receiving the signal instruction, the ending module feeds the ID address of each slave node back to the corresponding master node, so that the master node performs address allocation according to the ID address of each slave node.
As a further improvement of the invention, a plurality of function module groups are cascaded between the initial module and the ending module, each function module group comprises a main node and a plurality of slave nodes cascaded with the main node, each function module group communicates through different buses,
the method further comprises the following steps:
after the signal instruction is transmitted among all nodes of the previous functional module group in sequence, the signal instruction is transmitted to the next functional module group, so that the signal instruction is transmitted among all nodes of the next functional module group in sequence.
As a further improvement of the present invention, two adjacent nodes are electrically connected through a sequential signal line, and the signal command is transmitted from the previous node to the next node through the sequential signal line between the two adjacent nodes;
the initial module is electrically connected with a first node through a sequential signal line, and the signal instruction is transmitted from the initial module to the first node through the sequential signal line between the initial module and the first node;
the last node and the ending module are electrically connected through a sequential signal line, and the signal instruction is transmitted from the last node to the ending module through the sequential signal line between the last node and the ending module.
As a further improvement of the present invention, the initial module transmits the signaling instruction to a first node in a first functional module group, and the ending module feeds back the ID address of each slave node in each functional module group to the master node in the functional module group.
As a further improvement of the present invention, the master node sequentially assigns addresses to the slave nodes in the time sequence in which the slave nodes receive the signal instruction.
The embodiment of the invention also provides a system for distributing the node address, an initial module, an end module and
at least one master node and a plurality of slave nodes cascaded between the initiating module and the ending module;
the initial module is used for sequentially transmitting signal instructions to each node through a sequential signal line;
the slave node is used for generating an ID address of the slave node and sending the ID address to a bus after receiving the signal instruction;
the master node is used for generating an ID address of the master node and sending the ID address to a bus after receiving the signal instruction, and receiving the ID addresses of the slave nodes fed back by the ending module so as to carry out address allocation according to the ID addresses of the slave nodes;
and the ending module is used for recording the time of each node for receiving the signal instruction and feeding back the ID address of each slave node to the corresponding master node after receiving the signal instruction.
As a further improvement of the invention, a plurality of function module groups are cascaded between the initial module and the ending module, each function module group comprises a main node and a plurality of slave nodes cascaded with the main node, each function module group communicates through different buses,
after the signal instruction is transmitted among all nodes of the previous functional module group in sequence, the signal instruction is transmitted to the next functional module group, so that the signal instruction is transmitted among all nodes of the next functional module group in sequence.
As a further improvement of the present invention, the system further comprises:
the sequential signal line is connected between two adjacent nodes and is used for realizing the electrical connection between the two adjacent nodes and transmitting the signal instruction from the previous node to the next node;
a sequential signal line connected between the initial module and a first node for effecting electrical connection between the initial module and the first node, the sequential signal line transmitting the signal command from the initial module to the first node;
a sequential signal line connected between a last node and the end module for effecting electrical connection between the last node and the end module, the sequential signal line transmitting the signal instructions from the last node to the end module.
As a further improvement of the present invention, the initial module transmits the signaling instruction to a first node in a first functional module group, and the ending module feeds back the ID address of each slave node in each functional module group to the master node in the functional module group.
As a further improvement of the present invention, the master node sequentially assigns addresses to the slave nodes in the time sequence in which the slave nodes receive the signal instruction.
Embodiments of the present invention also provide an electronic device, which includes a memory and a processor, and is characterized in that the memory is configured to store one or more computer instructions, where the one or more computer instructions are executed by the processor to implement the method.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the method.
The invention has the beneficial effects that:
through the sequential transmission of the signal instructions, the ID address sequential production and the corresponding ID recording of each node can be completed, the physical sequential arrangement and the automatic ID address allocation of equipment are realized, and the reliability of the whole system is enhanced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic flowchart of a method for allocating node addresses according to an exemplary embodiment of the present invention;
fig. 2 is a schematic diagram of a node address allocation system according to an exemplary embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, in the description of the present invention, the terms used are for illustrative purposes only and are not intended to limit the scope of the present invention. The terms "comprises" and/or "comprising" are used to specify the presence of stated elements, steps, operations, and/or components, but do not preclude the presence or addition of one or more other elements, steps, operations, and/or components. The terms "first," "second," and the like may be used to describe various elements, not necessarily order, and not necessarily limit the elements. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified. These terms are only used to distinguish one element from another. These and/or other aspects will become apparent to those of ordinary skill in the art in view of the following drawings, and the description of the embodiments of the present invention will be more readily understood by those of ordinary skill in the art. The drawings are only for purposes of illustrating the described embodiments of the invention. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated in the present application may be employed without departing from the principles described in the present application.
In the method for allocating node addresses according to the embodiment of the present invention, at least one master node and a plurality of slave nodes are cascaded between an initial module and a final module, as shown in fig. 1, the method includes:
s1, the initial module transmits the signal instruction to each node in turn through a sequential signal line;
s2, after receiving the signal instruction, the node generates an ID address of the node and sends the ID address to a bus, and meanwhile, the ending module records the time for the node to receive the signal instruction;
and S3, after receiving the signal instruction, the ending module feeds back the ID address of each slave node to the corresponding master node, so that the master node performs address allocation according to the ID address of each slave node.
The invention relates to a method for automatically distributing node addresses of a master device and a plurality of slave devices in the communication process of industrial equipment, wherein each node device can be arranged at each physical position according to the requirement of an industrial production line, and the node devices can be randomly arranged at each physical position. It will be appreciated that the method of the present invention is for use in a bus network having at least one master node and a plurality of slave nodes cascaded with the at least one master node. Each node needs to support a bus protocol. The master node is a master node, that is, a master device, and the slave node is a function extension module, that is, a slave device. The method of the invention sequentially transmits signal instructions (sequential signals) to each node through a sequential signal line to form a closed loop, each node can transmit the signal instructions according to a cascade sequence, and the ID address of each node (equipment) is produced by sequential information and is hung on a bus to be accessed, thereby realizing the dynamic automatic allocation of the address of the function expansion module. No matter how the nodes (devices) increase or decrease and the arrangement sequence changes, through the sequential transmission of signal instructions, the ID address sequential production and the corresponding ID recording of each node can be completed. The method of the invention can realize the physical order arrangement and the automatic ID address allocation of the equipment, is convenient for maintaining each node and enhances the reliability of the whole system.
An initial module and an end module are also arranged in the bus network to realize closed-loop transmission of signal instructions, and the initial module and the end module also need to support a bus protocol. The initial module can realize power supply to each node besides realizing transmission of signal instructions. In this case, the initial module may be understood as a power supply module with signaling function. And after all the nodes are powered on, transmitting a signal instruction to the first node through the initial module. And the signal instruction is sent to the ending module through the last node, and the ending module can judge that the transmission of the signal instruction is ended after receiving the signal instruction. The ending module further needs to record the time of each node receiving the signal instruction and the ID address of each node in the signal instruction transmission process, so that after the signal instruction transmission is determined to be ended, the ID address of each slave node can be fed back (since the master node itself has an ID address recording function, the ID address of each slave node is fed back), and after the master node receives the feedback information, the master node can realize address allocation to each slave node according to each ID address. And the ending module feeds back the signal instruction to the master node when feeding back the ID address of the slave node.
When a signal instruction is transmitted, the signal instruction is firstly sent to a first node from an initial module, the first node hangs an ID address of the first node on a bus after receiving the signal instruction, the first node sends the signal instruction to a second node through a sequential signal line connected with the first node, the second node hangs the ID address of the second node on the bus after receiving the signal instruction, the second node sends the signal instruction to a third node through the sequential signal line connected with the second node, the third node hangs the ID address of the third node on the bus after receiving the signal instruction, the third node repeatedly executes the process and then transmits the signal instruction to a next node until the signal instruction is transmitted to an end module. It is to be understood that the first node, the second node, the third node, and the like may be a master node or a slave node in the bus network. The order of transmission of the signal commands between the nodes may be determined according to the order of concatenation of the nodes.
The bus is a CAN bus, for example, and communication among all nodes is realized. CAN is a serial communication protocol that is ISO international standardized. CAN is a serial communication network that effectively supports distributed control or real-time control. Compared with a plurality of distributed control systems constructed by RS-485 based on R lines, the distributed control system based on the CAN bus has the advantages of strong real-time data communication among nodes of the network and shorter development period. Each node, the initial module and the ending module in the CAN bus network need to support a CAN bus protocol, but it CAN be understood that the invention CAN be applied to other bus networks as well, and is not limited to the CAN bus network, and the invention does not specifically limit the form of the bus.
In an alternative embodiment, a plurality of functional module groups are cascaded between the initial module and the ending module, each functional module group comprises a main node and a plurality of slave nodes cascaded with the main node, each functional module group communicates through different buses,
the method further comprises the following steps:
after the signal instruction is transmitted among all nodes of the previous functional module group in sequence, the signal instruction is transmitted to the next functional module group, so that the signal instruction is transmitted among all nodes of the next functional module group in sequence.
It will be appreciated that in an industrial control system, there may be a plurality of master nodes, each master node cascading a plurality of slave nodes, a master node and its cascaded plurality of slave nodes may form a functional module group, and the plurality of nodes (including the master node and the slave nodes) in each functional module group may communicate using a bus, for example, a first functional module group may communicate using a first bus, a second functional module group may communicate using a second bus, and so on, different functional module groups may use different buses. Here, the different buses are not the same bus, and may be different types of buses, or may be the same type of buses, for example, CAN buses are all used. It is understood that, when there are a plurality of functional module groups, both ends of the bus of each functional module group are connected to the initial module and the ending module. And the signal instructions are transmitted in sequence in all the nodes in the last functional module group according to the cascade sequence, then transmitted in sequence in all the nodes in the next functional module group in the cascade sequence, and so on until the transmission of the signal instructions in all the functional module groups is completed.
In an alternative embodiment, the initiating module transmits the signaling instruction to a first node in a first functional module group, and the terminating module feeds back the ID address of each slave node in each functional module group to the master node in the functional module group.
It will also be appreciated that where there are multiple groups of functional modules, the master node in each group of functional modules is arranged to assign addresses to the various slave nodes in that group of functional modules. After all the nodes are powered on, the initial module transmits signal instructions to a first node in the first functional module group, the signal instructions are sequentially transmitted among all the nodes in the first functional module group, and are sequentially transmitted … among all the nodes in the second functional module group until the signal instructions are transmitted to the ending module, at this time, the ending module feeds back the ID addresses of all the slave nodes in each functional module group to the master node in the functional module group, and the master node realizes address allocation of all the slave nodes in the functional module group.
In an alternative embodiment, two adjacent nodes are electrically connected through a sequential signal line, and the signal command is transmitted from the previous node to the next node through the sequential signal line between the two adjacent nodes;
the initial module is electrically connected with a first node through a sequential signal line, and the signal instruction is transmitted from the initial module to the first node through the sequential signal line between the initial module and the first node;
the last node and the ending module are electrically connected through a sequential signal line, and the signal instruction is transmitted from the last node to the ending module through the sequential signal line between the last node and the ending module.
It can be understood that the nodes in each functional module group are electrically connected through a sequential signal line, and the nodes cascaded between adjacent functional module groups are also electrically connected through a sequential signal line. The initial module is electrically connected with the first node in the bus network through a sequential signal line, and the ending module is electrically connected with the last node in the bus network through a sequential signal line. After the electrical connection of each module and each node is completed through the sequential signal line, the sequential transmission of the signal instructions can be realized through the sequential signal line.
For example, as shown in fig. 2, the Power module as the initial module and the End module as the End module support a bus protocol, such as a CAN bus protocol. The first bus CANa and the second bus CANb are connected to the Power module and the End module at two ends, respectively. The bus network comprises two functional module groups, a first functional module group and a second functional module group. Module CANa is a slave NODE in the first functional Module group, BUS NODE is a master NODE in the first functional Module group, and all NODEs in the first functional Module group adopt the first BUS CANa for communication. The Module CANb is a slave node in the second functional Module group, a master node in the second functional Module group is not shown in the figure, and all nodes in the second functional Module group adopt the second bus CANb for communication. The first Module CANa and the second Module CANa in the first functional Module group are electrically connected through a SEQUENCE signal line, the second Module CANa and the third Module CANa are electrically connected through a SEQUENCE signal line, and so on, the last Module CANa and the first Module CANb in the second functional Module group are electrically connected through a SEQUENCE signal line, the first Module CANb and the second Module CANb in the second functional Module group are electrically connected through a SEQUENCE signal line, and so on, the last CANb is electrically connected with the main node in the second functional Module group through a SEQUENCE signal line.
The transmission process of the signal instruction comprises the following steps: the Power Module sends a signal instruction to a first Module CANa in the first functional Module group through a SEQUENCE connected with the Power Module, the first Module CANa receives the signal instruction and then hangs the ID address on the first BUS CANa, the first Module CANa sends the signal instruction to a second Module CANa through the SEQUENCE connected with the first Module CANa, the second Module CANa receives the signal instruction and then hangs the ID address on the first BUS CANa, the second Module CANa sends the signal instruction to a third Module CANa through the SEQUENCE connected with the second Module CANa, and the rest is repeated until the signal instruction is sent to a BUS NODE, the BUS NODE receives the signal instruction and then hangs the ID address on the first BUS CANa, the first Module CANb receives the signal instruction and then sends the signal instruction to the first Module CANb in the second functional Module, the first Module CANb receives the signal instruction and then hangs the ID address on the second BUS CANb, and the first Module CANb sends the signal instruction to the second Module CANb through the SEQUENCE connected with the second Module CANb, and analogizing in SEQUENCE until the signal instruction is sent to the main NODE in the second functional module, sending the signal instruction to the End module by the main NODE in the second functional module group through the SEQUENCE connected with the main NODE, and feeding the signal instruction and the ID address of each NODE back to the BUS NODE and the main NODE in the second functional module by the End module.
In an optional implementation manner, the master node sequentially assigns addresses to the slave nodes in a time sequence in which the slave nodes receive the signal instruction.
It can be understood that, the order of cascading of each node, that is, the order in which the node generates the ID address, that is, the time order in which the node receives the signal instruction, is recorded in the ending module, and when the ending module feeds back the time of receiving the signal instruction, the ending module may feed back the ID address of each slave node and the time of receiving the signal instruction to the corresponding master node together, and the master node may allocate an address to each slave node according to the fed-back time order, so that the process in which the master node allocates addresses according to the cascading order of the slave nodes is implemented. It can also be understood that, when there are multiple functional module groups, each master node allocates addresses to each slave node in the functional module group in which it is located according to the cascade order.
For example, as shown in fig. 2, the ending Module feeds back the ID addresses of the first Module CANa and the second Module CANa … in the first functional Module group to the BUS NODE, and simultaneously feeds back the ID addresses of the first Module canab and the second Module canab … in the second functional Module group to the corresponding master NODE. And the BUS NODE respectively allocates addresses for the first Module CANa and the second Module CANa according to the cascade sequence of all slave NODEs in the first functional Module group. And the main node in the second functional Module group respectively allocates addresses for the first Module CANb and the second Module CANb according to the cascade sequence of all the slave nodes in the functional Module group.
The system for distributing node addresses in the embodiment of the invention comprises:
an initial module and an end module, and
at least one master node and a plurality of slave nodes cascaded between the initiating module and the ending module;
the initial module is used for sequentially transmitting signal instructions to each node through a sequential signal line;
the slave node is used for generating an ID address of the slave node and sending the ID address to a bus after receiving the signal instruction;
the master node is used for generating an ID address of the master node and sending the ID address to a bus after receiving the signal instruction, and receiving the ID addresses of the slave nodes fed back by the ending module so as to carry out address allocation according to the ID addresses of the slave nodes;
and the ending module is used for recording the time of each node for receiving the signal instruction and feeding back the ID address of each slave node to the corresponding master node after receiving the signal instruction.
Each node of the invention is, for example, a valve body pull-in and pull-out device controlled by an industrial bus, and each node can be arranged at each physical position according to the requirements of an industrial production line. The master node is a master node, that is, a master device, and the slave node is a function extension module, that is, a slave device. No matter how the nodes (devices) in the system increase or decrease and the arrangement sequence changes, through the sequential transmission of signal instructions, the sequential production of the ID addresses of all the nodes and the corresponding ID recording can be completed.
In an alternative embodiment, a plurality of functional module groups are cascaded between the initial module and the ending module, each functional module group comprises a main node and a plurality of slave nodes cascaded with the main node, each functional module group communicates through different buses,
after the signal instruction is transmitted among all nodes of the previous functional module group in sequence, the signal instruction is transmitted to the next functional module group, so that the signal instruction is transmitted among all nodes of the next functional module group in sequence.
It can be understood that, in the system, a master node and multiple cascaded slave nodes thereof may form a function module group, multiple nodes (including the master node and the slave nodes) in each function module group communicate using a bus, and different function module groups may use different buses, may use different types of buses, and may also use the same type of bus, so as to implement a multi-bus (multi-protocol) control node device.
In an alternative embodiment, the system further comprises:
the sequential signal line is connected between two adjacent nodes and is used for realizing the electrical connection between the two adjacent nodes and transmitting the signal instruction from the previous node to the next node;
a sequential signal line connected between the initial module and a first node for effecting electrical connection between the initial module and the first node, the sequential signal line transmitting the signal command from the initial module to the first node;
a sequential signal line connected between a last node and the end module for effecting electrical connection between the last node and the end module, the sequential signal line transmitting the signal instructions from the last node to the end module.
In an alternative embodiment, the initiating module transmits the signaling instruction to a first node in a first functional module group, and the terminating module feeds back the ID address of each slave node in each functional module group to the master node in the functional module group.
For example, as shown in fig. 2, the Power module as the initial module and the End module as the End module support a bus protocol, such as a CAN bus protocol. The first bus CANa and the second bus CANb are connected to the Power module and the End module at two ends, respectively. The bus network comprises two functional module groups, a first functional module group and a second functional module group. Module CANa is a slave NODE in the first functional Module group, BUS NODE is a master NODE in the first functional Module group, and all NODEs in the first functional Module group adopt the first BUS CANa for communication. The Module CANb is a slave node in the second functional Module group, a master node in the second functional Module group is not shown in the figure, and all nodes in the second functional Module group adopt the second bus CANb for communication. The first Module CANa and the second Module CANa in the first functional Module group are electrically connected through a SEQUENCE signal line, the second Module CANa and the third Module CANa are electrically connected through a SEQUENCE signal line, and so on, the last Module CANa and the first Module CANb in the second functional Module group are electrically connected through a SEQUENCE signal line, the first Module CANb and the second Module CANb in the second functional Module group are electrically connected through a SEQUENCE signal line, and so on, the last CANb is electrically connected with the main node in the second functional Module group through a SEQUENCE signal line.
The transmission process of the signal instruction comprises the following steps: the Power Module sends a signal instruction to a first Module CANa in the first functional Module group through a SEQUENCE connected with the Power Module, the first Module CANa receives the signal instruction and then hangs the ID address on the first BUS CANa, the first Module CANa sends the signal instruction to a second Module CANa through the SEQUENCE connected with the first Module CANa, the second Module CANa receives the signal instruction and then hangs the ID address on the first BUS CANa, the second Module CANa sends the signal instruction to a third Module CANa through the SEQUENCE connected with the second Module CANa, and the rest is repeated until the signal instruction is sent to a BUS NODE, the BUS NODE receives the signal instruction and then hangs the ID address on the first BUS CANa, the first Module CANb receives the signal instruction and then sends the signal instruction to the first Module CANb in the second functional Module, the first Module CANb receives the signal instruction and then hangs the ID address on the second BUS CANb, and the first Module CANb sends the signal instruction to the second Module CANb through the SEQUENCE connected with the second Module CANb, and analogizing in SEQUENCE until the signal instruction is sent to the main NODE in the second functional module, sending the signal instruction to the End module by the main NODE in the second functional module group through the SEQUENCE connected with the main NODE, and feeding the signal instruction and the ID address of each NODE back to the BUS NODE and the main NODE in the second functional module by the End module.
In an alternative embodiment, the master node sequentially assigns addresses to the slave nodes in the time sequence in which the slave nodes receive the signal instruction.
For example, as shown in fig. 2, the ending Module feeds back the ID addresses of the first Module CANa and the second Module CANa … in the first functional Module group to the BUS NODE, and simultaneously feeds back the ID addresses of the first Module canab and the second Module canab … in the second functional Module group to the corresponding master NODE. And the BUS NODE respectively allocates addresses for the first Module CANa and the second Module CANa according to the cascade sequence of all slave NODEs in the first functional Module group. And the main node in the second functional Module group respectively allocates addresses for the first Module CANb and the second Module CANb according to the cascade sequence of all the slave nodes in the functional Module group.
The disclosure also relates to an electronic device comprising a server, a terminal and the like. The electronic device includes: at least one processor; a memory communicatively coupled to the at least one processor; and a communication component communicatively coupled to the storage medium, the communication component receiving and transmitting data under control of the processor; wherein the memory stores instructions executable by the at least one processor to implement the method of the above embodiments.
In an alternative embodiment, the memory is used as a non-volatile computer-readable storage medium for storing non-volatile software programs, non-volatile computer-executable programs, and modules. The processor executes various functional applications of the device and data processing, i.e., implements the method, by executing nonvolatile software programs, instructions, and modules stored in the memory.
The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store a list of options, etc. Further, the memory may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and such remote memory may be connected to the external device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more modules are stored in the memory and, when executed by the one or more processors, perform the methods of any of the method embodiments described above.
The product can execute the method provided by the embodiment of the application, has corresponding functional modules and beneficial effects of the execution method, and can refer to the method provided by the embodiment of the application without detailed technical details in the embodiment.
The present disclosure also relates to a computer-readable storage medium for storing a computer-readable program for causing a computer to perform some or all of the above-described method embodiments.
That is, as can be understood by those skilled in the art, all or part of the steps in the method for implementing the embodiments described above may be implemented by a program instructing related hardware, where the program is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Furthermore, those of ordinary skill in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
It will be understood by those skilled in the art that while the present invention has been described with reference to exemplary embodiments, various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (12)
1. A method for allocating node addresses, wherein at least one master node and a plurality of slave nodes are cascaded between an initial module and a final module, the method comprising:
the initial module transmits the signal instruction to each node in sequence through a sequential signal line;
after receiving the signal instruction, the node generates an ID address of the node and sends the ID address to a bus, and meanwhile, the ending module records the time for the node to receive the signal instruction;
and after receiving the signal instruction, the ending module feeds the ID address of each slave node back to the corresponding master node, so that the master node performs address allocation according to the ID address of each slave node.
2. The method of claim 1, wherein a plurality of functional module groups are cascaded between the initiating module and the terminating module, each functional module group comprising a master node and a plurality of slave nodes cascaded with the master node, each functional module group communicating over a different bus,
the method further comprises the following steps:
after the signal instruction is transmitted among all nodes of the previous functional module group in sequence, the signal instruction is transmitted to the next functional module group, so that the signal instruction is transmitted among all nodes of the next functional module group in sequence.
3. The method according to claim 1 or 2, wherein two adjacent nodes are electrically connected through a sequential signal line, and the signal instruction is transmitted from the previous node to the next node through the sequential signal line between the two adjacent nodes;
the initial module is electrically connected with a first node through a sequential signal line, and the signal instruction is transmitted from the initial module to the first node through the sequential signal line between the initial module and the first node;
the last node and the ending module are electrically connected through a sequential signal line, and the signal instruction is transmitted from the last node to the ending module through the sequential signal line between the last node and the ending module.
4. The method of claim 2, wherein the initiating module transmits the signaling instruction to a first node in a first group of functional modules, and the terminating module feeds back the ID address of the respective slave node in each group of functional modules to the master node in the group of functional modules.
5. The method of claim 1, wherein the master node assigns addresses to the slave nodes in sequence in accordance with a time sequence in which the signal instructions are received by the slave nodes.
6. A system for assigning addresses of nodes, the system comprising:
an initial module and an end module, and
at least one master node and a plurality of slave nodes cascaded between the initiating module and the ending module;
the initial module is used for sequentially transmitting signal instructions to each node through a sequential signal line;
the slave node is used for generating an ID address of the slave node and sending the ID address to a bus after receiving the signal instruction;
the master node is used for generating an ID address of the master node and sending the ID address to a bus after receiving the signal instruction, and receiving the ID addresses of the slave nodes fed back by the ending module so as to carry out address allocation according to the ID addresses of the slave nodes;
and the ending module is used for recording the time of each node for receiving the signal instruction and feeding back the ID address of each slave node to the corresponding master node after receiving the signal instruction.
7. The system of claim 6, wherein a plurality of functional module groups are cascaded between the initiation module and the termination module, each functional module group comprising a master node and a plurality of slave nodes cascaded with the master node, each functional module group communicating over a different bus,
after the signal instruction is transmitted among all nodes of the previous functional module group in sequence, the signal instruction is transmitted to the next functional module group, so that the signal instruction is transmitted among all nodes of the next functional module group in sequence.
8. The system of claim 6 or 7, wherein the system further comprises:
the sequential signal line is connected between two adjacent nodes and is used for realizing the electrical connection between the two adjacent nodes and transmitting the signal instruction from the previous node to the next node;
a sequential signal line connected between the initial module and a first node for effecting electrical connection between the initial module and the first node, the sequential signal line transmitting the signal command from the initial module to the first node;
a sequential signal line connected between a last node and the end module for effecting electrical connection between the last node and the end module, the sequential signal line transmitting the signal instructions from the last node to the end module.
9. The system of claim 7, wherein the initiating module transmits the signaling instructions to a first node in a first group of functional modules, and the terminating module feeds back the ID address of the respective slave node in each group of functional modules to the master node in that group of functional modules.
10. The system of claim 6, wherein the master node assigns addresses to the slave nodes in sequence in accordance with a time sequence in which the slave nodes receive the signal instructions.
11. An electronic device comprising a memory and a processor, wherein the memory is configured to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method of any of claims 1-5.
12. A computer-readable storage medium, on which a computer program is stored, the computer program being executable by a processor for implementing the method according to any of claims 1-5.
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