CN113346961A

CN113346961A - Duty ratio control method, device, circuit and equipment applied to physical layer

Info

Publication number: CN113346961A
Application number: CN202110875125.9A
Authority: CN
Inventors: 霍文驹; 董宗宇
Original assignee: Hangzhou Youzhilian Technology Co ltd
Current assignee: Hangzhou Youzhilian Technology Co ltd
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2021-09-03
Anticipated expiration: 2041-07-30
Also published as: CN113346961B

Abstract

The embodiment of the invention discloses a duty ratio control method, a device, a circuit and equipment applied to a physical layer; the method can comprise the following steps: the duty ratio controller reads the coded data used for indicating whether the pulse exists from the data buffer; the duty cycle controller generates a control signal for controlling a power mixer (PA) according to the encoded data to control the PA to be turned on when a pulse exists and to be turned off when no pulse exists.

Description

Duty ratio control method, device, circuit and equipment applied to physical layer

Technical Field

The embodiment of the invention relates to the technical field of integrated circuit design, in particular to a duty ratio control method, a device, a circuit and equipment applied to a physical layer.

Background

In order to meet the requirement of reducing power consumption of the internet of things or mobile devices, a modulation mode of a duty cycle (duty cycle) is usually adopted to avoid waste of power consumption caused by long-time operation of such devices.

Currently, a scheme for controlling a duty ratio is generally implemented by using a software program or a protocol layer, specifically, the software control scheme is simple to implement but has a large delay, and the protocol layer also has such problems, so that the scheme for controlling the duty ratio by using the software program or the protocol layer can only control the duty ratio between an overall communication system in equipment and a large component module in the system at present, and cannot achieve finer adjustment control, thereby still causing waste of power consumption.

Disclosure of Invention

In view of the above, embodiments of the present invention are to provide a duty cycle control method, apparatus, circuit and device applied to a physical layer; by implementing fine control of the duty cycle at the physical layer, power consumption is reduced.

The technical scheme of the embodiment of the invention is realized as follows:

in a first aspect, an embodiment of the present invention provides a duty cycle control method applied to a physical layer, where the method includes:

the duty ratio controller reads the coded data used for indicating whether the pulse exists from the data buffer;

the duty cycle controller generates a control signal for controlling a power mixer (PA) according to the encoded data to control the PA to be turned on when a pulse exists and to be turned off when no pulse exists.

In a second aspect, an embodiment of the present invention provides a duty cycle controller, including: a reading section and a generating section; wherein the reading section is configured to read encoded data indicating the presence or absence of a pulse from a data buffer; the generating section is configured to generate a control signal for controlling a power mixer (PA) according to the encoded data to control the PA to be turned on when pulsed and to be turned off when not pulsed.

In a third aspect, an embodiment of the present invention provides a duty cycle control circuit applied to a physical layer, where the duty cycle control circuit includes: a data buffer, a power mixer and the duty cycle controller of the second aspect.

In a fourth aspect, an embodiment of the present invention provides a transmitting device, where a transmitting front end of the transmitting device includes the duty cycle control circuit applied to the physical layer according to the third aspect.

The embodiment of the invention provides a duty ratio control method, a device, a circuit and equipment applied to a physical layer; the duty ratio controller is used for controlling the power mixer PA to be switched on and off according to whether the coded data have pulses or not, so that the duty ratio control in the data frame is realized.

Drawings

Fig. 1 is a schematic diagram of an exemplary network environment according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of an exemplary communication system architecture according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a transmitting front end according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a UWB pulsed radio frequency signal according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of another transmit front end according to an embodiment of the present invention.

Fig. 6 is a flowchart illustrating a duty cycle control method applied to a physical layer according to an embodiment of the present invention.

Fig. 7 is a timing diagram of a generation signal according to an embodiment of the present invention.

Fig. 8 is a schematic composition diagram of a duty cycle controller according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Referring to fig. 1, which shows a schematic diagram of a network environment 100 that can be applied to the technical solutions set forth in the embodiments of the present invention, as an illustrative example and not by way of limitation, taking a wireless communication device 102 as an example, the wireless communication device 102 can wirelessly communicate with other wireless communication devices in a short range of the wireless communication device 102 in the network environment 100, such as a printer 104, a Personal Digital Assistant (PDA) 106, a camera 108, and an access point 110, and can also wirelessly communicate with a speaker system 112 communicatively coupled to the access point 110 and a wireless network 114 through the access point 110. All wireless communication devices in network environment 100 may communicate wirelessly using any suitable wireless standard, such as 802.11x or Ultra Wide Band (UWB).

It should be noted that in the network environment 100 shown in fig. 1, the term "wireless communication device" may also be referred to by those skilled in the art as a Mobile Station (MS), a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless device, a remote device, a mobile subscriber station, an Access Terminal (AT), a mobile terminal, a wireless terminal, a remote terminal, a handset, a terminal, a user agent, a mobile client, a client, or some other suitable terminology; also, the wireless communication device need not necessarily have mobile capabilities in some examples, but may be stationary; further, a wireless communication device may include several hardware structural components sized, shaped, and arranged to facilitate wireless communication, such components may include antennas, antenna arrays, Radio Frequency (RF) chains, amplifiers, one or more processors, and so forth, electrically coupled to one another. Additionally, in some non-limiting examples, other non-limiting examples of wireless communication devices include mobile devices, cellular (cell) phones, smart phones, Session Initiation Protocol (SIP) phones, laptops, Personal Computers (PCs), notebooks, netbooks, smartbooks, tablets, and a wide variety of embedded systems, e.g., corresponding to the "internet of things" (IoT), in addition to the printers, PDAs, cameras, access points, speaker systems, and wireless networks described above. Additionally, the wireless communication device may be an automobile or other transportation vehicle, a remote sensor or actuator, a robot or robotic device, a satellite radio, a Global Positioning System (GPS) device, an object tracking device, a drone, a multi-axis aircraft, a quadcopter, a remote control device, a consumer and/or wearable device (such as glasses), a wearable camera, a virtual reality device, a smart watch, a health or fitness tracker, a digital audio player (e.g., MP3 player), a camera, a game console, and so forth. Additionally, the wireless communication device may also be a digital home or intelligent home device, such as a home audio, video, and/or multimedia device, an appliance, a vending machine, an intelligent lighting device, a home security system, a smart meter, and so forth. Additionally, the wireless communication device may also be a smart energy device, a security device, a solar panel or array, a municipal infrastructure device (e.g., a smart grid) that controls power, lighting, water, etc.; industrial automation and enterprise equipment; a logistics controller; agricultural equipment; military defense equipment, vehicles, airplanes, boats, weapons, and the like.

With respect to the wireless communication device 102 described above, which is capable of implementing bidirectional wireless communication with any of the other wireless communication devices in the network environment 100 to form the communication system 200, as shown in the architectural diagram of the communication system 200 shown in fig. 2, the communication system 200 may include a transmitter 202 (such as the wireless communication device 102 in the network environment 100 shown in fig. 1) and a receiver 206 (such as any of the other wireless communication devices in the network environment 100 shown in fig. 1), wherein the transmitter 202 may include one or more transmit antennas 204 (e.g., N1 transmit antennas), and the receiver 206 includes one or more receive antennas 208 (e.g., N2 receive antennas). The transmitter 202 transmits UWB pulses through the transmit antenna 204 to transmit a data stream, which travels through a wireless channel 210 to each receive antenna 208 of the receiver 206, and the receiver 206 may receive signals from each receive antenna 208 to reconstruct the data stream.

For the transmitter 202 shown in fig. 2, each transmit antenna 204 corresponds to a transmit front end 230. The hardware architecture of each transmit front end 230 can be seen in fig. 3, and includes: an ARM processor 231, a transmitting-end Digital controller 232, a Digital-to-Analog Converter (DAC) 233, and a power mixer 234; specifically, the transmitting end digital controller 232 is connected to the ARM processor 231 through the SPI interface to obtain the original data to be transmitted. The original data is encoded by the encoder 2321 in the digital controller 232 at the transmitting end and then stored in the data buffer 2322, and then the DAC data stream generator 2323 generates a data stream adapted to the DAC 233 based on the encoded data, so that the data stream generated by the DAC 233 according to the encoded data is converted into a corresponding baseband analog signal and transmitted to the power mixer PA 234; finally, the power mixer 234 mixes the local oscillator signal LO provided by the Digitally Controlled Oscillator (DCO) and the radio frequency Divider (RF Divider) with the baseband analog signal to generate a UWB pulsed radio frequency signal, which is finally transmitted to the wireless channel 210 via the transmitting antenna 204.

Based on the hardware architecture of the transmitting front end 230 shown in fig. 3, taking a UWB pulse radio frequency signal as an example, as shown in fig. 4, a Frame of UWB Data includes a Preamble, a Start of Frame Delimiter (SFD), a Physical HeadeR (PHR), and a Physical Service Data Unit (PSDU); and within a frame of UWB data, rather than pulses being sent out all the time, there will be a period of zero level between pulses, as specified by the protocol. Based on this, when encoding the original data to be transmitted, the encoder 2321 usually forms two encoded data portions based on the original data, wherein one portion (denoted by b 0) represents the presence or absence of a pulse, and the other portion (denoted by b 1) represents the polarity of the pulse; these two coded data portions are each represented by 1bit, as shown in the following table:

TABLE 1

That is, when b0 is zero, it can indicate that the zero point between the pulses is flat, and thus the original data is completely encoded for representation. After encoding, the two encoded data portions are buffered in the data buffer 2322, and accordingly pass through the DAC data stream generator 2323 and the DAC 233 to generate a baseband analog signal, so as to generate a UWB pulse radio frequency signal by using the PA 234.

For the zero level duration shown in fig. 4, PA 234 may be turned off to achieve power savings. At present, the software program and the protocol layer can only realize duty ratio control on zero level between data frames, and cannot realize duty ratio control inside the data frames, that is, at present, the software program and the protocol layer cannot be used for realizing finer duty ratio control in the related scheme.

Based on the above, embodiments of the present invention are expected to achieve finer duty control in the physical layer, and in particular, to enable duty control for the inside of a data frame. Based on this, referring to fig. 5 in conjunction with the hardware architecture of the transmit front end 230 shown in fig. 3, in an embodiment of the present invention, a duty cycle controller 2324 is additionally disposed in the transmit digital controller 232, as shown in fig. 5, the duty cycle controller 2324 is respectively connected to the data buffer 2322 and the PA 234, and is applied to the duty cycle controller 2324 shown in fig. 5, and an embodiment of the present invention provides a duty cycle control method applied to a physical layer, referring to fig. 6, the method may include:

s601: duty cycle controller 2324 reads encoded data indicating the presence or absence of a pulse, such as the encoded data portion identified as b0 above, from data buffer 2322;

s602: duty cycle controller 2324 generates control signals for controlling PA 234 based on the encoded data to control PA 234 to turn on when pulsed and to turn off when not pulsed.

Through the above technical solution shown in fig. 6, the duty cycle controller 2324 is used to control the PA 234 to be turned on and off according to whether the coded data has pulses, so as to implement the duty cycle control inside the data frame.

For the technical solution shown in fig. 6, in some possible implementations, the generating, by the duty cycle controller 2324, a control signal for controlling the PA 234 according to the encoded data specifically includes:

the duty ratio controller 2324 generates a data valid signal data _ valid according to the encoded data; wherein, when the encoded data indicates a pulse, the data valid signal data _ valid is at a high level; when the encoded data indicates no pulse, the data valid signal data _ valid is a low level.

For the above implementation, it should be noted that, in the process of controlling the PA 234 to turn on and turn off by using the data valid signal data _ valid, the start-up time of the PA 234 is not considered, that is, if the time interval between the turn-off and the start-up of the PA 234 is not enough, the abnormality of the transmission pulse may be caused due to the instability of the PA. In detail, in order to avoid an abnormal situation that the PA is unstable and thus causes a transmission pulse due to insufficient time intervals between the shutdown and the startup of the PA 234, in the process of generating the control signal for controlling the PA 234 as described in S602, the startup time of the PA 234 is considered, and in some possible implementations, after generating the data valid signal data _ valid, the method shown in fig. 6 may further include:

the duty controller 2324 reads the start-up time length value Tdelay of the PA 234 stored in the start-up delay Tdelay register, and obtains the control signal data _ valid _ delay of the data buffer 2321 after delaying the data valid signal data _ valid _ delay by Tdelay.

For the foregoing implementation, in a specific implementation process, the ARM processor 231 may configure the start delay Tdelay register through the SPI interface, where the stored Tdelay is a start duration of the PA 234, and the ARM processor 231 may configure the Tdelay to different values according to characteristics of an analog circuit of the PA 234. The data buffer 2321 may delay the encoded data obtained from the encoder 231 by Tdelay according to the control signal data _ valid _ delay thereof, and take b0 and b1 as examples, the data buffer 2321 delays both the encoded data by Tdelay, thereby obtaining b0 delay and b1 delay, respectively.

In some possible implementations, the method shown in fig. 6 may further include:

the duty controller 2324 generates a start pulse signal valid _ start at a first clock period of a high level of data _ valid according to the data valid signal data _ valid; the delayed stop pulse signal valid _ delay _ stop is generated at the last clock period of the data _ valid _ delay high level.

The duty ratio controller 2324 triggers the start counter to start counting through valid _ start; triggering a stop counter stop _ counter to start counting through a delayed stop pulse signal valid _ delay _ stop;

when the value of the stop _ counter is equal to the value of the start _ counter and is greater than 0, the duty ratio controller 2324 generates a reset pulse signal, and clears the start _ counter and the stop _ counter at a falling edge of the reset pulse signal;

when valid _ start is high, the duty controller 2324 pulls up the PA enable signal PA _ en, so that the PA 234 can be controlled to start; on the falling edge of the reset pulse signal, duty cycle controller 2324 pulls PA _ en low, thereby enabling control of PA 234 to turn off.

Since the DAC and the DAC data stream generator also have the hardware fixed delay value DAC delay, in order to consider the delay of this portion, in some examples, after obtaining pa _ en, the method further includes: duty cycle controller 2324 delays PA _ en by DAC delay for a clock period to obtain PA enable delay signal PA _ en _ delay, which is to be noted that PA _ en _ delay can be exactly time-aligned with the analog signal output by DAC, so as to control the switching of PA 234 more accurately.

For the above implementation and its examples, see fig. 7, which shows a timing diagram of generating the corresponding signal according to b0, in fig. 7, Tdelay =3, i.e. b0 delay is delayed by 3 clock cycles, for example, so that this partial delay guarantees that PA 234 has a sufficient start-up time. As can be seen from fig. 7, data _ valid is high when b0=1, and is low when b0= 0. The rising edge of data _ valid coincides with the rising edge of valid _ start and with the rising edge of pa _ en. Further, the falling edge of data _ valid _ delay coincides with the falling edge of valid _ delay _ stop, and also coincides with the falling edges of reset signal and pa _ en. According to the b1_ delay signal in the timing diagram, after delaying the DAC delay simultaneously with the b0_ delay signal, the analog pulse signal and the corresponding polarity can be formed, as shown in the last row in fig. 7. In addition, it should be noted that when b0 is 0 for a short time, such as only 1 clock cycle, as shown by the arrow in fig. 7, PA _ en is not pulled low for a short time due to the start _ counter and stop _ counter, but is maintained until the next b0 is 0, so as to avoid the insufficient start-up time caused by frequent switching off of PA 234.

Based on the same inventive concept of the foregoing technical solution, referring to fig. 8, a duty ratio controller 2324 provided in an embodiment of the present invention is shown, where the duty ratio controller 2324 includes: a reading portion 801 and a generating portion 802; wherein the reading section 801 is configured to read encoded data indicating the presence or absence of a pulse from a data buffer; the generating part 802 is configured to generate a control signal for controlling a power mixer PA in accordance with the encoded data to control the PA to be turned on when pulsed and to be turned off when not pulsed.

In the above scheme, the generating part 802 is configured to: generating a data valid signal data _ valid according to the encoded data; wherein the data _ valid is a high level when the encoded data indicates a pulse; when the encoded data indicates no pulse, the data _ valid is low level.

In the above scheme, the generating part 802 is further configured to:

reading a starting time length value Tdelay of the PA stored in a starting delay register, and delaying the data _ valid according to the Tdelay to obtain a control signal data _ valid _ delay of the data buffer, so that the data buffer delays the encoded data obtained from the encoder according to the Tdelay according to the data _ valid _ delay.

In the above scheme, the generating part 802 is further configured to:

generating a start pulse signal valid _ start in a first clock cycle of a high level of the data _ valid according to the data _ valid; generating a delayed stop pulse signal valid _ delay _ stop at the last clock period of the data _ valid _ delay high level;

triggering a start counter to start counting through the valid _ start; triggering a stop counter stop _ counter to start counting through the valid _ delay _ stop;

and generating a reset pulse signal when the value of the stop _ counter is equal to the value of the start _ counter and is greater than 0, and clearing the start _ counter and the stop _ counter at a falling edge of the reset pulse signal;

when the valid _ start is high, pulling up a PA enable signal PA _ en to control the PA to start; on the falling edge of the reset pulse signal, the duty cycle controller 2324 pulls the PA _ en low to control the PA to turn off.

In the above scheme, the generating part 802 is further configured to: and delaying the PA _ en according to hardware fixed delay values of a digital-to-analog converter DAC and a DAC data stream generator to obtain a PA enabling delay signal PA _ en _ delay.

It is understood that in this embodiment, "part" may be part of a circuit, part of a processor, or a unit, or may be a module or a non-modular.

In addition, each component in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit. The integrated unit may be implemented in the form of hardware. For a hardware implementation, the above-described components may be implemented in one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.

It can be understood that the above exemplary technical solution of the duty ratio controller 2324 belongs to the same concept as the above technical solution of the duty ratio control method applied to the physical layer, and therefore, the above detailed contents, which are not described in detail for the technical solution of the duty ratio controller 2324, can be referred to the description of the above technical solution of the duty ratio control method applied to the physical layer. The embodiments of the present invention will not be described in detail herein.

It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A duty cycle control method applied to a physical layer, the method comprising:

2. The method of claim 1, wherein the duty cycle controller generates a control signal for controlling a power mixer (PA) from the encoded data, comprising:

the duty ratio controller generates a data valid signal data _ valid according to the encoded data; wherein the data _ valid is a high level when the encoded data indicates a pulse; when the encoded data indicates no pulse, the data _ valid is low level.

3. The method of claim 2, further comprising:

the duty ratio controller reads a start-up time length value Tdelay of the PA stored in a start-up delay register, and obtains a control signal data _ valid _ delay of the data buffer after delaying the data _ valid according to the Tdelay, so that the data buffer delays the encoded data obtained from the encoder according to the data _ valid _ delay.

4. The method of claim 3, further comprising:

the duty ratio controller generates a start pulse signal valid _ start in a first clock period of a high level of the data _ valid according to the data _ valid; generating a delayed stop pulse signal valid _ delay _ stop at the last clock period of the data _ valid _ delay high level;

the duty ratio controller triggers a start counter to start counting through the valid _ start; triggering a stop counter stop _ counter to start counting through the valid _ delay _ stop;

when the value of the stop _ counter is equal to the value of the start _ counter and is greater than 0, the duty ratio controller generates a reset pulse signal, and clears the start _ counter and the stop _ counter at a falling edge of the reset pulse signal;

when the valid _ start is high, the duty ratio controller pulls up a PA enable signal PA _ en to control the PA to start; on the falling edge of the reset pulse signal, the duty cycle controller pulls the PA _ en low to control the PA to turn off.

5. The method of claim 4, further comprising:

and the duty ratio controller delays the PA _ en according to hardware fixed delay values of a digital-to-analog converter (DAC) and a DAC data stream generator to obtain a PA enabling delay signal PA _ en _ delay.

6. A duty cycle controller, characterized in that the duty cycle controller comprises: a reading section and a generating section; wherein the reading section is configured to read encoded data indicating the presence or absence of a pulse from a data buffer; the generating section is configured to generate a control signal for controlling a power mixer (PA) according to the encoded data to control the PA to be turned on when pulsed and to be turned off when not pulsed.

7. The duty cycle controller according to claim 6, wherein the generation section is configured to: generating a data valid signal data _ valid according to the encoded data; wherein the data _ valid is a high level when the encoded data indicates a pulse; when the encoded data indicates no pulse, the data _ valid is low level.

8. The duty cycle controller of claim 7, wherein the generating portion is further configured to:

9. The duty cycle controller of claim 8, wherein the generating portion is further configured to:

when the valid _ start is high, pulling up a PA enable signal PA _ en to control the PA to start; on the falling edge of the reset pulse signal, the duty cycle controller pulls the PA _ en low to control the PA to turn off.

10. The duty cycle controller of claim 9, wherein the generating portion is further configured to: and delaying the PA _ en according to hardware fixed delay values of a digital-to-analog converter DAC and a DAC data stream generator to obtain a PA enabling delay signal PA _ en _ delay.

11. A duty cycle control circuit for application to a physical layer, the circuit comprising: a data buffer, a power mixer and a duty cycle controller as claimed in any one of claims 6 to 10.

12. A transmitting device, characterized in that a transmit front end of the transmitting device comprises the duty cycle control circuit applied to the physical layer of claim 11.