CN113346885B - Single-pole double-throw switch circuit - Google Patents
Single-pole double-throw switch circuit Download PDFInfo
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- CN113346885B CN113346885B CN202010134504.8A CN202010134504A CN113346885B CN 113346885 B CN113346885 B CN 113346885B CN 202010134504 A CN202010134504 A CN 202010134504A CN 113346885 B CN113346885 B CN 113346885B
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- H—ELECTRICITY
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
Abstract
The invention discloses a single-pole double-throw switch circuit, comprising: the control signal generation module generates a first control signal and a second control signal according to the channel selection signal; the first gate voltage detection module is connected with the control signal generation module and generates a first feedback control signal according to the first control signal and the second feedback control signal; the second gate voltage detection module is connected with the control signal generation module and generates a second feedback control signal according to the second control signal and the first feedback control signal; the first transistor receives the first feedback control signal and switches on/off a first channel of the single-pole double-throw switch circuit according to the first feedback control signal; and the second transistor receives the second feedback control signal and switches on/off a second channel of the single-pole double-throw switch circuit according to the second feedback control signal. The single-pole double-throw switch circuit enhances the accuracy of the break-before-make function of the switch.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a single-pole double-throw switch circuit.
Background
For a single-pole multi-throw switch, taking a single-pole double-throw switch as an example, the break-before-make function is realized by generating two signals by a control signal through a two-phase non-overlapping signal generating circuit, and the two signals respectively control the two switches. The non-overlapping time of the two signals serves as break before make time of the switch.
The traditional circuit is an open-loop control circuit, the size of a switching transistor is large generally, the gate capacitance of the switching transistor is large for a CMOS (complementary metal oxide semiconductor) process, and the delay time from a two-phase non-overlapping signal generation circuit to a gate of a control signal is long. When the chip is applied, the chip can be under different temperature conditions, or the chip can meet different process angles in the processing process, for a circuit controlled by an open loop, the fixed non-overlapping time of two phases can not follow the drastic change of the process and the temperature, and the break-before-make time can be very short or even not, so that the break-before-make function fails.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problem, the invention provides a single-pole double-throw switch circuit which enhances the accuracy of the break-before-make function of a switch.
According to the present invention, there is provided a single pole double throw switch circuit comprising: the control signal generation module receives a channel selection signal and generates a first control signal and a second control signal according to the channel selection signal; the first gate voltage detection module is connected with the control signal generation module, receives the first control signal, simultaneously receives a second feedback control signal, and generates a first feedback control signal according to the first control signal and the second feedback control signal; the second gate voltage detection module is connected with the control signal generation module, receives the second control signal, receives the first feedback control signal at the same time, and generates a second feedback control signal according to the second control signal and the first feedback control signal; the first transistor is used for receiving the first feedback control signal and switching on/off a first channel of the single-pole double-throw switch circuit according to the first feedback control signal; and the second transistor is used for receiving the second feedback control signal and switching on/off a second channel of the single-pole double-throw switch circuit according to the second feedback control signal.
Preferably, the first gate voltage detection module includes: a third transistor, a source electrode of which is connected with a power supply end through a first current source, a grid electrode of which receives bias voltage, and a drain electrode of which receives the second feedback control signal; a fourth transistor having a source connected to a power source terminal, a drain connected to a ground terminal via a second current source, and a gate connected to a connection point of the first current source and the third transistor; and the first input end of the first OR gate receives the first control signal, the second input end of the first OR gate is connected with a connection point of the fourth transistor and the second current source, and the output end of the first OR gate outputs the first feedback control signal.
Preferably, the second gate voltage detection module includes: a fifth transistor, a source connected to a power supply terminal through a third current source, a gate receiving a bias voltage, and a drain receiving the first feedback control signal; a sixth transistor, a source connected to a power supply terminal, a drain connected to a ground terminal via a fourth current source, and a gate connected to a connection point of the third current source and the fifth transistor; and a second or gate, wherein a first input end receives the second control signal, a second input end is connected with a connection point of the sixth transistor and the fourth current source, and an output end outputs the second feedback control signal.
Preferably, the third transistor and the fourth transistor are both PMOS transistors.
Preferably, a difference between the voltage of the power source terminal and the bias voltage is larger than a sum of a gate-source voltage of the third transistor and a gate-source voltage of the fourth transistor.
Preferably, an output current when the fourth transistor is turned on is much larger than an output current of the second current source.
Preferably, the fifth transistor and the sixth transistor are both PMOS transistors.
Preferably, a difference between the voltage of the power source terminal and the bias voltage is greater than a sum of a gate-source voltage of the fifth transistor and a gate-source voltage of the sixth transistor.
Preferably, an output current when the sixth transistor is turned on is much larger than an output current of the fourth current source.
Preferably, the first transistor and the second transistor are both PMOS transistors.
The invention has the beneficial effects that: the invention discloses a single-pole double-throw switch circuit.A gate voltage detection module is added in the circuit to detect the change of the gate voltage of a switch tube in the switching-off process of one channel and generate a switching-on/off control signal of the other channel. Only when the gate voltage of the channel is changed to a final voltage value, namely the channel is completely switched off, the gate control signal of the other channel is changed to switch on the other channel, so that the accuracy of switching on and switching off before switching on is ensured.
Meanwhile, the number of components required by the first gate voltage detection module and the second gate voltage detection module is small, the structure is simple, and the cost is low.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a prior art single pole double throw switch circuit;
FIG. 2 shows a timing diagram of the circuit of FIG. 1 in an ideal state for the single pole, double throw switch circuit;
FIG. 3 shows a circuit timing diagram for the normal state of the single pole double throw switch circuit of FIG. 1;
FIG. 4 shows a circuit timing diagram for an abnormal state of the single pole double throw switch circuit of FIG. 1;
FIG. 5 shows a block diagram of a single pole, double throw switch circuit provided by an embodiment of the invention;
fig. 6(a) and 6(b) are schematic circuit diagrams illustrating the first and second gate voltage detecting units of fig. 5, respectively;
fig. 7 shows a circuit timing diagram of a single pole double throw switch circuit provided by an embodiment of the invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram showing a structure of a conventional single-pole double-throw switch circuit, fig. 2 is a circuit timing diagram of the single-pole double-throw switch circuit in an ideal state in fig. 1, fig. 3 is a circuit timing diagram of the single-pole double-throw switch circuit in a normal state in fig. 1, and fig. 4 is a circuit timing diagram of the single-pole double-throw switch circuit in an abnormal state in fig. 1.
As shown in fig. 1, a conventional single pole double throw switch circuit includes: a control signal generation module 110, a first transistor M0, and a first transistor M1.
The control signal generating module 110 receives the channel selection signal select and generates the first control signal s0 and the second control signal s1 according to the channel selection signal.
The first transistor M0 has a source terminal as a signal input/output terminal B0, a drain terminal connected to the common terminal a, and a gate terminal receiving the first control signal s 0. The second transistor M1 has a drain terminal serving as a signal input/output terminal B1, a source terminal connected to the common terminal a, and a gate terminal receiving a second control signal s 1.
Wherein, two channels of the single-pole double-throw switch circuit are respectively B0-A and B1-A. The control signal generating module 110 is a two-phase non-overlapping signal generating circuit, and the generated first control signal s0 and second control signal s1 are two-phase non-overlapping signals, and only one of the first transistor M0 and the second transistor M1 is controlled to be turned on. For example, when the first control signal s0 is asserted, the first transistor M0 is controlled to be turned on, and the first channel B0-a of the single-pole double-throw switch circuit is turned on; at this time, the second control signal s1 is in an inactive state, the second transistor M1 is turned off, and the second channel B1-a of the single-pole double-throw switch circuit is turned off.
The operation timing of the spdt analog switch is shown in fig. 2 to 4, and the first control signal s0 and the second control signal s1 are set to be active at low level and inactive at high level. The specific working principle is that when the channel selection signal select changes from low level to high level, the first control signal s0 changes from low level to high level, and the first channel B0-a is turned off. After the time interval t 2-t 1, the second control signal s1 changes from high to low to open the second channel B1-A. The Time interval after the first channel B0-A turns off and Before the second channel B1-A turns on is called Break Before Make Time (Break Before Make Time), denoted as tB.
Fig. 2 shows that in an ideal state, the rising and falling edges of the first control signal s0 and the second control signal s1 are small, and the break-before-make time tB is t 2-t 1.
However, in practice, the process of changing the first control signal s0 and the second control signal s1, which is also the process of charging and discharging the gate capacitance of the transistor, always requires a certain time, and the operation timing is as shown in fig. 3, the rising edge and the falling edge of the first control signal s0 and the second control signal s1 become slow, but the first control signal s0 is still pulled up to the power supply voltage before the time t2, the second control signal s1 starts to fall from the time t2, and the second channel B1-a starts to be on, so that the break-before-make function is ensured.
However, when the transistor size is larger, the corresponding gate parasitic capacitance of the transistor is larger, and the charging and discharging time is longer. In actual operation, the charging and discharging time becomes longer due to changes in conditions such as temperature and power supply voltage. FIG. 4 shows an abnormal operation timing diagram, in which the gate voltage of the first channel B0-A (i.e. the first control signal s0) is pulled up to the power voltage at time t3 after the channel select signal select changes from low to high, and the first channel B0-A is completely turned off. However, at time t2, the second control signal s1 has gone low and the second channel B1-A has begun to conduct, i.e., the second channel B1-A has already conducted when the first channel B0-A has not completely turned off, and obviously has not met the break-before-make requirement.
It can be seen that for a fixed time interval generated by a two-phase non-overlapping signal generating circuit (corresponding to the control signal generating module 110 herein), if the on and off of the switch become slower under different condition changes, the break-before-make time tB of the circuit may be very small or even disappear, so that the break-before-make function fails.
Fig. 5 shows a block diagram of a single-pole double-throw switch circuit according to an embodiment of the present invention, fig. 6(a) and 6(b) show schematic circuit diagrams of the first and second gate voltage detection units in fig. 5, respectively, and fig. 7 shows a timing diagram of the single-pole double-throw switch circuit according to an embodiment of the present invention.
As shown in fig. 5, in the present embodiment, the single-pole double-throw switch circuit includes: a control signal generating module 210, a first gate voltage detecting module 220, a second gate voltage detecting module 230, a first transistor M0, and a second transistor M1.
The control signal generating module 210 receives the channel selection signal select, and generates the first control signal s0 and the second control signal s1 according to the channel selection signal select.
The first gate voltage detecting module 220 is connected to the control signal generating module 210, receives the first control signal s0 and the second feedback control signal s1d, and generates the first feedback control signal s0d according to the first control signal s0 and the second feedback control signal s1 d.
The second gate voltage detecting module 230 is connected to the control signal generating module 210, receives the second control signal s1 and the first feedback control signal s0d, and generates the second feedback control signal s1d according to the second control signal s1 and the first feedback control signal s0 d.
The first transistor M0 has a source terminal as a signal input/output terminal B0, a drain terminal connected to the common terminal a, and a gate terminal receiving the first feedback control signal s0 d.
The second transistor M1 has a drain that is a signal input/output terminal B1, a source connected to the common terminal a, and a gate that receives the second feedback control signal s1 d.
In this embodiment, the two channels of the single-pole double-throw switch circuit are a first channel B0-A and a second channel B1-A, respectively.
Further, the first transistor M0 and the second transistor M1 have the same channel type and may be any one of an NMOS transistor and a PMOS transistor. In the present embodiment, the first transistor M0 and the second transistor M1 are preferably PMOS transistors.
Further, as shown in fig. 6(a), the circuit structure of the first gate voltage detecting module 220 includes: a first current source I1, a second current source I2, a third transistor M3, a fourth transistor M4, and a first or gate U1. The source of the third transistor M3 is connected to the power supply terminal VCC through the first current source I1, the gate of the third transistor M3 receives the bias voltage Vb, and the drain of the third transistor M3 receives the second feedback control signal s1 d. The source of the fourth transistor M4 is connected to the power supply terminal VCC, the drain of the fourth transistor M4 is connected to the ground terminal via the second current source I2, and the gate of the fourth transistor M4 is connected to the connection point (node H1) between the first current source I1 and the third transistor M3. A first input of the first or gate U1 receives the first control signal s0, a second input of the first or gate U1 is connected to the connection point (node s1c) of the fourth transistor M4 and the second current source I2, and an output of the first or gate U1 outputs a first feedback control signal s0 d.
Further, the third transistor M3 and the fourth transistor M4 are PMOS transistors.
In this embodiment, the gate voltage of the third transistor M3 is a fixed bias voltage Vb, and the difference (VCC-Vb) between the VCC voltage and the bias voltage Vb is at least greater than the sum (Vsg _ M3+ Vsg _ M4) of the gate-source voltage of the third transistor M3 and the gate-source voltage of the fourth transistor M4. Meanwhile, the drain terminal of the third transistor M3 is used for detecting the gate voltage s1d of the second transistor M1, and since the bias voltage Vb is a fixed value, the third transistor M3 is in a turned-on state, and the voltage of the node H1 follows the second feedback control signal s1d at the drain terminal of the third transistor M3.
Further, the current capability of the fourth transistor M4 when turned on is much larger than the output current of the second current source I2, so that the voltage at the second input terminal of the first or gate U1, i.e., the voltage at the node s1c, can be pulled high to ensure the correctness of the subsequent logic.
The circuit structure of the second gate voltage detecting module 230, as shown in fig. 6(b), includes: a third current source I3, a fourth current source I4, a fifth transistor M5, a sixth transistor M6, and a second or gate U2. The source of the fifth transistor M5 is connected to the power supply terminal VCC through the third current source I3, the gate of the fifth transistor M5 receives the bias voltage Vb, and the drain of the fifth transistor M5 receives the first feedback control signal s0 d. The source of the sixth transistor M6 is connected to the power supply terminal VCC, the drain of the sixth transistor M6 is connected to the ground terminal via the fourth current source I4, and the gate of the sixth transistor M6 is connected to the connection point (node H0) between the third current source I3 and the fifth transistor M5. A first input of the second or gate U2 receives the second control signal s1, a second input of the second or gate U2 is connected to the connection point (node s0c) of the sixth transistor M6 and the fourth current source I4, and an output of the second or gate U2 outputs a second feedback control signal s1 d.
Further, the fifth transistor M5 and the sixth transistor M6 are PMOS transistors. In the present embodiment, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are preferably PMOS transistors.
In this embodiment, the gate voltage of the fifth transistor M5 is a fixed bias voltage Vb, and the difference (VCC-Vb) between the power source terminal VCC voltage and the bias voltage Vb is at least greater than the sum (Vsg _ M5+ Vsg _ M6) of the gate-source voltage of the fifth transistor M5 and the gate-source voltage of the sixth transistor M6. Meanwhile, the drain terminal of the fifth transistor M5 is used for detecting the gate voltage s0d of the first transistor M0, and since the bias voltage Vb is a fixed value, the fifth transistor M5 is in a conducting state, and the voltage of the node H0 follows the first feedback control signal s0d at the drain terminal of the fifth transistor M5.
Further, the current capability of the sixth transistor M6 when turned on is much larger than the output current of the fourth current source I4, so that the voltage at the second input terminal of the second or gate U2, i.e., the voltage at the node s0c, can be pulled high to ensure the correctness of the subsequent logic.
In this embodiment, the control signal generating module 210 is a two-phase non-overlapping signal generating circuit, the first control signal s0 and the second control signal s1 generated by the two-phase non-overlapping signal generating circuit are two-phase non-overlapping signals, and the first feedback control signal s0d and the second feedback control signal s1d generated according to the two-phase non-overlapping first control signal s0 and the second control signal s1 are also two-phase non-overlapping signals, which only control one of the first transistor M0 and the second transistor M1 to be turned on. For example, when the first feedback control signal s0d is asserted, the first transistor M0 is controlled to be turned on, and the first channel B0-a of the single-pole double-throw switch circuit is turned on; at this time, the second feedback control signal s1d is in an inactive state, the second transistor M1 is turned off, and the second channel B1-a of the single-pole double-throw switch circuit is turned off.
In this embodiment, the operation timing of the single-pole double-throw switch circuit is shown in fig. 7. In fig. 6(B), the gate voltage of the first channel B0-a, i.e., the first feedback control signal s0d, is detected. When the channel selection signal select is low and the first channel B0-a is turned on, the first feedback control signal s0d is low and the sixth transistor M6 is turned on. Since the current capability of the sixth transistor M6 is greater than that of the fourth current source I4, the node s0c is high, the second feedback control signal s1d output by the second or gate U2 is also high, and the second channel B1-a is turned off.
After the channel selection signal select changes from low level to high level, the first control signal s0 changes from low level to high level at time t 1. After passing through the or gate U1 in fig. 6(a), the first feedback control signal s0d also starts to go high at time t1, and starts to turn off the first channel B0-a. At time t3, the first feedback control signal s0d is pulled up to the power supply terminal VCC voltage, by which the first channel B0-a is completely turned off. At this time, fig. 6(b) detects that the first channel s0d goes high, turning off the sixth transistor M6, and the node s0c is pulled down to ground by the fourth current source I4. Although the second control signal s1 has changed from high to low at time t2, since the node s0c is still high, the potential of the second feedback control signal s1d is not changed, and the second channel B1-a is not turned on. When the node s0c changes from high to low at time t3, the second control signal s1 and the node s0c both become low, and the second feedback control signal s1d starts to change from high to low after passing through the second or gate U2. At time t9, the second feedback control signal s1d goes low completely and the second channel B1-A completes conducting. Meanwhile, during the voltage drop of the second feedback control signal s1d, the fourth transistor M4 is gradually turned on, and at time t7, the node s1c changes from low level to high level. Since the first control signal s0 has become high at time t1, the voltage change at the node s1c does not cause a change in the first feedback control signal s0d at time t7, and thus the on/off state of the first channel B0-a is not changed.
Similarly, after the channel selection signal select changes from high level to low level, the second control signal s1 changes from low level to high level, and the second channel B1-A is gradually turned off. At time t6, the second feedback control signal s1d is pulled up to the power supply terminal VCC voltage, and the second channel B1-a is completely turned off. At this time, the voltage at the node s1c starts to become low, the voltages at the first control signal s0 and the node s1c are low at the same time, and the first feedback control signal s0d starts to become low from high after passing through the first or gate U1. At time t10, the first feedback control signal s0d goes low completely and the first channel B0-A completes conducting.
As can be seen from the above description, since the first and second gate voltage detection modules shown in fig. 6(a) and 6(b) are added to the single-pole double-throw switch circuit, no matter how slow the process of pulling up the gate voltages of the first transistor M0 and the second transistor M1 is, during the switch turn-off process, the gate voltage of the transistor of one channel will not be changed until the other channel is not completely turned off, and the channel will not be turned on, thereby ensuring the accuracy of the break-before-make function of the single-pole double-throw switch.
In summary, the present invention adds a gate voltage detection module to a single-pole double-throw switch circuit to detect the change of the gate voltage of one channel during the switching-off process of the other channel, and generate the on-off control signal of the other channel. Only when the gate voltage of the channel is changed to a final voltage value, namely the channel is completely switched off, the gate control signal of the other channel is changed to switch on the other channel, so that the accuracy of switching on and switching off before switching on is ensured.
Meanwhile, the number of components required by the gate voltage detection module added in the embodiment is small, the structure is simple, and the cost is low.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (10)
1. A single pole, double throw switch circuit, comprising:
the control signal generation module receives a channel selection signal and generates a first control signal and a second control signal according to the channel selection signal;
the first gate voltage detection module is connected with the control signal generation module, receives the first control signal, simultaneously receives a second feedback control signal, and generates a first feedback control signal according to the first control signal and the second feedback control signal;
the second gate voltage detection module is connected with the control signal generation module, receives the second control signal, receives the first feedback control signal at the same time, and generates a second feedback control signal according to the second control signal and the first feedback control signal;
the first transistor is used for receiving the first feedback control signal and switching on/off a first channel of the single-pole double-throw switch circuit according to the first feedback control signal; and
and the second transistor is used for receiving the second feedback control signal and switching on/off a second channel of the single-pole double-throw switch circuit according to the second feedback control signal.
2. The single pole double throw switch circuit of claim 1, wherein the first gate voltage detection module comprises:
a third transistor, a source electrode of which is connected with a power supply end through a first current source, a grid electrode of which receives bias voltage, and a drain electrode of which receives the second feedback control signal;
a fourth transistor having a source connected to a power source terminal, a drain connected to a ground terminal via a second current source, and a gate connected to a connection point of the first current source and the third transistor;
and a first input end of the first or gate receives the first control signal, a second input end of the first or gate is connected with a connection point of the fourth transistor and the second current source, and an output end of the first or gate outputs the first feedback control signal.
3. The single pole, double throw switch circuit of claim 2, wherein the second gate voltage detection module comprises:
a fifth transistor, a source connected to a power supply terminal through a third current source, a gate receiving a bias voltage, and a drain receiving the first feedback control signal;
a sixth transistor, a source connected to a power supply terminal, a drain connected to a ground terminal via a fourth current source, and a gate connected to a connection point of the third current source and the fifth transistor;
and a second or gate, wherein a first input end receives the second control signal, a second input end is connected with a connection point of the sixth transistor and the fourth current source, and an output end outputs the second feedback control signal.
4. The single-pole double-throw switch circuit of claim 3, wherein the third transistor and the fourth transistor are both PMOS transistors.
5. The single-pole double-throw switch circuit according to claim 4, wherein a difference between the voltage of the power source terminal and the bias voltage is larger than a sum of a gate-source voltage of the third transistor and a gate-source voltage of the fourth transistor.
6. The single-pole double-throw switch circuit of claim 5, wherein an output current of the fourth transistor when turned on is much larger than an output current of the second current source.
7. The single-pole double-throw switch circuit of claim 6, wherein the fifth transistor and the sixth transistor are both PMOS transistors.
8. The single-pole double-throw switch circuit of claim 7, wherein the difference between the voltage of the power supply terminal and the bias voltage is greater than the sum of the gate-source voltage of the fifth transistor and the gate-source voltage of the sixth transistor.
9. The single-pole double-throw switch circuit of claim 8, wherein an output current of the sixth transistor when turned on is much larger than an output current of the fourth current source.
10. The single-pole double-throw switch circuit of claim 9, wherein the first transistor and the second transistor are both PMOS transistors.
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| GaAs PHEMT通信开关电路设计;白元亮等;《半导体技术》;20130903(第09期);全文 * |
| Transmitter leakage analysis when operating USRP (N210) in duplex mode;Arul Mathi Maran Chandran等;《2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings》;20150709;全文 * |
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| CN113346885A (en) | 2021-09-03 |
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