CN113346564A

CN113346564A - Power management chip control method and device and terminal equipment

Info

Publication number: CN113346564A
Application number: CN202010135306.3A
Authority: CN
Inventors: 马强
Original assignee: Beijing Xiaomi Mobile Software Co Ltd
Current assignee: Beijing Xiaomi Mobile Software Co Ltd
Priority date: 2020-03-02
Filing date: 2020-03-02
Publication date: 2021-09-03

Abstract

The disclosure relates to a power management chip control method and device and terminal equipment, and belongs to the technical field of power management. The power management chip is matched with a processor of terminal equipment, and the method is executed in a plurality of cycles, and in one cycle, the method comprises the following steps: controlling the input voltage of the power management chip in a first time period, and acquiring the working efficiency of the power management chip; determining an input voltage corresponding to the maximum working efficiency in a first time period; taking the input voltage corresponding to the maximum working efficiency as the input voltage of the power management chip in a second time period; the second time period is a time period within the cycle other than the first time period.

Description

Power management chip control method and device and terminal equipment

Technical Field

The disclosure relates to the technical field of terminal equipment charging, in particular to a power management chip control method and device and terminal equipment.

Background

The terminal equipment needs power to maintain normal use. A power management chip is generally provided in a terminal device. When the power supply management chip is used, on one hand, the power supply management chip distributes the electric quantity of the battery in the terminal equipment to other different components; and on the other hand, the charging voltage provided by the external component is received to charge the battery.

The working efficiency of the power management chip may affect the user experience of the terminal device, so it is necessary to control the power management chip to achieve better working efficiency. However, the power management chip provided in the related art does not reach the maximum operating efficiency when in use, and has room for further improvement.

Disclosure of Invention

The disclosure provides a power management chip control method and device and terminal equipment, and aims to solve the problems in the related art.

In a first aspect, the present disclosure provides a power management chip control method, where the power management chip cooperates with a processor of a terminal device, and the method is performed in a plurality of cycles, where in one of the cycles, the method includes:

controlling the input voltage change of the power management chip in a first time period, and acquiring the working efficiency of the power management chip under different input voltages;

determining the input voltage corresponding to the maximum working efficiency in the first time period;

taking the input voltage corresponding to the maximum working efficiency as the input voltage of the power management chip in a second time period; the second time period is a time period within the cycle other than the first time period.

In one embodiment, the controlling the input voltage of the power management chip and obtaining the operating efficiency of the power management chip in the first period of time includes:

controlling the input voltage to gradually rise within the first time period by a set number of times and a set amplitude;

and responding to the rise of the input voltage, and acquiring the working efficiency of the power management chip.

In one embodiment, the obtaining the operating efficiency of the power management chip includes:

acquiring input voltage, output voltage, input current and output current of the power management chip;

and acquiring the working efficiency according to the input voltage, the input current, the output voltage and the output current.

In one embodiment, the terminal device further includes a current detection component, and the obtaining the input current and the output current of the power management chip includes:

receiving the input current and the output current detected by the current detection component.

In one embodiment, the processor includes an analog-to-digital conversion component, and the obtaining the input voltage and the output voltage of the power management chip includes:

and receiving the input voltage and the output voltage of the power management chip through the analog-to-digital conversion component.

In one embodiment, before controlling the input voltage of the power management chip during the first period of time, the method further comprises:

and detecting a charging trigger operation, so as to execute the control of the input voltage change of the power management chip in the first time period and acquire the working efficiency of the power management chip under different input voltages when the charging trigger operation is detected.

In a second aspect, an embodiment of the present disclosure provides a power management chip control apparatus, where the power management chip is applied to a terminal device and is matched with a processor of the terminal device; the apparatus is used in a plurality of cycles, one of the cycles comprising a first time period and a second time period; the device comprises:

the acquisition module is used for controlling the input voltage change of the power management chip in a first time period and acquiring the working efficiency of the power management chip under different input voltages;

the determining module is used for determining the input voltage corresponding to the maximum working efficiency in the first time period; and

the working module is used for taking the input voltage corresponding to the maximum working efficiency as the input voltage of the power management chip in a second time period; the second time period is a time period within the cycle other than the first time period.

In one embodiment, the obtaining module comprises: the control unit is used for controlling the input voltage to gradually increase within the first time period by a set number of times and a set amplitude; and

and the acquisition unit is used for responding to the secondary rise of the input voltage and acquiring the working efficiency of the power management chip.

In an embodiment, the obtaining unit is specifically configured to, when obtaining the working efficiency of the power management chip: acquiring input voltage, output voltage, input current and output current of the power management chip; and acquiring the working efficiency according to the input voltage, the input current, the output voltage and the output current.

In one embodiment, the terminal device further includes a current detection component, and the obtaining unit is specifically configured to, when obtaining the input current and the output current:

In one embodiment, the processor includes an analog-to-digital conversion component, and the obtaining unit is specifically configured to, when obtaining the input voltage and the output voltage:

In one embodiment, the apparatus is applied to a charging process of a terminal device, and the apparatus further includes: the detection module is used for detecting charging trigger operation so as to execute the control of the input voltage change of the power management chip in the first time period and acquire the working efficiency of the power management chip under the condition of different input voltages when the charging trigger operation is detected.

In a third aspect, an embodiment of the present disclosure provides a terminal device, where the terminal device includes:

a power management chip;

the processor is electrically connected with the power management chip;

a memory storing the processor-executable instructions;

the processor is configured to execute the executable instructions in the memory to implement the steps of the power management chip control method provided above.

In one embodiment, the terminal device further includes a current detection component, an input end of the current detection component is connected to the power management chip, and an output end of the current detection component is connected to the processor;

in a first time period, the current detection component responds to the input voltage change of the power management chip, obtains the input current and the output current of the power management chip, and sends the obtained input current and output current to the processor.

In a fourth aspect, the disclosed embodiments provide a readable storage medium, on which executable instructions are stored, which when executed by a light sensor core, implement the steps of the power management chip control method provided above.

The power management chip control method, the power management chip control device and the terminal equipment provided by the disclosure have the following beneficial effects:

according to the control method of the power management chip provided by the embodiment of the disclosure, in one period, the working efficiency of the power management chip is obtained every time when the input voltage is increased in the first time period, so that the input voltage corresponding to the maximum working efficiency in the first time period is determined. And taking the input voltage corresponding to the maximum working efficiency as the input voltage of the power management chip in the second time period. In this way, through the operating condition of real-time detection power management chip, guarantee power management chip with the work of highest work efficiency, optimize chip work efficiency, reduce the chip and generate heat. Moreover, the control method of the power management chip is strong in operability, the hardware architecture is easy to realize, the working efficiency of the power management chip is effectively improved, and the technical defects of the related technology are overcome.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a diagram illustrating a connection relationship of components in a terminal device according to an exemplary embodiment;

FIG. 2 is a schematic flow diagram illustrating a power management chip control method according to an exemplary embodiment;

FIG. 3 is a flow chart illustrating a method for obtaining chip operating efficiency in a power management chip control method according to an exemplary embodiment;

FIG. 4 is a flowchart illustrating a method for obtaining chip operating efficiency in a power management chip control method according to another exemplary embodiment;

FIG. 5 is a block diagram illustrating a power management chip control apparatus according to an exemplary embodiment;

FIG. 6 is a block diagram illustrating an acquisition module in a power management chip control apparatus according to an example embodiment;

fig. 7 is a block diagram of a terminal device shown according to an example embodiment.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this disclosure do not denote a limitation of quantity, but rather denote the presence of at least one. Unless otherwise indicated, the word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprises" or "comprising" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

As used in the specification and claims of this disclosure, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

Generally, when the input voltage and the output voltage of a "three level" type power management chip or an "1/2 divider" type power management chip provided in the related art satisfy the following relationship, the working efficiency of the power management chip is the maximum:

Vin＝2Vout+dV

where Vin is the input voltage, Vout is the output voltage, and dV is the variation. The dV is influenced by parameters such as input current and output voltage of the power management chip. In addition, because dV is difficult to measure when the input voltage is unknown, in the related art, dV is ignored, and it is roughly considered that the operating efficiency of the power management chip is the highest when the input voltage is 2 times the output voltage.

Taking the scenario that the power management chip charges the battery of the terminal device as an example, the output voltage of the power management chip changes along with the gradual change of the electric quantity of the battery. Further, the input voltage is determined in a relationship that the input voltage is 2 times the output voltage.

However, the input voltage determined in this way causes the operating efficiency of the power management chip to be always less than the maximum value. In other words, the power management chip control method provided in the related art has a further optimized space to improve the working efficiency and reduce the heat dissipation.

Based on the above situation, the embodiment of the disclosure provides a power management chip control method and device, and a terminal device. The power management chip is applied to the terminal equipment and is matched with a processor of the terminal equipment. Before describing the power management chip control method and apparatus provided by the embodiments of the present disclosure, a terminal device to which the method and apparatus are applied is first introduced.

Fig. 1 is a block diagram of a power management chip and a processor in a terminal device according to an exemplary embodiment. As shown in FIG. 1, processor 100 is coupled to a power management chip 200. The power management chip 200 is integrated with a current detection component 300, and the current detection component 300 is connected to the processor 200 through an I2C bus through a pin of the power management chip 200. In this manner, the processor 200 is able to receive current data detected by the current detection component 300.

The input terminal of the current detection component 300 is connected to the power management chip 200, and is used for detecting the input current and the output current of the power management chip 200.

Illustratively, the power management chip 200 includes a first terminal 210, and a current limiting switching element 220 connected to the first terminal 210. The input terminal of the current detection component 300 is connected to the current-limiting switching element 220 of the power management chip 200, and is configured to obtain a current passing through the current-limiting switching element 220, that is, an input current of the power management chip 200.

The power management chip 200 further includes a second terminal 230, and the second terminal 230 is connected to a load (e.g., a resistor, an inductor, or the like) external to the power management chip 200. The input terminal of the current detecting component 300 is further connected to an external load connected to the second terminal 230 of the power management chip 200, and is used for obtaining a current passing through the load, that is, an output current of the power management chip 200.

In addition, the output terminal of the current detection assembly 300 is connected to the processor 100 to transmit the detected input current and output current to the processor 100. Optionally, the current sensing component 300 is integrated on the power management chip and sends the sensed input current and output current to the processor 100 through the pins of the power management chip 200 and the I2C bus.

Furthermore, the processor 100 includes an analog-to-digital conversion component 110, and the input 210 and the output 240 of the power management chip 200 are further connected to the analog-to-digital conversion component 110. In this manner, the processor 100 receives the input voltage and the output voltage of the power management chip 200 through the analog-to-digital conversion component 110.

The specific type of the terminal device is not limited, for example, the terminal device is a mobile phone, a tablet computer, an intelligent wearable device (e.g., an intelligent bracelet, an intelligent watch, intelligent glasses, etc.), an on-vehicle device, a medical device, or the like.

On the basis of the hardware of the terminal device, the embodiment of the disclosure provides a power management chip control method.

Fig. 2 is a flowchart illustrating a power management chip control method according to an exemplary embodiment. The power management chip control method is executed in a plurality of cycles. In one of the periods, as shown in fig. 2, the method includes:

step S201, controlling the input voltage change of the power management chip in a first time period, and obtaining the working efficiency of the power management chip under different input voltages.

Illustratively, during the charging process of the terminal device, the power management chip is connected with the charger through the control circuit and the charging interface. In such a case, the processor of the terminal device may control the voltage output by the charger through the control circuit to achieve regulation of the input voltage. Further, in step S201, the correspondence relationship between the input voltage and the power management chip is recorded.

Fig. 3 is a flowchart illustrating a power management chip control method for obtaining chip operating efficiency according to an exemplary embodiment. In one embodiment, as shown in fig. 3, step S201 specifically includes:

step S301, controlling the input voltage to gradually rise by a set number of times and a set amplitude in a first time period.

In this way, the input voltage of the power management chip changes in a step shape in the first time period. The number of times and the width of settings are not particularly limited. For example, the setting range is 10mv, 20mv, 50mv, etc.; the set number of times is 5 times, 10 times, 20 times, 30 times, 40 times, etc. The more the setting times are, the smaller the setting amplitude is, the input voltage of the power management chip tends to continuously change, and the maximum working efficiency of the power management chip can be accurately obtained in the subsequent steps.

And S302, responding to the rise of the input voltage, and acquiring the working efficiency of the power management chip.

The input voltage changes cause the input current and the output current of the power management chip to change. Moreover, taking the charging process as an example, as the charging proceeds, the battery capacity gradually increases, which also affects the input current and the output current of the power management chip. In such a case, the processor obtains the operating efficiency of the power management chip once for each rise of the input voltage. It should be noted that, the more the setting times in step S301, the smaller the setting range, and the working efficiency of the power management chip obtained under different input voltages tends to change continuously.

Fig. 4 is a flowchart illustrating a power management chip control method for obtaining chip operating efficiency according to another exemplary embodiment. In an embodiment, as shown in fig. 4, when obtaining the working efficiency of the power management chip in step S302, the method specifically includes:

step S401, obtaining input voltage, output voltage, input current and output current of the power management chip.

Optionally, the processor receives the input current and the output current obtained by the current detection component. The current detection assembly can acquire the input current and the output current of the power management chip in real time, and the processor responds to the increase of the input voltage of the power management chip and reads the input current and the output current acquired by the current detection assembly in real time.

And the analog-to-digital conversion component of the processor is directly connected with the input end and the output end of the power management chip, and the processor acquires input voltage and output voltage through the analog-to-digital conversion component. That is, the processor obtains digital signals representing the values of the input voltage and the output voltage.

And S402, acquiring the working efficiency of the power management chip according to the input voltage, the input current, the output voltage and the output current. And calculating the voltage and current values acquired by the processor to obtain the working efficiency of the power management chip. The working efficiency of the power management chip is the product of the input voltage and the input current and the ratio of the product of the output voltage and the output current.

With continuing reference to fig. 2, after step S201, the method further includes:

step S202, determining the input voltage corresponding to the maximum working efficiency in the first time period.

The operating efficiency of the plurality of power management chips acquired by the processor in step S201. In step S202, the maximum operating efficiency is determined among the operating efficiencies of the plurality of power management chips. And searching the corresponding input voltage according to the maximum working efficiency.

And step S203, taking the input voltage corresponding to the maximum working efficiency as the input voltage of the power management chip in a second time period.

And the second time period is the time period in the cycle except the first time period. And, the duration of the second time period can be set according to the use requirement, such as 10s, 20s, 30s, 40s, 50s, 60s and the like. Since the use state of the power management chip is constantly changed, the shorter the duration of the second time period is, the faster the frequency of updating the working efficiency of the power management chip in the second time period is. In this case, the maximum operating efficiency obtained in the first time period is closer to the actual maximum operating efficiency of the power management chip in the second time period.

By adopting the control method of the power management chip provided by the embodiment of the disclosure, in one period, the working efficiency of the power management chip is obtained every time when the input voltage is increased in the first time period, and then the input voltage corresponding to the maximum working efficiency in the first time period is determined. And taking the input voltage corresponding to the maximum working efficiency as the input voltage of the power management chip in the second time period. In this way, through the operating condition of real-time detection power management chip, guarantee power management chip with the work of highest work efficiency, reduce power management chip and generate heat.

The power management chip control method provided by the embodiment of the disclosure has strong operability, the hardware architecture is easy to implement, the working efficiency of the power management chip is effectively improved, and the technical defects of the related technology are overcome.

In another embodiment, before performing step S201, the method further includes: a charging trigger operation is detected to perform step S201 when the charging trigger operation is detected. In this way, in the process of charging the battery of the terminal equipment by the power management chip, the working efficiency of the power management chip is optimized, the heating of the power management chip in the charging process is reduced, and the user experience is optimized.

Based on the power management chip control method provided above, the embodiment of the present disclosure further provides a power management chip control device. The power management chip is applied to the terminal equipment and is matched with a processor of the terminal equipment. The power management chip control device is used in a plurality of cycles, wherein any cycle comprises a first time period and a second time period.

Fig. 5 is a block diagram illustrating a power management chip control apparatus according to an example embodiment. As shown in fig. 5, the power management chip control apparatus includes:

the obtaining module 501 is configured to control input voltage change of the power management chip in a first time period, and obtain working efficiency of the power management chip under different input voltages;

a determining module 502, configured to determine an input voltage corresponding to a maximum working efficiency in a first time period; and

the working module 503 is configured to use the input voltage corresponding to the maximum working efficiency as the input voltage of the power management chip in the second time period; the second time period is a time period within the cycle other than the first time period.

Fig. 6 is a block diagram illustrating an acquisition module in a power management chip control apparatus according to an example embodiment. In one embodiment, as shown in fig. 6, the obtaining module 501 includes:

the control unit 5011 is configured to control the input voltage to be raised successively by a set number of times and a set width in the first period. And

the obtaining unit 5012 is configured to obtain the operating efficiency of the power management chip in response to the input voltage increase.

In one embodiment, the obtaining unit 5012 is specifically configured to, when obtaining the operating efficiency of the power management chip: acquiring input voltage, output voltage, input current and output current of a power management chip; and obtaining the working efficiency according to the input voltage, the input current, the output voltage and the output current.

In one embodiment, the terminal device further includes a current detection component, and the obtaining unit 5012 is specifically configured to, when obtaining the input current and the output current: the input current and the output current detected by the current detection component are received.

In one embodiment, the processor includes analog-to-digital conversion components, and the obtaining unit 5012 is specifically configured to: and receiving the input voltage and the output voltage of the power management chip through the analog-to-digital conversion component.

In one embodiment, the power management chip control apparatus is applied to a charging process of a terminal device, and the apparatus further includes: and the receiving module is used for receiving a charging starting instruction before the obtaining module controls the input voltage of the power management chip to change in a first time period.

The embodiment of the disclosure provides a terminal device, which can apply the power management chip control method provided by the embodiment. Fig. 7 is a block diagram of a terminal device provided according to an example embodiment, and as shown in fig. 7, a terminal device 700 may include one or more of the following components: a processing component 702, a memory 704, a power component 706, a multimedia component 708, an audio component 710, an input/output (I/O) interface 712, a sensor component 714, a communication component 716, and an image capture component.

The processing component 702 generally refers to the overall operation of the terminal device 700, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing components 702 may include one or more processors 720 to execute instructions. Further, the processing component 702 may include one or more modules that facilitate interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate interaction between the multimedia component 708 and the processing component 702.

The memory 704 is configured to store various types of data to support operations at the terminal device 700. Examples of such data include instructions for any application or method operating on terminal device 700, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 704 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.

The power component 706 provides power to the various components of the terminal device 700. The power components 706 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the terminal device 700.

The multimedia component 708 comprises a screen providing an output interface between said terminal device 700 and the target object. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a target object. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

The audio component 710 is configured to output and/or input audio signals. For example, the audio component 710 includes a Microphone (MIC) configured to receive an external audio signal when the terminal device 700 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal may further be stored in the memory 704 or transmitted via the communication component 716. In some embodiments, audio component 710 also includes a speaker for outputting audio signals.

The I/O interface 712 provides an interface between the processing component 702 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc.

The sensor component 714 includes one or more sensors for providing various aspects of status assessment for the terminal device 700. For example, sensor component 714 can detect an open/closed state of terminal device 700, the relative positioning of components, such as a display and keypad of terminal device 700, sensor component 714 can also detect a change in the position of terminal device 700 or one of the components, the presence or absence of a target object in contact with terminal device 700, orientation or acceleration/deceleration of terminal device 700, and a change in the temperature of terminal device 700. As another example, the sensor assembly 714 also includes a light sensor disposed below the OLED display screen.

The communication component 716 is configured to facilitate wired or wireless communication between the terminal device 700 and other devices. The terminal device 700 may access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 further includes a Near Field Communication (NFC) module to facilitate short-range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra Wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the terminal device 700 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components.

In an exemplary embodiment, the disclosed embodiment also provides a readable storage medium, and the readable storage medium stores executable instructions. The executable instructions can be executed by a processor of the terminal equipment to realize the steps of the power management chip control method. The readable storage medium may be, among others, ROM, Random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, and the like.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A power management chip control method, wherein the power management chip cooperates with a processor of a terminal device, and the method is executed in a plurality of cycles, and in one of the cycles, the method comprises:

2. The method of claim 1, wherein the controlling the input voltage variation of the power management chip during the first period of time and obtaining the operating efficiency of the power management chip under different input voltages comprises:

3. The method of claim 2, wherein obtaining the operating efficiency of the power management chip comprises:

4. The method of claim 3, wherein the terminal device further comprises a current detection component, and wherein obtaining the input current and the output current of the power management chip comprises:

5. The method of claim 4, wherein the processor comprises an analog-to-digital conversion component, and wherein obtaining the input voltage and the output voltage of the power management chip comprises:

6. The method of claim 1, wherein prior to controlling the input voltage of the power management chip for the first period of time, the method further comprises:

7. A power management chip control device is characterized in that the power management chip is applied to a terminal device and is matched with a processor of the terminal device; the apparatus is used in a plurality of cycles, one of the cycles comprising a first time period and a second time period; the device comprises:

8. The apparatus of claim 7, wherein the obtaining module comprises:

the control unit is used for controlling the input voltage to gradually increase within the first time period by a set number of times and a set amplitude; and

and the acquisition unit is used for responding to the rise of the input voltage and acquiring the working efficiency of the power management chip.

9. The apparatus of claim 8, wherein the obtaining unit, when obtaining the working efficiency of the power management chip, is specifically configured to:

10. The apparatus according to claim 9, wherein the terminal device further comprises a current detection component, and the obtaining unit, when obtaining the input current and the output current, is specifically configured to:

11. The apparatus of claim 9, wherein the processor comprises an analog-to-digital conversion component, and wherein the obtaining unit, when obtaining the input voltage and the output voltage, is specifically configured to:

12. The apparatus of claim 7, wherein the apparatus is applied to a charging process of a terminal device, and the apparatus further comprises:

the detection module is used for detecting charging trigger operation so as to execute the control of the input voltage change of the power management chip in the first time period and acquire the working efficiency of the power management chip under the condition of different input voltages when the charging trigger operation is detected.

13. A terminal device, characterized in that the terminal device comprises:

a power management chip;

the processor is electrically connected with the power management chip;

a memory storing the processor-executable instructions;

the processor is configured to execute executable instructions in the memory to implement the steps of the method of any of claims 1-6.

14. The terminal device according to claim 13, further comprising a current detection component, wherein an input terminal of the current detection component is connected to the power management chip, and an output terminal of the current detection component is connected to the processor;

15. A readable storage medium having stored thereon executable instructions, wherein the executable instructions, when executed by a light sensor core, implement the steps of the method of any one of claims 1 to 6.