CN113345839A - Semiconductor element and manufacturing method thereof - Google Patents

Semiconductor element and manufacturing method thereof Download PDF

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Publication number
CN113345839A
CN113345839A CN202110231289.8A CN202110231289A CN113345839A CN 113345839 A CN113345839 A CN 113345839A CN 202110231289 A CN202110231289 A CN 202110231289A CN 113345839 A CN113345839 A CN 113345839A
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gate
dielectric layer
layer
forming
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Inventor
许智凯
傅思逸
邱淳雅
吴骐廷
陈金宏
林毓翔
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United Microelectronics Corp
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United Microelectronics Corp
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Priority claimed from US16/807,108 external-priority patent/US11062954B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, wherein the method for manufacturing the semiconductor element comprises the steps of firstly providing a substrate, arranging a fin-shaped structure on the substrate, then forming a first single diffusion isolation structure in the substrate and dividing the fin-shaped structure into a first part and a second part, then forming a first grid structure on the single diffusion isolation structure, forming an interlayer dielectric layer to surround the first grid structure, converting the first grid structure into a first metal grid, removing the first metal grid to form a first groove, and then forming a dielectric layer in the first groove.

Description

Semiconductor element and manufacturing method thereof
Technical Field
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of separating a fin structure to form a single diffusion isolation (SDB) structure.
Background
In recent years, as Field Effect Transistors (FETs) continue to shrink in size, the development of planar field effect transistor (planar) devices has faced the limit of fabrication processes. To overcome the limitation of the manufacturing process, it is becoming a mainstream trend to replace planar transistor devices with non-planar (non-planar) field effect transistor devices, such as Fin field effect transistor (Fin FET) devices. The three-dimensional structure of the finfet device can increase the contact area between the gate and the fin structure, and thus can further increase the control of the gate on the carrier channel region, thereby reducing the Drain Induced Barrier Lowering (DIBL) effect faced by the small-sized device and suppressing the Short Channel Effect (SCE). Furthermore, since the finfet device has a wider channel width for the same gate length, a doubled drain driving current can be obtained. Furthermore, the threshold voltage (threshold voltage) of the transistor device can be adjusted by adjusting the work function of the gate.
In the conventional fin field effect transistor device fabrication process, after shallow trench isolation is formed around the fin structure, a portion of the fin structure and the shallow trench isolation are usually removed by etching to form a recess, and then an insulator is filled to form a single diffusion isolation structure and separate the fin structure into two parts. However, there are still many problems in the matching of the single diffusion isolation structure and the metal gate in the current manufacturing process, and therefore how to improve the conventional finfet manufacturing process and structure is an important issue in the current technology.
Disclosure of Invention
One embodiment of the present invention discloses a method for fabricating a semiconductor device. Firstly, providing a substrate, arranging a fin-shaped structure on the substrate, then forming a first single diffusion isolation structure in the substrate and dividing the fin-shaped structure into a first part and a second part, then forming a first grid structure on the single diffusion isolation structure, forming an interlayer dielectric layer to surround the first grid structure, converting the first grid structure into a first metal grid, removing the first metal grid to form a first groove, and then forming a dielectric layer in the first groove.
Another embodiment of the present invention discloses a semiconductor device, which mainly comprises a single diffusion isolation structure for separating a fin structure into a first portion and a second portion, and an isolation structure disposed on the single diffusion isolation structure, wherein the isolation structure comprises a T-shaped cross section.
In another embodiment of the present invention, a semiconductor device is disclosed, which comprises a single-diffused isolation structure dividing a fin structure into a first portion and a second portion, an isolation structure disposed on the single-diffused isolation structure and a first spacer disposed beside the isolation structure, wherein a top surface of the first spacer is lower than a top surface of the isolation structure.
Drawings
Fig. 1 to 6 are schematic views illustrating a method for fabricating a semiconductor device according to an embodiment of the invention;
fig. 7 to 10 are schematic views illustrating a method of fabricating a semiconductor device according to an embodiment of the invention;
fig. 11 to 16 are schematic views illustrating a method of fabricating a semiconductor device according to an embodiment of the invention;
fig. 17 to 20 are schematic views illustrating a method of fabricating a semiconductor device according to an embodiment of the invention.
Description of the main elements
12 base
14 fin structure
16 shallow trench isolation
18 single diffusion isolation structure
20 first part
22 second part
24 gate structure
26 gate structure
28 gate structure
30 gate structure
32 gate structure
34 gate structure
36 gate structure
38 gate structure
40: gate structure
42 gate dielectric layer
44 layer of gate material
45 hard mask
46 hard mask
48 spacer
50 source/drain region
54 interlayer dielectric layer
56 patterned mask
58 opening of the container
60 opening of the container
62 first groove
64 second groove
66 dielectric layer
68 single diffusion isolation structure
70 isolation structure
72 lower half part
74 upper half part
76 dielectric layer
78 dielectric layer with high dielectric constant
80 work function metal layer
82 low resistance metal layer
84 mask layer
86 patterning mask
88 opening
90: groove
92 contact hole etch stop layer
94 dielectric layer
96 single diffusion isolation structure
98 lower half part
100 the upper half part
102 groove
104 patterned mask
106 opening (C)
108 opening (C)
110: groove
112, groove
114 masking layer
116 dielectric layer
118 isolation structure
120 isolation structure
122U-shaped part
124: L-shaped part
132 cover layer
134 patterning mask
136: groove
138 groove
140 dielectric layer
142 isolation structure
144 isolation structure
Detailed Description
Referring to fig. 1 to 6, fig. 1 to 6 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein fig. 1 is a top view illustrating a semiconductor device according to an embodiment of the present invention, fig. 2 to 6 are schematic diagrams illustrating a cross-section of the semiconductor device along a cut line AA 'in fig. 1 in a left half, and fig. 2 to 6 are schematic diagrams illustrating a cross-section of the semiconductor device along a cut line BB' in fig. 1 in a right half. As shown in fig. 1-2, a substrate 12, such as a silicon substrate or a Silicon On Insulator (SOI) substrate, is provided, and at least one fin structure 14 is formed on the substrate 12. It should be noted that, although nine fin structures 14 are exemplified as the fin structures 14 disposed on the substrate 12 in the embodiment, the number of the fin structures 14 can be arbitrarily adjusted according to the product requirements, and is not limited thereto.
In accordance with a preferred embodiment of the present invention, fin structure 14 is preferably formed by a Sidewall Image Transfer (SIT) technique, which generally includes: a layout pattern is provided to a computer system and is properly calculated to define a corresponding pattern in a photomask. Subsequently, a plurality of patterned sacrificial layers with equal distance and equal width are formed on the substrate through photoetching and etching processes, so that the respective appearances of the sacrificial layers are in a strip shape. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layer. The sacrificial layer is then removed and an etching process is performed under the spacer to transfer the spacer pattern into the substrate, followed by a fin cut process (fin cut) to obtain a desired patterned structure, such as a patterned stripe fin.
In addition, the fin structure 14 may be formed by forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 to form the fin structure 18 through an etching process. Alternatively, the fin structure 14 may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and growing a semiconductor layer, such as a silicon germanium semiconductor layer, on the substrate 12 exposed by the patterned hard mask layer by an epitaxial process, wherein the semiconductor layer serves as the corresponding fin structure 14. These embodiments for forming the fin structure 14 are all within the scope of the present invention.
A Shallow Trench Isolation (STI) 16 is then formed around the fin structure 14. In the present embodiment, the shallow trench isolation 16 is formed by first forming a silicon oxide layer on the substrate 12 and completely covering the fin structure 14 by a Flowable Chemical Vapor Deposition (FCVD) process. Then, a Chemical Mechanical Polishing (CMP) process is used in combination with an etching process to remove a portion of the silicon oxide layer, so that the remaining silicon oxide layer is lower than the surface of the fin structure 14 to form the shallow trench isolation 16.
A single diffusion isolation (SDB) 18 is then formed in the substrate 12 to separate each fin 14 into a first portion 20 and a second portion 22. In the present embodiment, the method for forming the single-diffusion isolation structure 18 may first perform a photolithography and etching process to remove a portion of the fin structure 14 to form a recess, form a dielectric layer in the recess, and then perform a planarization process, such as a chemical mechanical polishing and/or an etch-back process, to remove a portion of the dielectric layer so that the top of the remaining dielectric layer is slightly lower than the top of the fin structure 14. As shown in fig. 1, the fin structures 14 preferably extend along a first direction (e.g., the X-direction) and the single-diffused isolation structures 18 preferably extend along a second direction (e.g., the Y-direction) perpendicular to the first direction and separate each fin structure 14 into two portions, including a first portion 20 on the left side of the single-diffused isolation structure 18 and a second portion 22 on the right side of the single-diffused isolation structure 18.
It should be noted that although the single diffusion isolation structure 18 is formed after the shallow trench isolation 16 is formed in this embodiment, the sequence is not limited thereto, and the single diffusion isolation structure 18 and the shallow trench isolation 16 may be formed simultaneously according to an embodiment of the present invention. For example, if the single diffusion isolation structure 18 and the shallow trench isolation 16 are formed simultaneously, both preferably comprise a dielectric material such as silicon oxide. However, if the single diffusion isolation structure 18 is formed after the shallow trench isolation 16 is formed, the shallow trench isolation 16 preferably comprises silicon oxide and the single diffusion isolation structure 18 may comprise silicon oxide or silicon nitride. In other words, the single diffusion isolation structure 18 and the shallow trench isolation 16 may comprise the same or different materials according to the manufacturing process or product requirements, and both may be selected from the group consisting of silicon oxide and silicon nitride, which are all within the scope of the present invention.
Next, gate structures 24, 26, 28, 30, 32, 34, 36, 38, 40 or dummy gates are formed on the fin structure 14 and the shallow trench isolation 16, wherein the left portion of fig. 2 discloses the gate structures 30 and 34 on the fin structure 14 and the gate structure 32 directly above the single diffusion isolation structure 18, and the right portion of fig. 2 discloses the gate structure 36 at the edge of the fin structure 14 and the gate structure 38 directly above the shallow trench isolation 16. In the present embodiment, the gate structures 24, 26, 28, 30, 32, 34, 36, 38, and 40 can be fabricated by a gate first (gate first) fabrication process, a gate last (gate last) fabrication process, a high-k first (high-k first) fabrication process, and a high-k last (high-k last) fabrication process according to the fabrication process requirements. Taking the post-high-k dielectric layer fabrication process of the present embodiment as an example, a gate dielectric layer or dielectric layer, a gate material layer made of polysilicon, and at least one selective hard mask may be sequentially formed on the substrate 12, a patterned photoresist (not shown) may be used as a mask to perform a pattern transfer process, a portion of the hard mask, a portion of the gate material layer, and a portion of the gate dielectric layer may be removed by a single etching step or a sequential etching step, and then the patterned photoresist may be stripped to form gate structures 24, 26, 28, 30, 32, 34, 36, 38, 40 made up of the patterned gate dielectric layer 42, the patterned gate material layer 44, the hard mask 45, and another hard mask 46 on the fin structure 14, the single diffusion isolation structure 18, and the shallow trench isolation 16.
In the present embodiment, the dual layer hard mask structure disposed on the patterned gate material layer 44 includes a hard mask 45 and a hard mask 46, wherein the hard mask 45 preferably comprises silicon oxide and the hard mask 46 preferably comprises silicon nitride. Without being limited to this combination of materials, the hard masks 45, 46 may comprise different materials and both may be selected from the group consisting of silicon oxide and silicon nitride in accordance with other embodiments of the present invention, which are within the scope of the present invention.
At least one spacer 48 is then formed on sidewalls of each of the gate structures 24, 26, 28, 30, 32, 34, 36, 38, and 40, a source/drain region 50 and/or an epitaxial layer (not shown) is formed in the fin structure 14 and/or the substrate 12 on both sides of the spacer 48, and a metal silicide (not shown) is selectively formed on a surface of the source/drain region 50 and/or the epitaxial layer. In the present embodiment, the spacer 48 may be a single spacer or a composite spacer, for example, the details may include an offset spacer and a main spacer. Wherein the offset spacer and the main spacer may comprise the same or different materials, and both may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source/drain regions 50 may comprise different dopants depending on the conductivity type of the transistors being provided, for example, P-type dopants or N-type dopants may be included. An optional contact hole etch stop layer (not shown) may then be formed over the gate structures 24, 26, 28, 30, 32, 34, 36, 38, 40 and the shallow trench isolation 16, and an interlayer dielectric layer 54 may be formed over the contact hole etch stop layer.
Then, as shown in fig. 3, a planarization process is performed, such as a chemical mechanical polishing process, to remove a portion of the ild layer 54, the hard mask 46 and a portion of the spacer 48 and to make the top surface of the hard mask 45 flush with the top surface of the ild layer 54. A patterned mask 56 is then formed over the ild 54, wherein the patterned mask 56 includes openings 58, 60 exposing the tops of the gate structures 32, 38. In the present embodiment, the patterned mask 56 may comprise a three-layer structure of an Organic Dielectric Layer (ODL), a silicon-containing hard mask and anti-reflective coating (SHB) layer, and a patterned photoresist, and the step of forming the openings 58, 60 in the patterned mask 56 may be performed by removing a portion of the silicon-containing hard mask and the anti-reflective coating and a portion of the organic dielectric layer using the patterned photoresist as a mask.
An etch process is then performed using patterned mask 56 as a mask to remove hard mask 45 and patterned gate material layer 44 of gate structures 32 and 38 to form first recess 62 exposing single diffusion isolation structure 18 and second recess 64 exposing shallow trench isolation 16. As shown in fig. 2-3, the first recess 62 formed at this stage preferably extends along the Y-direction as does the underlying single-diffused isolation structure 18, while the second recess 64 formed preferably extends along the X-direction and separates the gate structures 24, 26, 28, 30 and the gate structures 34, 36, 38, 40 into smaller segments.
It is noted that the first and second recesses 62 and 64 may comprise the same depth or different depths depending on the underlying single diffusion isolation structures 18 and shallow trench isolations 16. For example, if the single diffusion isolation structure 18 is made of silicon nitride and the shallow trench isolation 16 is made of silicon oxide, the bottom surface of the first recess 62 may be selected to be slightly lower or slightly higher than the bottom surface of the second recess 64 depending on the etchant used in the etching process. If the single diffusion isolation structure 18 and the shallow trench isolation 16 comprise the same material, such as silicon oxide, the bottom of the first recess 62 and the bottom of the second recess 64 are preferably aligned.
Then, as shown in fig. 4, a dielectric layer 66 is formed in the first recess 62 and the second recess 64 and completely fills the first recess 62 and the second recess 64. In the present embodiment, the dielectric layer 66 may comprise a dielectric material such as, but not limited to, silicon oxide, silicon oxycarbide (SiOCN), or silicon nitride.
As shown in fig. 5, a planarization process, such as a chemical mechanical polishing process, is then performed to remove a portion of the dielectric layer 66, the hard mask 45, or even a portion of the interlayer dielectric layer 54 and a portion of the contact hole etch stop layer to form another single diffusion isolation structure 68 between the gate structures 30 and 34 and an isolation structure 70 over the shallow trench isolation 16 beside the gate structure 36, wherein the top surface of the single diffusion isolation structure 68 is preferably aligned with the top surfaces of the isolation structure 70 and the interlayer dielectric layer 54.
In the present embodiment, the new single-diffusion isolation structure 68 comprises a lower half 72 embedded in the fin structure 14 and an upper half 74 disposed above the lower half 72, wherein the upper half 74, the lower half 72, the isolation structure 70 and the sti 16 may be selected from the group consisting of silicon oxide, silicon oxycarbide and silicon nitride, the upper half 74 and the lower half 72 may comprise the same or different materials, the sti 16 and the isolation structure 70 may comprise the same or different materials, and the sti 16 and the lower half 72 may comprise the same or different materials.
For example, the bottom half 72 of the single diffusion isolation structure 68 may comprise silicon nitride while the top half 74 may comprise silicon oxide, the bottom half 72 may comprise silicon oxide while the top half 74 may comprise silicon nitride or silicon oxycarbide, both the bottom half 72 and the top half 74 may comprise silicon oxide or silicon nitride, the STI 16 may comprise silicon oxide while the isolation structure 70 may comprise silicon oxycarbide, the STI 16 may comprise silicon oxide while the bottom half 72 comprises silicon nitride and the top half 74 and the isolation structure 70 comprise silicon oxycarbide, or the STI 16 and the lower half 72 are made of silicon oxide and the upper half 74 and the isolation structure 70 are made of silicon nitride or silicon oxycarbide, all of which are within the scope of the present invention.
As shown in fig. 6, a metal gate replacement process is then performed after the formation of new single-diffusion isolation structures 68 and isolation structures 70 to convert the gate structures 24, 26, 28, 30, 32, 34, 36, 38, 40 into metal gates. For example, a selective dry or wet etching process, such as ammonia (NH), may be performed4OH) or tetramethylammonium hydroxide (tetramethylammonium)Ammonium Hydroxide (TMAH) or the like to remove the gate material layer 44 and even the gate dielectric layer 42 from the gate structures 24, 26, 28, 30, 32, 34, 36, 38, 40, thereby forming a recess (not shown) in the interlayer dielectric layer 54.
Then, a selective dielectric layer 76 or a gate dielectric layer, a high-k dielectric layer 78, a work function metal layer 80 and a low-resistance metal layer 82 are sequentially formed in the recess, and a planarization process is performed, such as removing a portion of the low-resistance metal layer 82, a portion of the work function metal layer 80 and a portion of the high-k dielectric layer 78 by CMP, to form a metal gate. Taking the gate structure fabricated by the post-high-k dielectric layer fabrication process as an example in this embodiment, each metal gate formed preferably includes a dielectric layer 76 or gate dielectric layer, a U-shaped high-k dielectric layer 78, a U-shaped work function metal layer 80, and a low-resistance metal layer 82.
In the present embodiment, the high-k dielectric layer 78 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO)2) Hafnium silicate oxide (HfSiO)4) Hafnium silicate oxynitride (HfSiON), aluminum oxide (Al)2O3) Lanthanum oxide (La)2O3) Tantalum oxide (Ta), and a process for producing the same2O5) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) Strontium titanate (SrTiO), strontium titanate oxide (srf)3) Zirconium silicate oxide (ZrSiO)4) Hafnium zirconate (HfZrO) oxide4) Strontium bismuth tantalum oxide (SrBi)2Ta2O9SBT), lead zirconate titanate (PbZr)xTi1-xO3PZT), barium strontium titanate (Ba)xSr1- xTiO3BST), or combinations thereof.
Work function metal layer 80 is preferably used to adjust the work function of the metal gate formed, making it suitable for either N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 80 may be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 80 may be made of a metal material having a work function of 4.8eV to 5.2eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 80 and the low resistance metal layer 82, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like. The low resistance metal layer 82 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), and combinations thereof.
Referring to fig. 7 to 10, fig. 7 to 10 are schematic views illustrating a method for fabricating a semiconductor device along a direction of a cut line AA' in fig. 1 according to an embodiment of the present invention. As shown in fig. 7, the present invention may first form the single-diffused isolation structure 18 in the substrate 12 to separate the fin structure 14 into the first portion 20 and the second portion 22 according to the manufacturing process of fig. 2, and then form the gate structures 30 and 34 on the fin structure 14 and the gate structure 32 directly above the single-diffused isolation structure 18. Wherein each gate structure 30, 32, 34 includes a patterned gate dielectric layer 42, a patterned gate material layer 44, and hard masks 45, 46, spacers 48 are disposed on sidewalls of each gate structure 30, 32, 34, source/drain regions 50 and/or epitaxial layers are disposed on the fin structure 14 on both sides of the spacers 48, and optional silicide (not shown) may be disposed on the surface of the source/drain regions 50. In addition, the material composition of the spacers 48 and the source/drain regions 50 in this embodiment can be similar to that of the previous embodiment, and will not be described herein.
A mask layer 84 is then formed around the gate structures 30, 32, 34 after the source/drain regions 50 are formed, and a patterned mask 86, such as a patterned photoresist, is formed over the gate structures 30, 32, 34 and the mask layer 84, wherein the patterned mask 86 includes an opening 88 exposing the hard mask 46 disposed over the gate structure 32 and the single diffusion isolation structure 18. In the present embodiment, the mask layer 84 preferably includes a bottom anti-reflection layer, but is not limited thereto.
As shown in fig. 8, an etching process is then performed to remove the hard masks 45 and 46 of the gate structure 32, the patterned gate material layer 44 and the patterned gate dielectric layer 42 by using the patterned mask 86 as a mask to form a recess 90 exposing the single-diffusion isolation structure 18 thereunder. The patterned mask 86 is then removed and another etch process is performed without forming additional masks to completely remove the mask layer 84 or bottom antireflective layer and expose the gate structures 30, 34 on the fin structure 14
As shown in fig. 9, after removing mask layer 84, a contact hole etch stop layer 92 is formed in recess 90 and on the surfaces of gate structures 30, 34 and fin structure 14, and a dielectric layer 94 is formed as an interlayer dielectric layer on gate structures 30, 34 and contact hole etch stop layer 92 to fill recess 90. In the present embodiment, contact hole etch stop layer 92 preferably comprises a stressed dielectric material such as, but not limited to, silicon nitride or silicon oxycarbide and dielectric layer 94 preferably comprises an oxide such as, but not limited to, silicon dioxide.
Thereafter, as shown in fig. 10, a planarization process, such as a chemical mechanical polishing process, is performed to remove a portion of the dielectric layer 94 and a portion of the contact hole etch stop layer 92 to form another single diffusion isolation structure 96 between the gate structures 30 and 34, wherein the top surface of the single diffusion isolation structure 96 is preferably aligned with the top surface of the dielectric layer 94.
In the present embodiment, the single-diffusion isolation structure 96 includes a lower half 98 embedded in the fin structure 14 and an upper half 100 disposed on the lower half 98, wherein the contact hole etch stop layer 92 is disposed between the upper half 100 and the lower half 92. As with the previous embodiments, the top half 100 and bottom half 92 may be selected from the group consisting of silicon oxide, silicon oxycarbide, and silicon nitride while the top half 100 and bottom half 92 may comprise the same or different materials.
A metal gate replacement process is then performed after the formation of the new single diffusion isolation structure 96 to convert the gate structures 30, 34 into metal gates. Examples of such applications areFor example, a selective dry or wet etching process, such as ammonia (NH), may be performed4OH) or Tetramethylammonium Hydroxide (TMAH) to remove the gate material layer 44 and even the gate dielectric layer 42 in the gate structures 30 and 34, so as to form a recess (not shown) in the dielectric layer 94.
Then, a selective dielectric layer 76 or a gate dielectric layer, a high-k dielectric layer 78, a work function metal layer 80 and a low-resistance metal layer 82 are sequentially formed in the recess, and a planarization process is performed, such as removing a portion of the low-resistance metal layer 82, a portion of the work function metal layer 80 and a portion of the high-k dielectric layer 78 by CMP, to form a metal gate. As with the previous embodiments, each metal gate fabricated by the post-high-k dielectric layer fabrication process of the present embodiment preferably includes a dielectric layer 76 or gate dielectric layer, a U-shaped high-k dielectric layer 78, a U-shaped work function metal layer 80, and a low-resistance metal layer 82.
Referring to fig. 1 to fig. 2 and fig. 11 to fig. 16 simultaneously, fig. 1 to fig. 2 and fig. 11 to fig. 16 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein fig. 1 is a top view illustrating a semiconductor device fabricated according to an embodiment of the present invention, fig. 2 and fig. 11 to fig. 16 are schematic diagrams illustrating a cross-section of the semiconductor device fabricated along a cut line AA 'in fig. 1 in a left half portion, and fig. 2 and fig. 11 to fig. 16 are schematic diagrams illustrating a cross-section of the semiconductor device fabricated along a cut line BB' in fig. 1 in a right half portion. As shown in fig. 11, a planarization process is performed after the formation of the interlayer dielectric layer 54 in fig. 2, such as a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer 54, and a metal gate replacement process is performed to convert the gate structures 24, 26, 28, 30, 32, 34, 36, 38, and 40 into metal gates. For example, a selective dry or wet etching process, such as ammonia (NH), may be performed4OH) or Tetramethylammonium Hydroxide (TMAH) to remove the hard masks 45, 46, the gate material layer 44 and even the gate dielectric layer 42 in the gate structures 24, 26, 28, 30, 32, 34, 36, 38, 40 to form a plurality of recesses in the interlayer dielectric layer 54(not shown).
Then, a selective dielectric layer 76 or a gate dielectric layer, a high-k dielectric layer 78, a work function metal layer 80 and a low-resistance metal layer 82 are sequentially formed in the recess, and a planarization process is performed, such as removing a portion of the low-resistance metal layer 82, a portion of the work function metal layer 80 and a portion of the high-k dielectric layer 78 by CMP, to form the gate structure 24, 26, 28, 30, 32, 34, 36, 38, 40 formed by the metal gate. Taking the gate structure fabricated by the post-high-k dielectric layer fabrication process as an example in this embodiment, each metal gate formed preferably includes a dielectric layer 76 or gate dielectric layer, a U-shaped high-k dielectric layer 78, a U-shaped work function metal layer 80, and a low-resistance metal layer 82. For simplicity, the following processes are only illustrated with the gate structures 30, 32, 34, 36, 38 along the cross-sections of the cut lines AA 'and BB'.
In the present embodiment, the high-k dielectric layer 78 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO)2) Hafnium silicate oxide (HfSiO)4) Hafnium silicate oxynitride (HfSiON), aluminum oxide (Al)2O3) Lanthanum oxide (La)2O3) Tantalum oxide (Ta), and a process for producing the same2O5) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) Strontium titanate (SrTiO), strontium titanate oxide (srf)3) Zirconium silicate oxide (ZrSiO)4) Hafnium zirconate (HfZrO) oxide4) Strontium bismuth tantalum oxide (SrBi)2Ta2O9SBT), lead zirconate titanate (PbZr)xTi1-xO3PZT), barium strontium titanate (Ba)xSr1- xTiO3BST), or combinations thereof.
Work function metal layer 80 is preferably used to adjust the work function of the metal gate formed, making it suitable for either N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 80 may be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 80 may be made of a metal material having a work function of 4.8eV to 5.2eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 80 and the low resistance metal layer 82, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like. The low resistance metal layer 82 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), and combinations thereof.
After forming the metal gates, an etching process is performed to remove portions of the gate structures 30, 32, 34, 36, 38 directly using the interlayer dielectric layer 54 as a mask to form a plurality of recesses 102 in the interlayer dielectric layer 54 and directly over the remaining metal gates or gate structures 30, 32, 34, 36, 38, as shown in fig. 12.
As shown in fig. 13, a patterned mask 104, such as a patterned photoresist, is then formed over the gate structures 30, 34, 36 and the interlayer dielectric layer 54 and fills the recess 102 above the gate structures 30, 34, 36, wherein the patterned mask 104 includes openings 106, 108 exposing the remaining gate structures 32, 38 and even the top of the interlayer dielectric layer 54 beside the gate structures 32, 38.
As shown in fig. 14, an etching process is then performed to remove portions of the spacers 48 and the remaining gate structures 32 and 38 directly above the single-diffusion isolation structures 18 and the shallow trench isolations 16 by using the patterned mask 104 as a mask to form recesses 110 and 112 in the interlayer dielectric layer 54, wherein the recesses 10 expose the underlying single-diffusion isolation structures 18 and the recesses 112 expose the surface of the shallow trench isolations 16. The patterned mask 104 is then removed. It should be noted that the etching process performed at this stage simultaneously removes a portion of the spacer 48 directly above the single-diffused isolation structure 18 such that the top surface of the remaining spacer 48, except for the top surface which is flat, is slightly lower than the top surface of the interlayer dielectric layer 54 and the top surface of the spacer 48 adjacent to the gate structures 30, 34, and 36, and the bottom surface of the spacer 48 directly above the single-diffused isolation structure 18 is preferably aligned with the bottom surface of the source/drain region 50 and/or the top surface of the single-diffused isolation structure 18.
As shown in fig. 15, a capping layer 114 is then formed on the ild layer 54 and fills the recess 102 and the recesses 110, 112 directly above the gate structures 30, 34, 36. It should be noted that since the depth of the recesses 110, 112 directly above the single-diffused isolation structures 18 and the shallow trench isolations 16 is much greater than the depth of the recess 102 directly above the gate structures 30, 34, 36, the masking layer 114 is preferably deposited such that the masking layer 114 fills the recess 102 directly above the gate structures 30, 34, 36 but only partially fills the recesses 110, 112 directly above the single-diffused isolation structures 18 and the shallow trench isolations 16. A dielectric layer 116 is then formed over the cap layer 114 and fills the recesses 110, 112 above the single-diffused isolation structures 18 and the shallow trench isolations 16. In the present embodiment, the capping layer 114 and the dielectric layer 116 preferably comprise different dielectric materials, wherein the capping layer 114 preferably comprises silicon nitride and the dielectric layer 116 preferably comprises silicon oxide, but not limited thereto.
As shown in fig. 16, a planarization process, such as a chemical mechanical polishing process, is then performed to remove a portion of the dielectric layer 116, a portion of the capping layer 114, or even a portion of the interlayer dielectric layer 54, so that the remaining dielectric layer 116 and the top of the capping layer 114 are aligned with the top surface of the interlayer dielectric layer 54. At this stage, the remaining dielectric layer 116 and the cap layer 114 directly over the single-diffused isolation structure 18 form an isolation structure 118, and the remaining dielectric layer 116 and the cap layer 114 over the shallow trench isolation 16 form another isolation structure 120. Thus, the fabrication of the semiconductor device according to an embodiment of the present invention is completed.
Referring to fig. 16 again, fig. 16 further discloses a structural schematic diagram of the semiconductor device according to an embodiment of the invention. As shown in fig. 6, the semiconductor device comprises a single diffusion isolation structure 18 separating the fin structure 14 into a first portion 20 and a second portion 22, a shallow trench isolation 16 surrounding the fin structure 14, an isolation structure 118 disposed on the single diffusion isolation structure 18, a spacer 48 surrounding the isolation structure 118, another isolation structure 120 disposed on the shallow trench isolation 16, and another spacer 48 surrounding the isolation structure 120, wherein each of the isolation structures 118, 120 has a T-shaped cross-section.
More specifically, each isolation structure 118, 120 comprises a cap layer 114 disposed on the single-diffusion isolation structure 18 and a dielectric layer 116 disposed on the cap layer 114, wherein the cap layer 114 comprises a U-shaped portion 122 and two L-shaped portions 124 connecting the U-shaped portion 122, the sidewalls of the cap layer 114 or the L-shaped portions 124 are preferably aligned with the sidewalls of the spacers 48, the dielectric layer 116 itself comprises a T-shaped cross-section, and the cap layer 114 and the dielectric layer 116 may together form another T-shaped cross-section. In addition, the masking layer 114 and the dielectric layer 116 in the present embodiment are preferably made of different dielectric materials, for example, the masking layer 114 preferably comprises silicon nitride and the dielectric layer 116 comprises silicon oxide.
Referring to fig. 1 to fig. 2 and fig. 17 to fig. 20, fig. 1 to fig. 2 and fig. 17 to fig. 20 are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein fig. 1 is a top view illustrating a semiconductor device fabricated according to an embodiment of the present invention, fig. 2 and fig. 17 to fig. 20 are schematic diagrams illustrating a cross-section of the semiconductor device fabricated along a cut line AA 'in fig. 1 in a left half, and fig. 2 and fig. 17 to fig. 20 are schematic diagrams illustrating a cross-section of the semiconductor device fabricated along a cut line BB' in fig. 1 in a right half. As shown in fig. 17, a planarization process is performed after the formation of the interlayer dielectric layer 54 in fig. 2, such as a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer 54, and a metal gate replacement process is performed to convert the gate structures 24, 26, 28, 30, 32, 34, 36, 38, and 40 into metal gates. For example, a selective dry or wet etching process, such as ammonia (NH), may be performed4OH) or Tetramethylammonium Hydroxide (TMAH) to remove the hard masks 45, 46, the gate material layer 44 and even the gate dielectric layer 42 in the gate structures 24, 26, 28, 30, 32, 34, 36, 38, 40, so as to form a plurality of recesses (not shown) in the interlayer dielectric layer 54.
Then, a selective dielectric layer 76 or a gate dielectric layer, a high-k dielectric layer 78, a work function metal layer 80 and a low-resistance metal layer 82 are sequentially formed in the recess, and a planarization process is performed, such as removing a portion of the low-resistance metal layer 82, a portion of the work function metal layer 80 and a portion of the high-k dielectric layer 78 by CMP, to form the gate structure 24, 26, 28, 30, 32, 34, 36, 38, 40 formed by the metal gate. Taking the gate structure fabricated by the post-high-k dielectric layer fabrication process as an example in this embodiment, each metal gate formed preferably includes a dielectric layer 76 or gate dielectric layer, a U-shaped high-k dielectric layer 78, a U-shaped work function metal layer 80, and a low-resistance metal layer 82. For simplicity, the following processes are only illustrated with the gate structures 30, 32, 34, 36, 38 along the cross-sections of the cut lines AA 'and BB'.
In the present embodiment, the high-k dielectric layer 78 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO)2) Hafnium silicate oxide (HfSiO)4) Hafnium silicate oxynitride (HfSiON), aluminum oxide (Al)2O3) Lanthanum oxide (La)2O3) Tantalum oxide (Ta), and a process for producing the same2O5) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) Strontium titanate (SrTiO), strontium titanate oxide (srf)3) Zirconium silicate oxide (ZrSiO)4) Hafnium zirconate (HfZrO) oxide4) Strontium bismuth tantalum oxide (SrBi)2Ta2O9SBT), lead zirconate titanate (PbZr)xTi1-xO3PZT), barium strontium titanate (Ba)xSr1- xTiO3BST), or combinations thereof.
Work function metal layer 80 is preferably used to adjust the work function of the metal gate formed, making it suitable for either N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 80 may be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but not limited thereto; if the transistor is a P-type transistor, the work function metal layer 80 may be made of a metal material having a work function of 4.8eV to 5.2eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 80 and the low resistance metal layer 82, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and the like. The low resistance metal layer 82 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), and combinations thereof.
Then, portions of the gate structures 30, 32, 34, 36, and 38 are removed to form a plurality of recesses in the interlayer dielectric layer 54, and a cap layer 132 or a hard mask is formed over the remaining gate structures 30, 32, 34, 36, and 38 such that the top surface of the cap layer 132 is aligned with the top surface of the interlayer dielectric layer 54. In the present embodiment, the cap layer 132 preferably comprises a dielectric material such as, but not limited to, silicon nitride.
As shown in fig. 18, a patterned mask 134, such as a patterned photoresist, is then formed on the gate structures 30, 34, 36 and the interlayer dielectric layer 54, wherein the patterned mask 134 includes openings (not shown) exposing the cap layer 132 directly above the single diffusion isolation structures 18 and the shallow trench isolations 16. An etching process is then performed using the patterned mask 134 as a mask to remove portions of the spacers 48, the cap layer 132 over the gate structures 32, 38, and the remaining gate structures 32, 38 over the single-diffused isolation structures 18 and the shallow trench isolations 16. Recesses 136, 138 are formed in the ild layer 54, wherein the recesses 136, 138 expose the underlying monodiffusion isolation structures 18 and the recess 138 exposes the surface of the shallow trench isolation 16 and the bottom surfaces of the recesses 136, 138 are lower than the bottom surfaces of the gate structures 30, 34, 36 that are located next to and above the fin 14. As in the previous embodiments, the etching process performed at this stage simultaneously removes a portion of the spacers 48 directly above the single-diffused isolation structures 18 such that the top surfaces of the remaining spacers 48, except for the top surfaces that are flat, are slightly lower than the top surfaces of the interlayer dielectric layer 54 and the top surfaces of the spacers 48 adjacent to the gate structures 30, 34, and 36, and the bottom surfaces of the remaining spacers 48 directly above the single-diffused isolation structures 18 are preferably aligned with the bottom surfaces of the source/drain regions 50 and/or the top surfaces of the single-diffused isolation structures 18.
As shown in fig. 19, patterned mask 134 is then removed and a dielectric layer 140 is deposited over gate structures 30, 34, 36 and interlayer dielectric layer 54 and fills recesses 136, 138. In the present embodiment, the dielectric layer 140 and the interlayer dielectric layer 54 may comprise the same or different materials, wherein both may comprise, but are not limited to, silicon oxide, silicon oxynitride, or Tetraethoxysilane (TEOS).
As shown in fig. 20, a planarization process, such as a chemical mechanical polishing process, may then be optionally performed to remove a portion of the dielectric layer 140 to form an isolation structure 142 on the single-diffusion isolation structure 18 and another isolation structure 144 on the shallow trench isolation 16, wherein the top surfaces of the isolation structures 142, 144 are preferably aligned with the top surface of the interlayer dielectric layer 54. Thus, the fabrication of the semiconductor device according to an embodiment of the present invention is completed.
Referring to fig. 20 again, fig. 20 further discloses a structural schematic diagram of the semiconductor device according to an embodiment of the invention. As shown in fig. 20, the semiconductor device comprises a single diffusion isolation structure 18 separating the fin structure 14 into a first portion 20 and a second portion 22, a shallow trench isolation 16 surrounding the fin structure 14, an isolation structure 142 disposed on the single diffusion isolation structure 18, a spacer 48 surrounding the isolation structure 142, another isolation structure 144 disposed on the shallow trench isolation 16, and another spacer 48 surrounding the isolation structure 144, wherein each isolation structure 142, 144 has a T-shaped cross section.
In detail, each isolation structure 142, 144 comprises a dielectric layer 140 disposed on the single-diffused isolation structure 18 and the shallow trench isolation 16, wherein the dielectric layer 140 has a T-shaped cross section and the sidewalls of the isolation structures 142, 144 are preferably aligned with the sidewalls of the spacer 48. In addition, the bottom surface of the spacer 48 surrounding the isolation structures 142, 144 is preferably lower than the bottom surface of the spacer 48 surrounding the gate structures 30, 34, 36, and the top surface of the spacer 48 surrounding the isolation structures 142, 144 is lower than the top surface of the spacer 48 surrounding the gate structures 30, 34, 36 and higher than the bottom surface of the spacer 48 surrounding the gate structures 30, 34, 36. In addition, the cap layer 140 and the interlayer dielectric layer 54 may be made of the same or different dielectric materials in the present embodiment, such as silicon oxide, silicon oxynitride, Tetraethoxysilane (TEOS), or a combination thereof.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims (20)

1. A method of fabricating a semiconductor device, comprising:
providing a substrate, wherein a fin-shaped structure is arranged on the substrate;
forming a single diffusion isolation structure in the substrate and dividing the fin structure into a first part and a second part;
forming a first gate structure on the single diffusion isolation structure;
forming an interlayer dielectric layer surrounding the first gate structure;
converting the first gate structure into a first metal gate;
removing the first metal gate to form a first groove; and
a dielectric layer is formed in the first recess.
2. The method of claim 1, further comprising:
forming a second gate structure beside the first gate structure and on the fin structure;
forming the interlayer dielectric layer to surround the first gate structure and the second gate structure;
converting the first gate structure and the second gate structure into a first metal gate and a second metal gate;
removing part of the second metal grid to form a second groove;
removing the first metal gate to form the first groove;
forming a cover layer in the first groove and the second groove;
forming the dielectric layer in the first groove; and
planarizing the dielectric layer and the cap layer.
3. The method of claim 2, wherein said first gate structure bottom surface is lower than said second gate structure bottom surface.
4. The method of claim 2, wherein the first recess bottom surface is lower than the second recess bottom surface.
5. The method of claim 2, further comprising:
forming a first spacer surrounding the first gate structure;
forming the interlayer dielectric layer to surround the first gate structure;
converting the first gate structure into the first metal gate;
removing the first metal gate and a portion of the first spacer to form the first recess;
forming the cover layer on the first spacer; and
forming the dielectric layer on the mask layer.
6. The method of claim 5, wherein a top surface of said first spacer is lower than a top surface of said ILD layer.
7. The method of claim 1, further comprising:
forming a second gate structure beside the first gate structure and on the fin structure;
forming the interlayer dielectric layer to surround the first gate structure and the second gate structure;
converting the first gate structure and the second gate structure into a first metal gate and a second metal gate;
forming a cover layer on the first metal gate and the second metal gate;
removing the first metal gate to form the first groove; and
forming the dielectric layer in the first recess.
8. The method of claim 7, further comprising:
forming a first spacer surrounding the first gate structure;
forming the interlayer dielectric layer to surround the first gate structure;
converting the first gate structure into the first metal gate;
removing the first metal gate and a portion of the first spacer to form the first recess; and
forming the dielectric layer on the first spacer and in the first recess.
9. The method of claim 8, wherein a top surface of said first spacer is lower than a top surface of said ild layer.
10. A semiconductor device, comprising:
the single diffusion isolation structure divides a fin-shaped structure into a first part and a second part; and
and the isolation structure is arranged on the single diffusion isolation structure, wherein the isolation structure comprises a T shape.
11. The semiconductor device of claim 10, wherein the isolation structure comprises:
a cover layer disposed on the single diffusion isolation structure; and
the dielectric layer is arranged on the covering layer.
12. The semiconductor device of claim 11, wherein said dielectric layer comprises said T-shape.
13. The semiconductor device as defined in claim 11, wherein the cap layer and the dielectric layer together form the T-shape.
14. The semiconductor device as defined in claim 11, wherein the cap layer comprises a U-shape.
15. The semiconductor device as defined in claim 11, wherein the cap layer and the dielectric layer comprise different materials.
16. A semiconductor device, comprising:
a single diffusion isolation structure separating the fin structure into a first portion and a second portion;
the isolation structure is arranged on the single diffusion isolation structure; and
the first gap wall is arranged beside the isolation structure, wherein the top surface of the first gap wall is lower than that of the isolation structure.
17. The semiconductor device of claim 16, further comprising:
the grid structure is arranged beside the isolation structure; and
and a second spacer surrounding the gate structure.
18. The semiconductor device as defined in claim 17, wherein the bottom surface of the first spacer is lower than the bottom surface of the bottom spacer.
19. The semiconductor device as defined in claim 17, wherein the top surface of the first spacer is lower than the top surface of the second spacer.
20. The semiconductor device as defined in claim 17, wherein the top surface of the first spacer is higher than the bottom surface of the second spacer.
CN202110231289.8A 2020-03-02 2021-03-02 Semiconductor element and manufacturing method thereof Pending CN113345839A (en)

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