CN113345379A

CN113345379A - Shifting register unit and driving method thereof, grid driving circuit and display device

Info

Publication number: CN113345379A
Application number: CN202110728272.3A
Authority: CN
Inventors: 冯雪欢; 高如珍; 薛而延; 万燕飞; 罗标; 桂学海
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2021-09-03
Anticipated expiration: 2041-06-29
Also published as: CN113345379B

Abstract

The present disclosure provides a shift register unit, including: a display write reset sub-circuit, a black insertion write reset sub-circuit, and a first output sub-circuit, the display write reset sub-circuit configured to write an active level signal to the first pull-up node and the second pull-up node under control of the display cascade signal, and write a non-active level signal to the first pull-up node and the second pull-up node under control of the display reset signal; the black insertion writing reset sub-circuit is configured to write an active level signal to the first pull-up node and the second pull-up node under the control of the black insertion cascade signal, and write a non-active level signal to the first pull-up node and the second pull-up node under the control of the control clock signal; a first output sub-circuit configured to output under control of a voltage at the first pull-up node and a voltage at the second pull-up node.

Description

Shifting register unit and driving method thereof, grid driving circuit and display device

Technical Field

The present invention relates to the field of display, and in particular, to a shift register unit, a driving method thereof, a gate driving circuit, and a display device.

Background

In the display field, especially in the organic light emitting diode display device, the dynamic image smear phenomenon is easily generated in the switching process of the dynamic display picture, that is, when the previous frame of display picture is switched to the next frame of display picture, the smear of the previous frame of picture is sensed. In order to overcome the smear phenomenon of the dynamic image, the related art adds a picture black cutting process during the pixel luminescence period, and reduces the normal display time of the pixel by adding the picture black cutting process, thereby effectively improving the smear phenomenon of the dynamic image.

Disclosure of Invention

In a first aspect, an embodiment of the present disclosure provides a shift register unit, including:

a display write reset sub-circuit coupled to the first pull-up node, the second pull-up node, the display cascade signal input terminal, and the display reset signal input terminal, and configured to write an active level signal to the first pull-up node and the second pull-up node under control of a display cascade signal provided by the display cascade signal input terminal, and write an inactive level signal to the first pull-up node and the second pull-up node under control of a display reset signal provided by the display reset signal input terminal;

a black insertion write reset sub-circuit coupled to the first pull-up node, the second pull-up node, the black insertion cascade signal input terminal, and the control clock signal terminal, and configured to write an active level signal to the first pull-up node and the second pull-up node under control of a black insertion cascade signal provided by the black insertion cascade signal input terminal, and write an inactive level signal to the first pull-up node and the second pull-up node under control of a control clock signal provided by the control clock signal terminal;

a first output sub-circuit coupled to the first pull-up node, the second pull-up node, the two cascade clock signal terminals, the two first scan clock signal terminals, the two cascade signal output terminals, and the two first composite signal output terminals, and configured to write a cascade clock signal provided from one of the cascade clock signal terminals to one of the cascade signal output terminals under control of a voltage at the first pull-up node, and writes a first scan clock signal provided from a first scan clock signal terminal into a first composite signal output terminal, and writing the cascade clock signal provided by the other cascade clock signal terminal to the other cascade signal output terminal under the control of the voltage at the second pull-up node, and writing the first scanning clock signal provided by the other first scanning clock signal terminal into the other first composite signal output terminal.

In some embodiments, the black insertion write reset sub-circuit includes: a first black insertion writing transistor, a second black insertion writing transistor, a first black insertion reset transistor, and a second black insertion reset transistor;

a control electrode of the first black insertion writing transistor is coupled with a black insertion cascade signal input end, a first electrode of the first black insertion writing transistor is coupled with the black insertion cascade signal input end, and a second electrode of the first black insertion writing transistor is coupled with the first pull-up node;

a control electrode of the second black insertion writing transistor is coupled with a black insertion cascade signal input end, a first electrode of the second black insertion writing transistor is coupled with the black insertion cascade signal input end or a voltage control node, and a second electrode of the second black insertion writing transistor is coupled with the second pull-up node;

a control electrode of the first black insertion reset transistor is coupled with a black insertion reset signal input end, a first electrode of the first black insertion reset transistor is coupled with a first reset voltage end, and a second electrode of the first black insertion reset transistor is coupled with the first pull-up node;

and the control electrode of the second black insertion reset transistor is coupled with the black insertion reset signal input end, the first electrode of the second black insertion reset transistor is coupled with the first reset voltage end or the voltage control node, and the second electrode of the second black insertion reset transistor is coupled with the second pull-up node.

In some embodiments, the shift register cell further comprises:

a voltage control sub-circuit, coupled to the first pull-up node, the first working voltage terminal, and the voltage control node, configured to control a voltage at the first pull-up node, and write a first working voltage provided by the first working voltage terminal into the voltage control node, where the first working voltage is an active level;

the shift register unit further includes: a first leakage prevention electronic circuit coupled to a first reset voltage terminal, the voltage control node, and the display reset signal input terminal, the first leakage prevention electronic circuit configured to write a first reset voltage provided by the first reset voltage terminal to the voltage control node under control of the display reset signal, the first reset voltage being at a non-active level, the display write reset sub-circuit specifically configured to write a voltage at the voltage control node to the first pull-up node and the second pull-up node under control of the display reset signal;

and/or, the shift register unit further comprises: a second leak-proof electronic circuit coupled to the first reset voltage terminal, the voltage control node, and the black insertion reset signal input terminal, the first leak-proof electronic circuit configured to write a first reset voltage provided by the first reset voltage terminal to the voltage control node under the control of the black insertion reset signal, the first reset voltage being a non-active level, the black insertion write reset sub-circuit specifically configured to write a voltage at the voltage control node to the first pull-up node and the second pull-up node under the control of the black insertion reset signal.

In some embodiments, the shift register cell further comprises:

a sense input sub-circuit coupled to the first pull-up node, the second pull-up node, the sense cascade signal input terminal, the random sense signal terminal, and the sense control signal terminal, for writing the sense cascade signal provided by the sense cascade signal input terminal to a sense control node inside the sense input sub-circuit under control of a random sense signal provided by the random sense signal terminal, and writing the sense control signal to the first pull-up node under control of a voltage at the sense control node and a sense control signal provided by the sense control signal terminal.

In some embodiments, the shift register cell further comprises:

an inverting subcircuit coupled to the first pull-up node, the second pull-up node, a first pull-down node, a second pull-down node, configured to write to the first pull-down node a voltage that is inverted from a voltage at the first pull-up node, and to write to the second pull-down node a voltage that is inverted from a voltage at the second pull-up node;

a feedback sub-circuit coupled to the first pull-up node, the second pull-up node, the first pull-down node, the second pull-down node, configured to write a non-active level signal to the first pull-up node and the second pull-up node under control of a voltage at the first pull-down node and/or a voltage at the second node;

the first output sub-circuit is further coupled to the first pull-down node and the second pull-down node, and the first output sub-circuit is configured to write an inactive level signal to two cascaded signal outputs and two first composite signal outputs under control of a voltage at the first pull-down node and a voltage at the second pull-down node.

In some embodiments, the shift register cell further comprises:

a pull-down control sub-circuit coupled to the display cascade signal input terminal, the black insertion cascade signal input terminal, the first pull-down node, the second pull-down node, and the first reset voltage terminal, and configured to write a first reset voltage provided by the first reset voltage terminal to the first pull-down node and the second pull-down node under control of the display cascade signal, and write the first reset voltage to the first pull-down node and the second pull-down node under control of the black insertion cascade signal.

In some embodiments, the shift register cell further comprises:

a global reset sub-circuit coupled to the first pull-up node, the second pull-up node, and the global reset signal input terminal, and configured to write an inactive level signal to the first pull-up node and the second pull-up node under control of a global reset signal provided by the global reset signal input terminal.

In a second aspect, an embodiment of the present disclosure further provides a gate driving circuit, including: a plurality of cascaded shift register units, the shift register units employing the shift register unit provided in the first aspect above.

In some embodiments, the gate driving circuit includes M stages of shift register units, one of the two cascade signal output ends of each shift register unit is a display cascade signal output end, and the other is a black insertion cascade signal output end;

the display cascade signal input end of the M-th stage shift register unit is coupled with the display cascade signal output end of the M-a stage shift register unit, the display reset signal input end of the M-th stage shift register unit is coupled with the display cascade signal output end of the M + b stage shift register unit, the black insertion cascade signal input end of the M-th stage shift register unit is coupled with the black insertion cascade signal output end of the M-c stage shift register unit, a, b and c are respectively preset positive integers, a + b is less than or equal to c, M is a positive integer and satisfies a is less than M, c is less than M, and M + b is less than or equal to M.

In some embodiments, the M shift register units are divided into a plurality of first shift register unit groups, a plurality of second shift register unit groups, and a plurality of third shift register unit groups, the first shift register unit groups, the second shift register unit groups, and the third shift register unit groups are sequentially and alternately arranged, and the number of shift register units in the first shift register unit groups, the number of shift register units in the second shift register unit groups, and the number of shift register units in the third shift register unit groups are all c;

the grid driving circuit is provided with 3 control clock signal lines;

the control clock signal terminal of each shift register unit in the first shift register unit group is coupled to 1 control clock signal line, the control clock signal terminal of each shift register unit in the second shift register unit group is coupled to the other 1 control clock signal line, and the control clock signal terminal of each shift register unit in the third shift register unit group is coupled to the remaining 1 control clock signal line.

In some embodiments, the gate driving circuit is configured with 6c first scan clock signal lines, the 6c first scan clock signal lines are divided into a first signal line group, a second signal line group and a third signal line group, and the number of the first scan clock signal lines in the first signal line group, the number of the first scan clock signal lines in the second signal line group and the number of the first scan clock signal lines in the third signal line group are all 2 c;

two first scanning clock signal ends of an ith shift register unit in the first shift register unit group are respectively coupled with a 2i-1 first scanning clock signal line and a 2i first scanning clock signal line in the first signal line group;

two first scanning clock signal ends of an ith shift register unit in the second shift register unit group are respectively coupled with a 2i-1 first scanning clock signal line and a 2i first scanning clock signal line in the second signal line group;

two first scanning clock signal ends of an ith shift register unit in the third shift register unit group are respectively coupled with a 2i-1 first scanning clock signal line and a 2i first scanning clock signal line in the third signal line group;

i is a positive integer and i is less than or equal to c.

In some embodiments, the gate driving circuit is configured with 6c cascade clock signal lines, the 6c cascade clock signal lines are divided into a fourth signal line group, a fifth signal line group and a sixth signal line group, and the number of the cascade clock signal lines in the fourth signal line group, the number of the cascade clock signal lines in the fifth signal line group and the number of the cascade clock signal lines in the sixth signal line group are all 2c

Two cascade clock signal ends of the ith shift register unit in the first shift register unit group are respectively coupled with the 2i-1 cascade clock signal line and the 2i cascade clock signal line in the fourth signal line group;

two cascade clock signal ends of the ith shift register unit in the second shift register unit group are respectively coupled with the 2i-1 cascade clock signal line and the 2i cascade clock signal line in the fifth signal line group;

two cascade clock signal ends of the ith shift register unit in the third shift register unit group are respectively coupled with the 2i-1 th cascade clock signal line and the 2i cascade clock signal line in the sixth signal line group;

i is a positive integer and i is less than or equal to c.

In some embodiments, c has a value of 4.

In a third aspect, an embodiment of the present disclosure further provides a display device, including: the gate driving circuit as provided in the second aspect above.

In a fourth aspect, an embodiment of the present disclosure further provides a driving method for a shift register unit, where the shift register unit provided in the second aspect is adopted, and the driving method includes:

the display write reset sub-circuit writes an active level signal into the first pull-up node and the second pull-up node under the control of the display cascade signal, the first output sub-circuit writes a cascade clock signal provided by one cascade clock signal terminal into one cascade signal output terminal and writes a first scan clock signal provided by one first scan clock signal terminal into one first composite signal output terminal under the control of the voltage at the first pull-up node, and writes a cascade clock signal provided by the other cascade clock signal terminal into the other cascade signal output terminal and writes a first scan clock signal provided by the other first scan clock signal terminal into the other first composite signal output terminal under the control of the voltage at the second pull-up node;

the display write reset sub-circuit writes a non-active level signal into the first pull-up node and the second pull-up node under the control of the reset cascade signal;

the black insertion writing reset sub-circuit writes effective level signals into the first pull-up node and the second pull-up node under the control of the black insertion cascade signal, the first output sub-circuit writes a cascade clock signal provided by one cascade clock signal terminal into one cascade signal output terminal under the control of the voltage of the first pull-up node, and writes a first scan clock signal provided by one first scan clock signal terminal into one first composite signal output terminal, and writes a cascade clock signal provided by the other cascade clock signal terminal into the other cascade signal output terminal under the control of the voltage of the second pull-up node, and writes a first scan clock signal provided by the other first scan clock signal terminal into the other first composite signal output terminal;

and the black insertion writing reset sub-circuit writes a non-effective level signal into the first pull-up node and the second pull-up node under the control of the control clock signal.

Drawings

FIG. 1 is a schematic top view of a display device according to an embodiment of the present disclosure;

FIG. 2 is a schematic circuit diagram of a pixel unit in a display device according to the present disclosure;

FIG. 3A is a timing diagram illustrating operation of the pixel unit shown in FIG. 2;

FIG. 3B is a timing diagram illustrating another operation of the pixel unit shown in FIG. 2;

fig. 4 is a schematic circuit structure diagram of a shift register unit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 6 is a schematic circuit diagram of a shift register unit according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram illustrating operation of the shift register unit shown in FIG. 6 during display driving and black insertion driving;

FIG. 8 is a timing diagram illustrating another operation of the shift register unit shown in FIG. 6 during display driving and black insertion driving;

fig. 9 is a schematic circuit diagram of a shift register unit according to another embodiment of the present disclosure;

fig. 10 is a schematic circuit diagram of a shift register unit according to another embodiment of the present disclosure;

fig. 11 is a schematic circuit diagram of a shift register unit according to another embodiment of the present disclosure;

fig. 12 is a schematic circuit structure diagram of a gate driving circuit according to an embodiment of the disclosure;

FIG. 13 is a schematic diagram of a circuit configuration of a first shift register cell group according to an embodiment of the present disclosure;

FIG. 14 is a schematic circuit diagram of a second shift register unit set according to an embodiment of the present disclosure;

FIG. 15 is a schematic circuit diagram of a third shift register unit set according to an embodiment of the present disclosure;

FIG. 16 is a timing diagram illustrating the operation of the gate driving circuit shown in FIG. 12;

fig. 17 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure;

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, a shift register unit, a driving method thereof, a gate driving circuit and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not restricted to physical or mechanical couplings, but may include electrical couplings, whether direct or indirect.

The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the drain and source of each transistor may be coupled in an interchangeable manner, and thus, the drain and source of each transistor in the embodiment of the present disclosure are not different. Here, only in order to distinguish two poles of the transistor except for the control electrode (i.e., the gate), one of the poles is referred to as a drain and the other pole is referred to as a source. The thin film transistor used in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor. In the embodiment of the present disclosure, when an N-type thin film transistor is used, the first electrode thereof may be a source electrode, and the second electrode thereof may be a drain electrode. In the following embodiments, the thin film transistor is described as an N-type transistor.

In the present disclosure, an "active level signal" refers to a signal that can control the transistor to be turned on when the signal is input to the control electrode of the transistor, and an "inactive level signal" refers to a signal that can control the transistor to be turned off when the signal is input to the control electrode of the transistor. For an N-type transistor, a high level signal is an active level signal, and a low level signal is a non-active level signal; for a P-type transistor, the low level signal is an active level signal and the high level signal is an inactive level signal.

In the following description, the transistors will be described as N-type transistors as an example, and at this time, the active level signal refers to a high level signal and the inactive level signal refers to a low level signal. It is conceivable that when a P-type transistor is employed, the timing of the control signal needs to be adjusted accordingly. Specific details are not set forth herein but are intended to be within the scope of the present disclosure.

Fig. 1 is a schematic top view of a display device in an embodiment of the disclosure, and as shown in fig. 1, the display device 100 includes: a display area 101 and a peripheral area 102, a plurality of pixel units 300 arranged in an array are disposed in the display area 101, a gate driving circuit 200 is disposed in the peripheral area 102, and the gate driving circuit 200 includes: a cascade of a plurality of shift register cells (not shown in fig. 1).

Fig. 2 is a schematic circuit diagram of a pixel unit in a display substrate according to the present disclosure, fig. 3A is a timing diagram of an operation of the pixel unit shown in fig. 2, and fig. 3B is a timing diagram of another operation of the pixel unit shown in fig. 2, and as shown in fig. 2 to 3B, the pixel unit 300 includes: a pixel circuit and a light emitting element. In which the light emitting element is an Organic Light Emitting Diode (OLED) as an example.

The pixel circuit includes a data writing transistor QTFT (a control electrode connected to the first gate line G1), a driving transistor DTFT, a sensing transistor STFT (a control electrode connected to the second gate line G2, a first electrode connected to the sensing signal line sequence), and a storage capacitor Cst. Referring to fig. 2, when only the pixel unit 300 needs to perform light emitting display, the working process of the pixel unit 300 includes a display data writing phase and a light emitting phase; during the stage of writing display Data, the first gate line G1 controls the Data writing transistor QTFT to be turned on, and the Data line Data writes the Data voltage Vdata to the control electrode of the driving transistor DTFT; in the light emitting stage, the driving transistor DTFT outputs a corresponding driving current according to the voltage at the control electrode thereof, so as to drive the light emitting element OLED to emit light.

It should be noted that after one frame is finished, the electrical characteristics of the driving transistor DTFT and/or the light emitting element OLED in the pixel circuit may be sensed by the sensing transistor STFT, and the sensing result may be used to externally compensate the pixel circuit. The specific external compensation process belongs to the conventional technology in the field, and is not described in detail herein.

The pixel unit 300 may generate a moving image smear during operation, that is, when the display device switches from one frame to another frame, a user may feel the smear of the previous frame. One solution is: as shown in fig. 3, a black data writing process and a black data holding process, i.e., a process of one Picture black insertion, are set during the lighting of the pixel circuit, which reduces the lighting Time and enhances the Moving Picture Response Time (MPRT), the larger the MPRT, the lighter the smear.

In the related art, one gate driving circuit can output only one type of driving signal, and thus in order to provide the first gate lines with the display driving signal for display (pulse 1 in fig. 3A) and the black insertion driving signal for black insertion (pulse 2in fig. 3A), it is generally necessary to arrange two independent gate driving circuits, one of which is used for providing the first gate lines with the display driving signal and the other is used for providing the first gate lines with the black insertion driving signal. Therefore, in the related art, in order to implement the black insertion function, it is generally required to add a gate driving circuit for providing a black insertion driving signal to the peripheral region of the display device. However, the added gate driving circuit inevitably occupies a certain peripheral area space, which is not favorable for the narrow frame design of the product.

In order to solve the technical problem, the present disclosure provides a corresponding solution. In the disclosure, each stage of shift register unit in the gate driving circuit can output the display driving signal and the black insertion driving signal, so that an independent gate driving circuit does not need to be configured for the black insertion driving signal, and the narrow frame design of the product is facilitated.

Fig. 4 is a schematic circuit structure diagram of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 4, the shift register unit includes: a write reset sub-circuit 1, a black insertion write reset sub-circuit 2 and a first output sub-circuit 3 are shown.

Wherein the display write reset sub-circuit 1 is coupled to the first pull-up node PU1, the second pull-up node PU2, the display cascade signal input IN1 and the display reset signal input RST, the display write reset sub-circuit 1 is configured to write an active level signal to the first pull-up node PU1 and the second pull-up node PU2 under control of a display cascade signal provided by the display cascade signal input IN1, and to write an inactive level signal to the first pull-up node PU1 and the second pull-up node PU2 under control of a display reset signal provided by the display reset signal input RST.

The black insertion write reset sub-circuit 2 is coupled to the first pull-up node PU1, the second pull-up node PU2, the black insertion cascade signal input terminal IN2, and the control clock signal terminal BCK, and the black insertion write reset sub-circuit 2 is configured to write an active level signal to the first pull-up node PU1 and the second pull-up node PU2 under control of a black insertion cascade signal provided from the black insertion cascade signal input terminal IN2, and write an inactive level signal to the first pull-up node PU1 and the second pull-up node PU2 under control of a control clock signal provided from the control clock signal terminal BCK.

The first output sub-circuit 3 is coupled to the first pull-up node PU1, the second pull-up node PU2, the two cascade clock signal terminals CLKD, CLKD ', the two first scan clock signal terminals CLKE, CLKE', the two cascade signal output terminals CR, CR 'and the two first composite signal output terminals OUT1, OUT 1', the first output sub-circuit 3 is configured to write the cascade clock signal provided by one of the cascade clock signal terminals to one of the cascade signal output terminals under the control of the voltage at the first pull-up node PU1, and writes a first scan clock signal provided from a first scan clock signal terminal into a first composite signal output terminal, and writes the cascade clock signal provided from the other cascade clock signal terminal to the other cascade signal output terminal under the control of the voltage at the second pull-up node PU2, and writing the first scanning clock signal provided by the other first scanning clock signal terminal into the other first composite signal output terminal.

In the present disclosure, of two cascade clock signal terminals CLKD, CLKD' of the shift register unit, the cascade clock signal provided by one of the cascade clock signal terminals is used as a display driving cascade signal, and the cascade clock signal provided by the other cascade clock signal terminal is used as a black insertion driving cascade signal; accordingly, of the two cascade signal output terminals CR, CR' of the shift register unit, one of the cascade signal output terminals (corresponding to one of the cascade clock signal terminals supplying the display driving cascade signal) serves as the display cascade signal output terminal, and the other cascade signal output terminal (corresponding to one of the cascade clock signal terminals supplying the black insertion driving cascade signal) serves as the black insertion cascade signal output terminal.

The working process of the shift register unit provided by the embodiment of the disclosure comprises a display driving process and a black insertion driving process.

In the display driving process, the display write reset sub-circuit 1 writes the active level signal to the first pull-up node PU1 and the second pull-up node PU2 under the control of the display cascade signal, the first output sub-circuit 3 writes the cascade clock signal provided from one of the cascade clock signal terminals to one of the cascade signal output terminals and writes the first scan clock signal provided from one of the first scan clock signal terminals to one of the first composite signal output terminals under the control of the voltage at the first pull-up node PU1, and writes the cascade clock signal provided from the other of the cascade clock signal terminals to the other of the cascade signal output terminals and writes the first scan clock signal provided from the other of the first scan clock signal terminals to the other of the first composite signal output terminals under the control of the voltage at the second pull-up node PU 2. At this time, the two first scan clock signal terminals CLKE, CLKE' are both provided with display driving pulses; the cascade clock signal provided by a cascade clock signal terminal corresponding to the display cascade signal output terminal includes a display cascade pulse. Thereafter, the display write reset sub-circuit 1 writes the inactive level signal to the first pull-up node PU1 and the second pull-up node PU2 under the control of the display reset signal to reset the first pull-up node PU1 and the second pull-up node PU 2.

In the black insertion driving process, the black insertion write reset sub-circuit 2 writes the active level signal to the first pull-up node PU1 and the second pull-up node PU2 under the control of the black insertion cascade signal, the first output sub-circuit 3 writes the cascade clock signal provided from one cascade clock signal terminal to one cascade signal output terminal and writes the first scan clock signal provided from one first scan clock signal terminal to one first composite signal output terminal under the control of the voltage at the first pull-up node PU1, and writes the cascade clock signal provided from the other cascade clock signal terminal to the other cascade signal output terminal and writes the first scan clock signal provided from the other first scan clock signal terminal to the other first composite signal output terminal under the control of the voltage at the second pull-up node PU 2. At this time, the two first scan clock signal terminals CLKE, CLKE' are both provided with black insertion drive pulses; the cascade clock signal provided by a cascade clock signal end corresponding to the black insertion cascade signal output end comprises a black insertion cascade pulse. Thereafter, the black insertion write reset sub-circuit 2 writes an inactive level signal to the first and second pull-up nodes PU1 and PU2 under the control of the black insertion reset signal to reset the first and second pull-up nodes PU1 and PU 2.

Based on the above, it can be seen that the two first composite signal output ends OUT1 and OUT 1' of the shift register unit provided by the present disclosure may each output a display driving pulse and a black insertion driving pulse to perform display driving and black insertion driving on the corresponding first gate line; meanwhile, two cascade signal output ends CR and CR' in the shift register unit can respectively output a display cascade pulse and a black insertion cascade pulse so as to realize display drive cascade and black insertion drive cascade among a plurality of shift register units in the grid drive circuit. Compared with the prior art, the technical scheme of the disclosure can effectively reduce the number of the gate driving circuits in the display device, and is beneficial to the narrow frame design of products.

Fig. 5 is a schematic circuit diagram of another circuit structure of a shift register unit according to an embodiment of the present disclosure, as shown in fig. 5, in some embodiments, the shift register unit further includes: an inverter sub-circuit 5 and a feedback sub-circuit 6.

Wherein the inverting sub-circuit 5 is coupled to the first pull-up node PU1, the second pull-up node PU2, the first pull-down node PD1, and the second pull-down node PD2, the inverting sub-circuit 5 is configured to write a voltage inverted from the voltage at the first pull-up node PU1 to the first pull-down node PD1, and write a voltage inverted from the voltage at the second pull-up node PU2 to the second pull-down node PD 2.

A feedback sub-circuit 6 is coupled to the first pull-up node PU1, the second pull-up node PU2, the first pull-down node PD1, and the second pull-down node PD2, the feedback sub-circuit 6 being configured to write a non-active level signal to the first pull-up node PU1 and the second pull-up node PU2 under control of a voltage at the first pull-down node PD1 and/or a voltage at the second node; the first output sub-circuit 3 is further coupled to the first pull-down node PD1 and the second pull-down node PD2, the first output sub-circuit 3 being configured to write an inactive level signal to the two cascade signal output terminals CR, CR 'and the two first composite signal output terminals OUT1, OUT 1' under control of the voltage at the first pull-down node PD1 and the voltage at the second pull-down node PD 2.

In some embodiments, the shift register cell further comprises: a pull-down control sub-circuit 7; the pull-down control sub-circuit 7 is coupled to the display cascade signal input terminal IN1, the black insertion cascade signal input terminal IN2, the first pull-down node PD1, the second pull-down node PD2, and the first reset voltage terminal, and the pull-down control sub-circuit 7 is configured to write the first reset voltage provided by the first reset voltage terminal to the first pull-down node PD1 and the second pull-down node PD2 under the control of the display cascade signal, and to write the first reset voltage to the first pull-down node PD1 and the second pull-down node PD2 under the control of the black insertion cascade signal.

In some embodiments, the shift register cell further comprises: a global reset sub-circuit 4, the global reset sub-circuit 4 being coupled to the first pull-up node PU1, the second pull-up node PU2, and the global reset signal input RST, the global reset sub-circuit 4 being configured to write an inactive level signal to the first pull-up node PU1 and the second pull-up node PU2 under control of a global reset signal provided by the global reset signal input RST.

Fig. 6 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure, and as shown in fig. 6, in some embodiments, the write reset sub-circuit 1 includes first to fourth transistors M1 to M4, the black insertion write reset sub-circuit 2 includes first to eighth black insertion write transistors (also referred to as a fifth transistor M5, M7, M6, M24, and M8), the first output sub-circuit 3 includes ninth to sixteenth transistors M9 to M16, the inverting sub-circuit 5 includes seventeenth to twenty fourth transistors M17 to M24, the feedback sub-circuit 6 includes twenty fifth to twenty eighth transistors M25 to M28, the global reset sub-circuit 4 includes twenty ninth to thirty transistors M29 and M30, the pull-down control sub-circuit 7 includes thirty-first to thirty-fourth transistors M31 to M.

A control electrode of the first transistor M1 is coupled to the display cascade signal input terminal IN1, a first electrode of the first transistor M1 is coupled to the display cascade signal input terminal IN1, and a second electrode of the first transistor M1 is coupled to the first pull-up node PU 1.

The control electrode of the second transistor M2 is coupled to the display reset signal input RST, the first electrode of the second transistor M2 is coupled to the first pull-up node PU1, and the second electrode of the second transistor M2 is coupled to the first reset voltage terminal (providing the first reset voltage VGL 1).

A control electrode of the third transistor M3 is coupled to the display cascade signal input terminal IN1, a first electrode of the third transistor M3 is coupled to the display cascade signal input terminal IN1, and a second electrode of the third transistor M3 is coupled to the second pull-up node PU 2.

A control electrode of the fourth transistor M4 is coupled to the display reset signal input RST, a first electrode of the fourth transistor M4 is coupled to the second pull-up node PU2, and a second electrode of the fourth transistor M4 is coupled to the first reset voltage terminal.

A control electrode of the fifth transistor M5 is coupled to the black inserted cascade signal input terminal IN2, a first electrode of the fifth transistor M5 is coupled to the black inserted cascade signal input terminal IN2, and a second electrode of the fifth transistor M5 is coupled to the first pull-up node PU 1.

A control electrode of the sixth transistor M6 is coupled to the control clock signal terminal BCK, a first electrode of the sixth transistor M6 is coupled to the first pull-up node PU1, and a second electrode of the sixth transistor M6 is coupled to the first reset voltage terminal.

A control electrode of the seventh transistor M7 is coupled to the black inserted cascade signal input terminal IN2, a first electrode of the seventh transistor M7 is coupled to the black inserted cascade signal input terminal IN2, and a second electrode of the seventh transistor M7 is coupled to the second pull-up node PU 2.

A control electrode of the eighth transistor M8 is coupled to the control clock signal terminal BCK, a first electrode of the eighth transistor M8 is coupled to the second pull-up node PU2, and a second electrode of the eighth transistor M8 is coupled to the first reset voltage terminal.

A control electrode of the ninth transistor M9 is coupled to the first pull-up node PU1, a first electrode of the ninth transistor M9 is coupled to a cascade clock signal terminal CLKD, and a second electrode of the ninth transistor M9 is coupled to a cascade signal output terminal CR.

A control electrode of the tenth transistor M10 is coupled to the first pull-up node PU1, a first electrode of the tenth transistor M10 is coupled to a first scan clock signal terminal CLKE, and a second electrode of the tenth transistor M10 is coupled to a first composite signal output terminal OUT.

A control electrode of the eleventh transistor M11 is coupled to the first pull-down node PD1, a first electrode of the eleventh transistor M11 is coupled to the cascade signal output terminal CR, and a second electrode of the eleventh transistor M11 is coupled to the first reset voltage terminal.

A control electrode of the twelfth transistor M12 is coupled to the first pull-down node PD1, a first electrode of the twelfth transistor M12 is coupled to the first composite signal output terminal OUT, and a second electrode of the twelfth transistor M12 is coupled to a second reset voltage terminal (providing a second reset voltage VGL2, VGL2 may be equal to VGL 1).

A control electrode of the thirteenth transistor M13 is coupled to the second pull-up node PU2, a first electrode of the thirteenth transistor M13 is coupled to another cascade clock signal terminal CLKD ', and a second electrode of the thirteenth transistor M13 is coupled to another cascade signal output terminal CR'.

A control electrode of the fourteenth transistor M14 is coupled to the second pull-up node PU2, a first electrode of the fourteenth transistor M14 is coupled to another first scan clock signal terminal CLKE ', and a second electrode of the fourteenth transistor M14 is coupled to another first composite signal output terminal OUT'.

A control electrode of the fifteenth transistor M15 is coupled to the second pull-down node PD2, a first electrode of the fifteenth transistor M15 is coupled to the cascade signal output terminal CR', and a second electrode of the fifteenth transistor M15 is coupled to the first reset voltage terminal.

A control electrode of the sixteenth transistor M16 is coupled to the second pull-down node PD2, a first electrode of the sixteenth transistor M16 is coupled to the first composite signal output terminal OUT', and a second electrode of the sixteenth transistor M16 is coupled to the second reset voltage terminal (providing the second reset voltage VGL 2).

A control electrode of the seventeenth transistor M17 is coupled to the second operating voltage terminal (providing the second operating voltage VDD), a first electrode of the seventeenth transistor M17 is coupled to the second operating voltage terminal, and a second electrode of the seventeenth transistor M17 is coupled to a control electrode of the nineteenth transistor M19 and a first electrode of the eighteenth transistor M18;

a control electrode of the eighteenth transistor M18 is coupled to the first pull-up node PU1, and a second electrode of the eighteenth transistor M18 is coupled to the first reset voltage terminal.

A first pole of the nineteenth transistor M19 is coupled to the second operating voltage terminal, and a second pole of the nineteenth transistor M19 is coupled to the first pull-down node PD 1.

A control electrode of the twentieth transistor M20 is coupled to the first pull-up node PU1, a first electrode of the twentieth transistor M20 is coupled to the first pull-down node PD1, and a second electrode of the twentieth transistor M20 is coupled to the first reset voltage terminal.

A control electrode of the twenty-first transistor M21 is coupled to the second operating voltage terminal, a first electrode of the twenty-first transistor M21 is coupled to the second operating voltage terminal, a second electrode of the twenty-first transistor M21 is coupled to a control electrode of the twenty-third transistor M23 and a first electrode of the twenty-second transistor M22;

the control electrode of the twentieth transistor M22 is coupled to the second pull-up node PU2, and the second electrode of the twentieth transistor M22 is coupled to the first reset voltage terminal.

A first pole of the twenty-third transistor M23 is coupled to the second operating voltage terminal, and a second pole of the twenty-third transistor M23 is coupled to the second pull-down node PD 2.

A control electrode of the twenty-fourth transistor M24 is coupled to the second pull-up node PU2, a first electrode of the twenty-fourth transistor M24 is coupled to the second pull-down node PD2, and a second electrode of the twenty-fourth transistor M24 is coupled to the first reset voltage terminal.

A control electrode of the twenty-fifth transistor M25 is coupled to the first pull-down node PD1, a first electrode of the twenty-fifth transistor M25 is coupled to the first pull-up node PU1, and a second electrode of the twenty-fifth transistor M25 is coupled to the first reset voltage terminal.

A control electrode of the twenty-sixth transistor M26 is coupled to the second pull-down node PD2, a first electrode of the twenty-sixth transistor M26 is coupled to the first pull-up node PU1, and a second electrode of the twenty-sixth transistor M26 is coupled to the first reset voltage terminal.

A control electrode of the twenty-seventh transistor M27 is coupled to the second pull-down node PD2, a first electrode of the twenty-seventh transistor M27 is coupled to the second pull-up node PU2, and a second electrode of the twenty-seventh transistor M27 is coupled to the first reset voltage terminal.

A control electrode of the twenty-eighth transistor M28 is coupled to the first pull-down node PD1, a first electrode of the twenty-eighth transistor M28 is coupled to the second pull-up node PU2, and a second electrode of the twenty-eighth transistor M28 is coupled to the first reset voltage terminal.

A control electrode of the twenty-ninth transistor M29 is coupled to the global reset signal input RST, a first electrode of the twenty-ninth transistor M29 is coupled to the first pull-up node PU1, and a second electrode of the twenty-ninth transistor M29 is coupled to the first reset power supply terminal.

A control electrode of the thirtieth transistor M30 is coupled to the global reset signal input RST, a first electrode of the thirtieth transistor M30 is coupled to the second pull-up node PU2, and a second electrode of the thirtieth transistor M30 is coupled to the first reset power source terminal.

A control electrode of the thirty-first transistor M31 is coupled to the display cascade signal input terminal IN1, a first electrode of the thirty-first transistor M31 is coupled to the first pull-down node PD1, and a second electrode of the thirty-first transistor M31 is coupled to the first reset voltage terminal.

A control electrode of the thirtieth transistor M32 is coupled to the black insertion cascade signal input terminal IN2, a first electrode of the thirtieth transistor M32 is coupled to the first pull-down node PD1, and a second electrode of the thirty-first transistor M32 is coupled to the first reset voltage terminal.

A control electrode of the thirty-third transistor M33 is coupled to the display cascade signal input terminal IN1, a first electrode of the thirty-third transistor M33 is coupled to the second pull-down node PD2, and a second electrode of the thirty-third transistor M33 is coupled to the first reset voltage terminal.

A control electrode of the thirty-fourth transistor M34 is coupled to the black insertion cascade signal input terminal IN2, a first electrode of the thirty-fourth transistor M34 is coupled to the second pull-down node PD2, and a second electrode of the thirty-fourth transistor M34 is coupled to the first reset voltage terminal.

Fig. 7 is an operation timing diagram of the shift register unit shown in fig. 6 during display driving and black insertion driving, and as shown in fig. 7, the process of the shift register unit during display driving may include: a display writing phase t1, a display driving output phase t2 and a display resetting phase t 3; the process of black insertion driving of the shift register unit can comprise the following steps: a black insertion writing phase t4, a black insertion driving output phase t5, and a black insertion reset phase t 6.

IN the display writing phase t1, the display cascade signal provided by the display cascade signal input terminal IN1 is IN a high level state, the first transistor M1 and the third transistor M3 are both turned on, the display cascade signal IN the high level state (i.e., the active level signal) is written into the first pull-up node PU1 and the second pull-up node PU2, and the first pull-up node PU1 and the second pull-up node PU2 are both IN a high level state; meanwhile, the first pull-down node PD1 and the second pull-down node PD2 are both in a low state by the seventeenth transistor M17 through the twenty-fourth transistor M24.

In the display driving output stage t2, since the first pull-up node PU1 and the second pull-up node PU2 are both in a high level state, the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, and the fourteenth transistor M14 are all turned on, the cascade clock signal terminal CLKD and the cascade clock signal terminal CLKD 'respectively write corresponding cascade signals to the cascade signal output terminal CR and the cascade signal output terminal CR', and the first scan clock signal terminal CLKE 'respectively write corresponding signals to the first composite signal output terminal OUT1 and the first composite signal output terminal OUT 1' of the cascade signal output terminal. The coupled signal output terminal CR outputs display cascade pulses, and the first composite signal output terminal OUT1 and the first composite signal output terminal OUT 1' sequentially output display driving pulses.

It should be noted that, in the operation sequence shown in fig. 7, the cascade signal output terminal CR is used as the display cascade signal output terminal, and the cascade signal output terminal CR 'is used as the black insertion cascade signal output terminal, so that no pulse is output from the cascade signal output terminal CR' in the display drive output stage t 2.

In the display reset phase t3, the display reset signal provided by the display reset signal input terminal RST is in a high level state, the second transistor M2 and the fourth transistor M4 are both turned on, and the first reset voltage (inactive level signal) is written to the first pull-up node PU1 and the second pull-up node PU 2; meanwhile, under the action of the seventeenth transistor M17 to the twenty-fourth transistor M24, the first pull-down node PD1 and the second pull-down node PD2 are all in a high level state, and the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15 and the sixteenth transistor M16 are all turned on, so that the coupled signal output end CR, the coupled signal output end CR ', the first composite signal output end OUT1 and the first composite signal output end OUT 1' are reset and noise is reduced. In this stage, the twenty-fifth transistor M25 through the twenty-eighth transistor M28 are all turned on to reduce noise on the first pull-up node PU1 and the second pull-up node PU 2.

IN the black insertion writing phase t4, the display cascade signal provided by the black insertion cascade signal input terminal IN2IN2 is IN a high level state, the fifth transistor M5 and the seventh transistor M7 are both turned on, the black insertion cascade signal IN the high level state (i.e., an active level signal) is written into the first pull-up node PU1 and the second pull-up node PU2, and the first pull-up node PU1 and the second pull-up node PU2 are both IN a high level state; meanwhile, the first pull-down node PD1 and the second pull-down node PD2 are both in a low state by the seventeenth transistor M17 through the twenty-fourth transistor M24.

In the black insertion driving output stage t5, since the first pull-up node PU1 and the second pull-up node PU2 are both in a high level state, the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, and the fourteenth transistor M14 are all turned on, the cascade clock signal terminal CLKD and the cascade clock signal terminal CLKD 'respectively write corresponding cascade signals to the cascade signal output terminal CR and the cascade signal output terminal CR', and the first scan clock signal terminal CLKE 'respectively write corresponding signals to the first composite signal output terminal OUT1 and the first composite signal output terminal OUT 1' of the cascade signal output terminal. The joint signal output terminal CR 'outputs a black insertion cascade pulse, and the first composite signal output terminal OUT1 and the first composite signal output terminal OUT 1' simultaneously output a black insertion driving pulse.

It should be noted that, in the operation sequence shown in fig. 7, the cascade signal output terminal CR is used as the display cascade signal output terminal, and the cascade signal output terminal CR' is used as the black insertion cascade signal output terminal, so that no pulse is output from the cascade signal output terminal CR in the black insertion drive output stage t 5.

In the black insertion reset period t6, the control clock signal of the control clock signal terminal BCK is in a high level state, the sixth transistor M6 and the eighth transistor M8 are both turned on, and the first reset voltage (inactive level signal) is written to the first pull-up node PU1 and the second pull-up node PU 2; meanwhile, under the action of the seventeenth transistor M17 to the twenty-fourth transistor M24, the first pull-down node PD1 and the second pull-down node PD2 are all in a high level state, and the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15 and the sixteenth transistor M16 are all turned on, so that the coupled signal output end CR, the coupled signal output end CR ', the first composite signal output end OUT1 and the first composite signal output end OUT 1' are reset and noise is reduced. In this stage, the twenty-fifth transistor M25 through the twenty-eighth transistor M28 are all turned on to reduce noise on the first pull-up node PU1 and the second pull-up node PU 2.

Fig. 8 is another operation timing chart of the shift register unit shown in fig. 6 during display driving and black insertion driving, and as shown in fig. 8, in the operation timing chart shown in fig. 8, the cascade signal output terminal CR is used as a black insertion cascade signal output terminal, and the cascade signal output terminal CR' is used as a display cascade signal output terminal. Therefore, in the display driving output stage t2, the cascade signal output terminal CR outputs no pulse and the cascade signal output terminal CR' outputs a display cascade pulse; in the black insertion driving output stage t5, the cascade signal output terminal CR' outputs no pulse and the cascade signal output terminal CR outputs a black insertion cascade pulse.

Fig. 9 is a schematic circuit structure diagram of another shift register unit provided in the embodiment of the present disclosure, and as shown in fig. 9, the shift register unit includes not only the display write reset sub-circuit 1, the black insertion write reset sub-circuit 2, the first output sub-circuit 3, the inverting sub-circuit 5, the feedback sub-circuit 6, the global reset sub-circuit 4, and the pull-down control sub-circuit 7 according to the foregoing embodiment, but also the sensing input sub-circuit 8. The sensing input sub-circuit 8 is coupled to the first pull-up node PU1, the second pull-up node PU2, the sensing cascade signal input terminal IN3, the random sensing signal terminal OE, and the sensing control signal terminal CLKA, and is configured to write the sensing cascade signal provided by the sensing cascade signal input terminal IN3 to the sensing control node Q inside the sensing input sub-circuit 8 under the control of the random sensing signal provided by the random sensing signal terminal OE, and write the sensing control signal to the first pull-up node PU1 under the control of the voltage at the sensing control node Q and the sensing control signal provided by the sensing control signal terminal CLKA.

In some embodiments, the sensing input sub-circuit 8 includes thirty-fifth transistor M35 through thirty-seventh transistor M37.

A control electrode of the thirty-fifth transistor M35 is coupled to the random sensing signal terminal OE, a first electrode of the thirty-fifth transistor M35 is coupled to the sensing cascade signal input terminal IN3, and a second electrode of the thirty-fifth transistor M35 is coupled to the sensing control node Q.

A control electrode of the thirty-sixth transistor M36 is coupled to the sensing control node Q, a first electrode of the thirty-sixth transistor M36 is coupled to the sensing control signal terminal CLKA, and a second electrode of the thirty-sixth transistor M36 is coupled to a first electrode of the thirty-seventh transistor M37.

A control electrode of the thirty-seventh transistor M37 is coupled to the sensing control signal terminal CLKA, and a second electrode of the thirty-seventh transistor M37 is coupled to the first pull-up node PU 1.

IN practical applications, the sensing input sub-circuit 8 can be controlled to write an active level signal to the first pull-up node PU1 through the random sensing signal terminal OE, the sensing cascade signal input terminal IN3 and the sensing control signal terminal CLKA, so as to control the shift register unit to output a sensing driving signal capable of controlling the pixel unit to perform electrical characteristic sensing.

Fig. 10 is a schematic circuit structure diagram of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 10, in some embodiments, the shift register unit further includes: a second output sub-circuit 9; wherein the second output sub-circuit 9 is coupled to the first pull-up node PU1, the second pull-up node PU2, the two second scan clock signal terminals CLKF, CLKF 'and the two second composite signal output terminals OUT2, OUT2', and the second output sub-circuit 97 is configured to write the second scan clock signal provided by one second scan clock signal terminal CLKF to one second composite signal output terminal CLKF under the control of the voltage at the first pull-up node PU1, and write the second scan clock signal provided by the other second scan clock signal terminal CLKF 'to the other second composite signal output terminal OUT2' under the control of the voltage at the second pull-up node PU 2.

In the display region, the second gate line G2 extends into the peripheral region and is coupled to the corresponding second composite signal output terminals OUT2, OUT2', and different second gate lines G2 are coupled to different second composite signal output terminals CLKF, CLKF'.

In some embodiments, the second output sub-circuit 9 includes thirty-eighth to forty-first transistors M38-M41, a fourth capacitor C4, and a fifth capacitor C5.

A control electrode of the thirty-eighth transistor M38 is coupled to the first pull-up node PU1, a first electrode of the thirty-eighth transistor M38 is coupled to a second scan clock signal terminal CLKF, and a second electrode of the thirty-eighth transistor M38 is coupled to a second composite signal output terminal OUT 2.

A control electrode of the thirty-ninth transistor M39 is coupled to the first pull-down node PD1, a first electrode of the thirty-ninth transistor M39 is coupled to the second composite signal output terminal OUT2, and a second electrode of the thirty-ninth transistor M39 is coupled to the second reset power supply terminal.

A gate of the fortieth transistor M40 is coupled to the second pull-up node PU2, a first pole of the fortieth transistor M40 is coupled to another second scan clock signal terminal CLKF ', and a second pole of the fortieth transistor M40 is coupled to a second composite signal output terminal OUT 2'.

A control electrode of the forty-first transistor M41 is coupled to the second pull-down node PD2, a first electrode of the forty-first transistor M41 is coupled to the second composite signal output terminal OUT2', and a second electrode of the forty-first transistor M41 is coupled to the second reset power supply terminal.

In the embodiment of the present disclosure, the shift register unit may not only provide a display driving pulse and a black insertion driving pulse for the first gate line G1 configured in the pixel unit, but also provide a sensing driving pulse for the second gate line G2 configured in the pixel unit, so that an independent gate driving circuit does not need to be configured for the second gate line, and thus the number of gate driving circuits in the display device may be effectively reduced, which is beneficial to the narrow frame design of the product.

Fig. 11 is a schematic circuit diagram of a shift register unit according to another embodiment of the present disclosure, as shown in fig. 11, in some embodiments, the shift register unit further includes a voltage control sub-circuit 10; the voltage control sub-circuit 10 is coupled to the first pull-up node PU1, the first working voltage terminal, and the voltage control node OFF, and configured to control a voltage at the first pull-up node PU1, and write the first working voltage VDD provided by the first working voltage terminal into the voltage control node OFF, where the first working voltage VDD is an active level.

Further, in some embodiments the shift register cell further comprises: a first leak-proof electronic circuit 11 and/or a second leak-proof electronic circuit 12. The shift register unit shown in fig. 11 includes both the first electron leakage preventing circuit 11 and the second electron leakage preventing circuit 12, which is only an example and not a limitation to the technical solution of the present disclosure. In the present disclosure, only the first leakage prevention electronic circuit 11 may be included without the second leakage prevention electronic circuit 12, and of course, the second leakage prevention electronic circuit 12 may be included without the first leakage prevention electronic circuit 11.

The first electron leakage prevention circuit 11 is coupled to the first reset voltage terminal, the voltage control node OFF and the display reset signal input terminal RST, the first electron leakage prevention circuit 11 is configured to write a first reset voltage provided by the first reset voltage terminal to the voltage control node OFF under the control of the display reset signal, the first reset voltage is at an inactive level, and the display write reset sub-circuit 1 is specifically configured to write a voltage at the voltage control node OFF to the first pull-up node PU1 and the second pull-up node PU2 under the control of the display reset signal.

The second leakage prevention electronic circuit 12 is coupled to the first reset voltage terminal, the voltage control node OFF and the control clock signal terminal BCK, the first leakage prevention electronic circuit 11 is configured to write the first reset voltage VGL1 provided by the first reset voltage terminal to the voltage control node OFF under the control of the control clock signal provided by the control clock signal terminal BCK, the first reset voltage VGL1 is at an inactive level, and the black insertion write reset sub-circuit 2 is specifically configured to write the voltage at the voltage control node OFF to the first pull-up node PU1 and the second pull-up node PU2 under the control of the control clock signal terminal BCK.

In the disclosure, by providing the first leakage-proof electronic circuit 11 and/or the second leakage-proof electronic circuit 12 to be used in combination with the voltage-controlling sub-circuit 10, the problem of unstable voltages at the first pull-up node PU1 and the second pull-up node PU2 caused by the leakage currents of the transistors (e.g., the second transistor M2, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8, etc.) in the display-write reset sub-circuit 1 and the black-insertion-write reset sub-circuit 2 can be effectively avoided, so that the accuracy of the voltages written into the first pull-up node PU1 and the second pull-up node PU2 at each stage can be improved, and the stable operation of the shift register unit can be ensured.

In some embodiments, the voltage control sub-circuit 10 includes a forty-second transistor M42, the first leakage prevention sub-circuit 11 includes a forty-third transistor M43, and the second leakage prevention sub-circuit 12 includes a forty-fourth transistor M44.

A control electrode of the forty-second transistor M42 is coupled to the first pull-up node PU1, a first electrode of the forty-second transistor M42 is coupled to the first operating voltage terminal (providing the first operating voltage VDD, which is an active level), and a second electrode of the forty-second transistor M42 is coupled to the voltage-control node OFF.

The forty-third transistor M43 is disposed between the second transistor M2 and the first reset voltage terminal, a control electrode of the forty-third transistor M43 is coupled to the display reset signal input terminal RST, a first electrode of the forty-third transistor M43 is coupled to the voltage control node OFF, and a second electrode of the forty-third transistor M43 is coupled to the first reset voltage terminal.

The forty-fourth transistor M44 is disposed between the sixth transistor M6 and the first reset voltage terminal, a control electrode of the forty-fourth transistor M44 is coupled to the control clock signal terminal BCK, a first electrode of the forty-fourth transistor M44 is coupled to the control voltage node OFF, and a second electrode of the forty-third transistor M43 is coupled to the first reset voltage terminal.

Accordingly, the first pole of the third transistor M3, the first pole of the seventh transistor M7, the second pole of the fourth transistor M4, and the second pole of the eighth transistor M8 are all coupled to the voltage control node OFF.

It should be noted that, in the display charging phase t1, after the first transistor M1 is turned on, the first pull-up node PU1 is charged to a high level by the display cascade signal, at this time, the forty-second transistor M42 is turned on, the first working voltage VDD at the active level is written into the voltage control node OFF through the forty-second transistor M42, and the voltage at the voltage control node OFF is at the high level, i.e., the active level. At this time, the third transistor M3 is turned on, and the voltage at the control voltage node OFF is written into the second pull-up node PU2 through the third transistor M3, i.e., the active level signal is written into the second pull-up node PU2 through the third transistor M3.

In the display reset period t3, the second transistor M2 and the forty-third transistor M43 are both turned on, the first reset voltage VGL1 at the inactive level is written to the voltage control node OFF and the first pull-up node PU1, the forty-second transistor M42 is turned OFF, and the voltage at the voltage control node OFF is at the inactive level. At this time, the third transistor M3 is turned on, and the voltage at the control voltage node OFF is written into the second pull-up node PU2 through the third transistor M3, i.e., the inactive level signal is written into the second pull-up node PU2 through the third transistor M3.

In the black insertion charging period t4, after the fifth transistor M5 is turned on, the first pull-up node PU1 is charged to a high level by the black insertion cascade signal, at this time, the forty-second transistor M42 is turned on, the first working voltage VDD at an active level is written to the voltage control node OFF through the forty-second transistor M42, and the voltage at the voltage control node OFF is at a high level, i.e., an active level. At this time, the seventh transistor M7 is turned on, and the voltage at the voltage control node OFF is written to the second pull-up node PU2 through the seventh transistor M7, i.e., the active level signal is written to the second pull-up node PU2 through the seventh transistor M7.

In the black insertion reset period t3, the sixth transistor M6 and the forty-fourth transistor M44 are both turned on, the first reset voltage VGL1 at the inactive level is written to the voltage control node OFF and the first pull-up node PU1, the forty-second transistor M42 is turned OFF, and the voltage at the voltage control node OFF is at the inactive level. At this time, the seventh transistor M7 is turned on, and the voltage at the voltage control node OFF is written to the second pull-up node PU2 through the seventh transistor M7, i.e., the inactive level signal is written to the second pull-up node PU2 through the seventh transistor M7.

In some embodiments, the first transistor M1, the fifth transistor M5, and the twenty-ninth transistor M29 may be configured with corresponding circuit structures for preventing current leakage, such as a forty-fifth transistor M45, a forty-sixth transistor M46, and a forty-seventh transistor M47 in fig. 11. Specific coupling relationships can be seen in fig. 11.

It should be noted that the shift register units shown in fig. 5, fig. 6, fig. 9, fig. 10, and fig. 11 are only some specific embodiments corresponding to the shift register unit shown in fig. 4, and the structures of these embodiments only serve as examples, and do not limit the technical solution of the present disclosure. In the present disclosure, the shift register unit may also adopt other circuit structures, which is not illustrated here.

Based on the same inventive concept, the embodiment of the present disclosure further provides a gate driving circuit, where the gate driving circuit includes a plurality of cascaded shift register units, and the shift register unit provided in the foregoing embodiment can be used as the shift register unit.

It should be noted that, in the shift register units shown in fig. 6, 9, 10, and 11, the (a) part and the (b) part can be respectively regarded as a shift register circuit (the shift register unit of one stage includes two shift register circuits), where the shift register circuit of one stage corresponds to one row of pixel units in the display area. When the M shift register units are sequentially arranged to form a gate driving circuit, the gate driving circuit can be regarded as including 2M cascaded shift register circuits, and the gate driving circuit can be used for driving M rows of pixel units in the display area. In fig. 6, 9, 10 and 11, (a) the shift register circuits corresponding to the parts are shift register circuits located at odd-numbered stages in the gate driving circuit, and (b) the shift register circuits corresponding to the parts are shift register circuits located at even-numbered stages in the gate driving circuit; (a) the shift register circuit corresponding to part corresponds to the pixel units positioned in the odd-numbered rows in the display area, and the shift register circuit corresponding to part (b) corresponds to the pixel units positioned in the even-numbered rows in the display area.

Further, in the gate driver circuit, the shift register circuits located at odd-numbered stages (i.e., the shift register circuits corresponding to the part (a)) are used for implementing display driving cascade, and the shift register circuits located at even-numbered stages (i.e., the shift register circuits corresponding to the part (b)) are used for implementing black insertion driving cascade; or, the shift register circuits at the odd-numbered stages are used for realizing the black insertion driving cascade, and the shift register circuits at the even-numbered stages are used for realizing the display driving cascade. In practical application, the design can be carried out according to actual needs.

In some embodiments, a display cascade signal input terminal of the mth stage shift register unit is coupled to a display cascade signal output terminal of the M-a stage shift register unit, a display reset signal input terminal of the mth stage shift register unit is coupled to a display cascade signal output terminal of the M + b stage shift register unit, a black insertion cascade signal input terminal of the mth stage shift register unit is coupled to a black insertion cascade signal output terminal of the M-c stage shift register unit, a, b, and c are respectively preset positive integers, a + b is less than or equal to c, M is a positive integer and satisfies a < M, c < M, and M + b is less than or equal to M. The display cascade signal input terminals of the first a-stage shift register units SRU 1-SRUa are coupled to the display frame start signal input terminal (for providing the display frame start signal STV), the display reset signal input terminals of the second b-stage shift register units SRUM-b + 1-SRUM are coupled to the display frame reset signal input terminal (for providing the display frame reset signal), and the black insertion cascade signal input terminals of the first c-stage shift register units SRU 1-SRUc are coupled to the black insertion frame start signal input terminal (for providing the black insertion frame start signal BSTV).

Fig. 12 is a schematic circuit structure diagram of a gate driving circuit according to an embodiment of the disclosure, fig. 13 is a schematic circuit structure diagram of a first shift register unit group according to an embodiment of the disclosure, fig. 14 is a schematic circuit structure diagram of a second shift register unit group according to an embodiment of the disclosure, fig. 15 is a schematic circuit structure diagram of a third shift register unit group according to an embodiment of the disclosure, as shown in fig. 12 to 15, the gate driving circuit 200 is configured with 3 control clock signal lines BK1 to BK3, M shift register units are divided into a plurality of first shift register unit groups a, a plurality of second shift register unit groups B, and a plurality of third shift register unit groups C, the first shift register unit groups a, the second shift register unit groups B, and the third shift register unit groups C are alternately arranged in sequence, the number of shift register units in the first shift register group a, the unit groups B, and the third shift register unit groups C are arranged in sequence, The number of shift register units in the second shift register unit group B and the number of shift register units in the third shift register unit group C are both C.

Control clock signal terminals CKB of the shift register units SRU1, SRU2, SRU3, SRU4 in the first shift register unit group a are coupled to 1 control clock signal line BK1, control clock signal terminals CKB of the shift register units SRU5, SRU6, SRU7, SRU8 in the second shift register unit group B are coupled to the other 1 control clock signal line BK2, and control clock signal terminals CKB of the shift register units SRU9, SRU10, SRU11, SRU12 in the third shift register unit group C are coupled to the remaining 1 control clock signal line BK 3.

With continued reference to fig. 12 to 15, in some embodiments, the gate driving circuit is configured with 6c first scan clock signal lines CKE1 to CKE24, the 6c first scan clock signal lines are divided into first signal line groups CKE1 to CKE8, second signal line groups CKE9 to CKE16 and third signal line groups CKE17 to CKE24, and the number of the first scan clock signal lines in the first signal line groups CKE1 to CKE8, the number of the first scan clock signal lines in the second signal line groups CKE9 to CKE16 and the number of the first scan clock signal lines in the third signal line groups CKE17 to CKE24 are all 2 c.

Referring to fig. 13, two first scan clock signal terminals CLKE, CLKE' of the i-th shift register unit in the first shift register unit group are coupled to the 2i-1 first scan clock signal line and the 2 i-th first scan clock signal line in the first signal line group CKE 1-CKE 8, respectively; referring to fig. 14, two first scan clock signal terminals CLKE, CLKE' of the i-th shift register unit in the second shift register unit group are coupled to the 2i-1 first scan clock signal line and the 2 i-th first scan clock signal line in the second signal line group CKE 9-CKE 16, respectively; referring to fig. 15, two first scan clock signal terminals CLKE, CLKE' of the i-th shift register unit in the third shift register unit group are coupled to the 2i-1 first scan clock signal line and the 2 i-th first scan clock signal line in the third signal line group CKE 17-CKE 24, respectively; wherein i is a positive integer and i is less than or equal to c.

With continued reference to fig. 12 to 15, in some embodiments, the gate driving circuit is configured with 6c cascaded clock signal lines, the 6c cascaded clock signal lines CKD1 to CKD24 are divided into a fourth signal line group CKD1 to CKD8, a fifth signal line group CKD9 to CKD16 and a sixth signal line group CKD17 to CKD24, and the number of cascaded clock signal lines in the fourth signal line group CKD1 to CKD8, the number of cascaded clock signal lines in the fifth signal line group CKD9 to CKD16 and the number of cascaded clock signal lines in the sixth signal line group CKD17 to CKD24 are all 2 c.

Referring to fig. 13, two cascade clock signal terminals CLKD, CLKD' of the ith shift register unit in the first shift register unit group a are coupled to the 2i-1 and 2i cascade clock signal lines in the fourth signal line group CKD 1-CKD 8, respectively; referring to fig. 14, two cascade clock signal terminals CLKD and CLKD' of the ith shift register unit in the second shift register unit group are coupled to the 2i-1 and 2i cascade clock signal lines in the fifth signal line group CKD 9-CKD 16, respectively; referring to fig. 15, two cascade clock signal terminals CLKD and CLKD' of the i-th shift register unit in the third shift register unit group are coupled to the 2i-1 th cascade clock signal line and the 2 i-th cascade clock signal line in the sixth signal line group CKD17 to CKD24, respectively.

Referring to fig. 12, in some embodiments, c has a value of 4. Referring to fig. 12, as a specific example, 4 shift register cells SRU <1-4> of the 1 st-order shift register cell SRU1 to the 4 th-order shift register cell SRU4 constitute one first shift register cell group a; 4 shift register units SRU <5-8> of the 5 th-8 th stage shift register units SRU 5-SRU 8 constitute a second shift register unit group B; 4 shift register units SRU <9-12> of the 9 th-12 th stage shift register units SRU 9-SRU 12 constitute a third shift register unit group C; 4 shift register units SRU <13-16> of the 13 th-16 th stage shift register units SRU 1-SRU 4 constitute a first shift register unit group a; 4 shift register units SRU <17-20> of the 17 th-20 th-stage shift register units SRU 17-SRU 20 constitute a second shift register unit group B; the 4 shift register cells SRU <21-24> of the 21 st stage shift register cell SRU21 to the 24 th stage shift register cell SRU24 constitute a third shift register cell group C, and so on. Accordingly, the gate driving circuit is provided with 3 control clock signal lines BK1 to BK3, 24 first scan clock signal lines CKE1 to CKE24, and 24 cascade clock signal lines CKD1 to CKD 24.

At this time, when c is 4, the values of a and b may be as follows: 1) a takes the value 1 and b takes the value 1; 2) a takes the value 1 and b takes the value 2; 3) a takes the value 1 and b takes the value 3; 4) a takes the value of 2 and b takes the value of 1; 5) a takes the value of 2 and b takes the value of 2; 6) a takes the value 3 and b takes the value 1. The values of a and b determine the cascade relation among the shift register units in the display driving process.

Fig. 16 is an operation timing diagram of the gate driving circuit shown in fig. 12, and as shown in fig. 16, the gate driving circuit alternately performs a display driving period J1 and a black insertion driving period J2 during operation; in addition, the gate driving circuit performs display driving on a certain 8 rows of pixel units in a display driving phase J1, and performs black insertion driving on a certain 8 rows of pixels in a black insertion driving phase J2. The detailed working process is not described herein.

The embodiment of the disclosure also provides a display device, which comprises the gate driving circuit provided by the previous embodiment.

The display device provided by the embodiment of the disclosure may be: any product or component with a display function, such as a display panel, a flexible wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

Fig. 17 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure, and as shown in fig. 17, the shift register unit employs the shift register provided in the above embodiment, and the driving method of the shift register unit includes:

step S101, the display write reset sub-circuit writes the active level signal into the first pull-up node and the second pull-up node under the control of the display cascade signal, the first output sub-circuit writes the cascade clock signal provided by one cascade clock signal terminal into one cascade signal output terminal under the control of the voltage at the first pull-up node, and writes the first scan clock signal provided by one first scan clock signal terminal into one first composite signal output terminal, and writes the cascade clock signal provided by the other cascade clock signal terminal into the other cascade signal output terminal under the control of the voltage at the second pull-up node, and writes the first scan clock signal provided by the other first scan clock signal terminal into the other first composite signal output terminal.

And step S102, the display writing reset sub-circuit writes the non-effective level signal into the first pull-up node and the second pull-up node under the control of the reset cascade signal.

Step S103, the black insertion writing reset sub-circuit writes the effective level signal into the first pull-up node and the second pull-up node under the control of the black insertion cascade signal, the first output sub-circuit writes the cascade clock signal provided by one cascade clock signal terminal into one cascade signal output terminal under the control of the voltage at the first pull-up node, and writes the first scan clock signal provided by one first scan clock signal terminal into one first composite signal output terminal, and writes the cascade clock signal provided by the other cascade clock signal terminal into the other cascade signal output terminal under the control of the voltage at the second pull-up node, and writes the first scan clock signal provided by the other first scan clock signal terminal into the other first composite signal output terminal.

And step S104, the black insertion writing reset sub-circuit writes the non-effective level signal into the first pull-up node and the second pull-up node under the control of the control clock signal.

The detailed description of the above steps S101 to S104 can be related to the operation of the shift register unit described above, and will not be described herein again.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A shift register cell, comprising:

2. The shift register cell of claim 1, wherein the black insertion write reset subcircuit comprises: a first black insertion writing transistor, a second black insertion writing transistor, a first black insertion reset transistor, and a second black insertion reset transistor;

3. The shift register cell according to claim 1 or 2, further comprising:

and/or, the shift register unit further comprises: a second leak-proof electronic circuit coupled to the first reset voltage terminal, the voltage-controlled node, and the control clock signal terminal, the second leak-proof electronic circuit configured to write a first reset voltage provided by the first reset voltage terminal to the voltage-controlled node under control of the control clock signal, the first reset voltage being a non-active level, the black insertion write reset sub-circuit specifically configured to write a voltage at the voltage-controlled node to the first pull-up node and the second pull-up node under control of the control clock signal.

4. The shift register cell according to claim 1 or 2, further comprising:

5. The shift register cell according to claim 1 or 2, further comprising:

the first output sub-circuit is further coupled to the first and second pull-down nodes, and is further configured to write an inactive level signal to two cascaded signal outputs and two first composite signal outputs under control of a voltage at the first and second pull-down nodes.

6. The shift register cell of claim 5, further comprising:

7. The shift register cell according to claim 1 or 2, further comprising:

8. A gate drive circuit, comprising: a plurality of cascaded shift register cells, said shift register cells employing the shift register cells of any of claims 1-7 above.

9. The gate driving circuit according to claim 8, wherein the gate driving circuit comprises M stages of shift register units, one of the two cascade signal output terminals of each shift register unit is a display cascade signal output terminal, and the other is a black insertion cascade signal output terminal;

10. The gate driving circuit according to claim 9, wherein the M shift register cells are divided into a plurality of first shift register cell groups, a plurality of second shift register cell groups, and a plurality of third shift register cell groups, the first shift register cell groups, the second shift register cell groups, and the third shift register cell groups are alternately arranged in sequence, and the number of shift register cells in the first shift register cell group, the number of shift register cells in the second shift register cell group, and the number of shift register cells in the third shift register cell group are all c;

the grid driving circuit is provided with 3 control clock signal lines;

11. The gate driving circuit according to claim 10, wherein the gate driving circuit is configured with 6c first scan clock signal lines, the 6c first scan clock signal lines are divided into a first signal line group, a second signal line group and a third signal line group, and the number of the first scan clock signal lines in the first signal line group, the number of the first scan clock signal lines in the second signal line group and the number of the first scan clock signal lines in the third signal line group are all 2 c;

i is a positive integer and i is less than or equal to c.

12. The gate driving circuit according to claim 10, wherein the gate driving circuit is configured with 6c cascaded clock signal lines, the 6c cascaded clock signal lines are divided into a fourth signal line group, a fifth signal line group and a sixth signal line group, and the number of the cascaded clock signal lines in the fourth signal line group, the number of the cascaded clock signal lines in the fifth signal line group and the number of the cascaded clock signal lines in the sixth signal line group are all 2c

i is a positive integer and i is less than or equal to c.

13. A gate drive circuit as claimed in any one of claims 9 to 12, wherein c is 4.

14. A display device, comprising: a gate drive circuit as claimed in any one of claims 8 to 13.

15. A driving method of a shift register unit employing the shift register unit according to any one of claims 1 to 7, the driving method comprising: