CN113342570B - Dual-target state elimination coding and decoding method adaptive to 3D TLC type NAND flash memory data storage - Google Patents

Dual-target state elimination coding and decoding method adaptive to 3D TLC type NAND flash memory data storage Download PDF

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CN113342570B
CN113342570B CN202110672534.9A CN202110672534A CN113342570B CN 113342570 B CN113342570 B CN 113342570B CN 202110672534 A CN202110672534 A CN 202110672534A CN 113342570 B CN113342570 B CN 113342570B
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state
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flash memory
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CN113342570A (en
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魏德宝
张京超
朴哲龙
冯骅
乔立岩
彭喜元
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Harbin Institute of Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Abstract

The invention provides a double-target state elimination coding and decoding method adaptive to 3D TLC type NAND flash memory data storage, wherein the data of a cell is preprocessed through an encoder, 3-bit information can be stored in each cell, the number of the cells is 8, the number of the states N is 8, the 8 states are pairwise and equally divided into 4 groups, and the groups are marked as Gi; setting one group of GX as a target elimination double state, dividing an original data stream according to the length of a word line, taking 4 cells as a coded code segment, recording the number num (N) of 8 states in the 4 cell code segment, and combining the states according to the states in the code segment to obtain a remapping coding method; storing the remapped and encoded information into different blocks of the flash memory; the decoder remaps the 4-cell code segment into original data according to the flag bit; the method can be used as a general method, and the reliability of the 3D TLC type NAND flash memory is improved.

Description

Dual-target state elimination coding and decoding method adaptive to 3D TLC type NAND flash memory data storage
Technical Field
The invention belongs to the field of nonvolatile storage, and particularly relates to a double-target state elimination coding and decoding method adaptive to 3D TLC type NAND flash memory data storage.
Background
At present, a 3D TLC (Trinary-Level Cell, in which 3-bit information is stored in each Cell) type NAND flash memory is widely applied to non-volatile storage scenarios such as a solid-state disk, and a large number of studies indicate that the data storage reliability of the 3D TLC type NAND flash memory is closely related to a programmed threshold voltage distribution mode.
In recent years, 3D TLC type NAND flash memory is widely used as a solution for non-volatile storage media due to its advantages of low access delay, low power consumption, high shock resistance, etc., however, the advancement of integration processes also causes a great reduction in the reliability of NAND flash memory in addition to the realization of lower bit cost and higher integration level of flash memory, taking wear endurance against write/erase cycles as an example, a conventional SLC (Single-Level Cell) type NAND flash memory can achieve wear endurance of more than 10 ten thousand times, the 3D TLC type NAND flash suffers from several thousands of wear, which causes a serious distortion of the stored data, therefore, how to extend the lifetime of the device by introducing an appropriate reliability management method is an important research topic for the application of the non-volatile memory system based on the 3D TLC type NAND flash memory.
Disclosure of Invention
The invention provides a double-target state elimination coding and decoding method adaptive to data storage of a 3D TLC type NAND flash memory, which is used for realizing programming of the 3D TLC type NAND flash memory in a data mode of eliminating two target states, further inhibiting various main state conversion error types and obviously improving the reliability of the 3D TLC type NAND flash memory in various storage application scenes.
The invention is realized by the following scheme:
a double-target state elimination coding and decoding method adaptive to data storage of a 3D TLC type NAND flash memory comprises the following steps:
the method comprises the following steps:
the method comprises the following steps: preprocessing cell data through an encoder, wherein 3-bit information can be stored in each cell, and the cells have 8 states N, namely ER, A, B, C, D, E, F and G;
step two: pairwise pairing the 8 states into 4 groups, and marking as GiWherein i is 1,2, 3, 4; set one group GXFor the double state of target elimination, dividing the original data stream according to the length of a word line, taking 4 cells as a coded code segment, recording the number num (N) of 8 states in the 4 cell code segment, and combining the states according to the states in the code segment to obtain a remapping coding method;
step three: storing the remapped and encoded information into different blocks of the flash memory;
step four: the decoder remaps the 4-cell code segment from step three to the original data according to the flag bit.
Further, the air conditioner is provided with a fan,
let the threshold voltage of the cell be identified as [ V ]TH-1，VTH]Wherein TH ═ a, b, c, d, e, f, g;
the right adjacent state is that the threshold voltage of the current cell is increased to exceed the right boundary V of the threshold voltage window of the current cell in the process of data storageTHThe current cell state N will be converted to the next state cell state N +1, which results in a left bias error;
the left-adjacent state is that the threshold voltage of the current cell is reduced by more than the left boundary V of the threshold voltage window in the data storage processTH-1The current cell state N will be converted to the previous state cell state N-1, which results in a right bias error.
Further, the air conditioner is provided with a fan,
let X be GXThe state in (1), starting with i-1 and incrementally searching,
when there are two states of a certain group that are not present in the 4-cell code segment, i.e., there is GyTwo states Y therein1And Y2Satisfy num (Y)1)+num(Y2) 0; then according to the target eliminated two-state GXWherein the two states are respectively X1And X2Since 4 cells are used as a code segment for coding, there are four possibilities for this case, and the remapping scheme is X1→Y1And X2→Y2；
If all the states of all the groups appear, the number of the states appearing in each group is 1, namely G existszLet two of the missing states be Z1And Z2I.e. satisfies num (X)n) 1 and num (Z)n) 0, wherein n is 1, 2; then the remapping method adopted for the 4-cell code segment to be encoded at this time is Xn→ZnI.e. G which may occur in 4 cells to be codedxAnd GzThe combination has four possibilities, respectivelyIs X1→Z1，X1→Z2，X2→Z1And X2→Z2。
Further, the elimination of the target double state is realized under the condition that the 4-cell code segment to be coded has 8 kinds of remapping, the 8 remapping methods are respectively recorded by using 1 flag bit of 3-bit, the 8 remapping methods are used for data recovery in the decoding process, and each generated 3-bit flag bit is completely stored in the flash memory cell.
Further, after all the original data with the length of 1 word line is coded as a code segment by every 4 cells, a flag bit cell sequence with the length of 1 word line and the length of 1/4 word lines of the coded data with the double-target state elimination is obtained, and the two data are respectively stored in different blocks of the flash memory.
Further, the air conditioner is provided with a fan,
the work flow of the decoder is as follows:
s1: the left boundary of the threshold voltage window of the dual-target elimination state is shifted to the right to read the reference voltage, and the right bias error of the left adjacent state of the elimination state is restrained;
s2: reading data of a word line from the NAND flash memory;
s3: correcting the cell in the threshold voltage window of the elimination state as the right adjacent state of the elimination state by default, and inhibiting the left deviation error of the right adjacent state of the elimination state;
s4: reading a flag bit cell sequence corresponding to the word line;
s5: splitting data to be decoded into a group of code segments according to 4 cells;
s6: judging whether the data of the word line are decoded, if not, performing step S7, and if so, performing step S8;
s7: for each 4-cell modulation data split, reflecting the original 4-cell data back according to the corresponding zone bit cell;
s8: the demapped 4-cell code segments are integrated into the original data stream output of 1 word line.
The invention has the beneficial effects
(1) The invention realizes a data storage scheme for programming a 3D TLC type in a data form eliminating two unreliable target states, and eliminates state transition errors caused by the two states;
(2) on the basis of eliminating state conversion errors caused by two unreliable states, the invention further corrects the cell elements which are caused by the state conversion errors and fall in the threshold voltage window of the elimination state, thereby inhibiting the state conversion errors of the left adjacent state and the right adjacent state of the double-target elimination state;
(3) according to the invention, because the cell state reliability difference of the 3D TLC type NAND flash memory is ubiquitous in various application storage scenes, the encoding and decoding method can be used as a general method to realize the reliability improvement of the 3D TLC type NAND flash memory.
Drawings
FIG. 1 is a schematic diagram of the present invention illustrating the state erasure of a multi-level cell flash memory by data modulation;
FIG. 2 is a schematic diagram of the relationship between the cell threshold voltage and the stored 3-bit information of a 3D TLC type NAND flash memory chip according to the present invention;
FIG. 3 is an example of state transitions of the present invention;
fig. 4 shows the suppression of the primary state transition type after a cell in one state is erased;
FIG. 5 is an example of a remapping method to eliminate the B-state and the E-state;
FIG. 6 is a flow chart of the demapping of the decoder;
fig. 7 is an example of the codec method to improve the reliability of the 3D TLC type NAND flash memory.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments; all other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A double-target state elimination coding and decoding method adaptive to data storage of a 3D TLC type NAND flash memory comprises the following steps:
the method comprises the following steps:
the method comprises the following steps: preprocessing cell data through an encoder, wherein 3-bit information can be stored in each cell, and the cells have 8 states N, namely ER, A, B, C, D, E, F and G;
step two: the 8 states of the 3D TLC type NAND flash memory are pairwise equally divided into 4 groups, which are marked as GiWherein i is 1,2, 3, 4; set one group GXDual state (X) for targeted elimination1And X2) Dividing an original data stream according to the length of a word line, taking 4 cells as a coded code segment, recording the number num (N) of 8 states in the 4 cell code segment, and combining the states according to the states in the code segment to obtain a remapping coding method;
step three: storing the remapped and encoded information into different blocks of the flash memory;
step four: the decoder remaps the 4-cell code segment from step three to the original data according to the flag bit.
As shown in fig. 1, if random data is directly written into one block of the 3D TLC type NAND flash memory, it can be found that the number of cells programmed to various states is almost equal, and by pre-writing the data into the flash memory according to the encoding method of the present patent, the elimination of two target state cells can be achieved.
The principle of implementing the non-volatile storage by the TLC type NAND flash memory will be briefly described. Flash memory stores information by injecting electrons into its internal cells, which, after being injected into the cell, cause a threshold voltage (V) to develop across the cellTH) In the 3D TLC type NAND flash memory, 3-bit information can be stored in each cell, as shown in fig. 2, the relationship between the threshold voltage of the 3D TLC type NAND flash memory chip and the stored information is shown, wherein the abscissa represents the threshold voltage of the cell, the ordinate represents the number of cells, and the flash memory internal circuit judges the stored information by reading the threshold voltage of the cell, for example, if the threshold voltage of a cell is identified as being at Va,Vb]In the interval, the flash memory internal circuit recognizes the cell as the B state, and outputs information stored in the cell as "001".
The two target states are respectively a right adjacent state and a left adjacent state;
ideally, a cell will be in the programmed state after programming is complete without change, and in practice, the number of electrons trapped in the cell will change, causing the threshold voltage to shift, resulting in a state transition. A cell is said to be right biased erroneous (e.g., an a state cell is converted to a B state cell) if its threshold voltage rises above the right boundary of its threshold voltage window during data storage, and conversely, a cell is said to be left biased erroneous (e.g., an E state cell is converted to a D state cell) if its threshold voltage falls below the left boundary of its threshold voltage window during data storage, and is converted to its left neighboring state.
Let the threshold voltage of the cell be identified as [ V ]TH-1，VTH]Wherein TH ═ a, b, c, d, e, f, g;
the right adjacent state is that the threshold voltage of the current cell is increased to exceed the right boundary V of the threshold voltage window of the current cell in the process of data storageTHThe current cell state N is converted to the next state cell state N + 1;
the left-adjacent state is that the threshold voltage of the current cell is reduced by more than the left boundary V of the threshold voltage window in the data storage processTH-1The current cell state N is converted to the previous state cell state N-1.
A lot of research shows that the probability of error of individual states in TLC type NAND flash is very asymmetric, and considering that in most storage scenarios, the data written in flash is almost random, i.e. the number of cells programmed to each state is almost equal, a feasible method for improving the reliability of flash is to modulate the stored data so that as few cells as possible are programmed to unreliable states. The method provided by the patent is a limit condition of the idea, namely two unreliable states are eliminated, and the overall error rate of stored data in the same cell area overhead is further reduced.
After the elimination of the dual target state cell in step one, the current cell state is eliminated, the threshold voltage window right boundary V of the previous cell state N-1TH-1Increasing the left boundary V of the threshold voltage window for the next cell state N +1THAnd decreases.
Referring to fig. 3, the number of various state transitions counted by the retention error is counted for a 3DTLC NAND flash memory chip. A retention error refers to an error in which electrons stored in a flash memory cell leak over time, thereby causing a change in the cell storage information. We first wear out the flash memory chip for 1500 write/erase cycles (wear endurance recommended in chip handbook), then write random data and leave the chip at 85 ℃ to produce a 1 year retention effect at room temperature, and from this figure it can be seen that although there are 56(7x8) cases of state transitions, the probability of these state transitions occurring is very different. Specifically, the difference is represented by two aspects, on one hand, the state transition mainly occurs between adjacent states, and on the other hand, the occurrence probability of the state transition between the adjacent states shows a significant asymmetric distribution, i.e., there is a large difference between the reliability of the states of the cells.
In the following, the effect of improving the overall reliability of the flash memory after the cells in a certain state are eliminated is discussed, and as shown in fig. 4, if the B-state cells in the programmed 3DTLC NAND flash memory are eliminated after data modulation, it is first known that all the state transition types caused by the B-state are eliminated, i.e. there is no B-state present>X type state transitions. In addition, because state transitions occur primarily between adjacent states, a can be aligned to a falling within the B-state threshold voltage window>B and C>B two state transition types further inhibit, in particular, the read reference voltage VaAppropriate right shifting to correct the red area a-state cells followed by the blue area cells being corrected to the C-state by default.
Let X be GxThe state in (1), starting with i-1 and incrementally searching,
code in the 4-cell when there are two states of a certain groupWhen none of the segments is present, i.e. G is presentyTwo states Y therein1And Y2Satisfy num (Y)1)+num(Y2) 0; then according to the target eliminated two-state GXWherein the two states are respectively X1And X2Since 4 cells are used as a code segment for coding, there are four possibilities for this case, and the remapping scheme is X1→Y1And X2→Y2；
If all the states of all the groups appear, the number of the states appearing in each group is 1, namely G existszLet two of the missing states be Z1And Z2I.e. satisfies num (X)n) 1 and num (Z)n) 0, wherein n is 1, 2; then the remapping method adopted for the 4-cell code segment to be encoded at this time is Xn→ZnI.e. G which may occur in 4 cells to be codedxAnd GzThe combination has four possibilities, X1→Z1，X1→Z2，X2→Z1And X2→Z2。
From the above, the target dual-state elimination is realized under the condition that the 4-cell code segment to be coded has 8 kinds of remapping, the 8 kinds of remapping methods are respectively recorded by using 1 flag bit of 3-bit, the 8 kinds of remapping methods are used for data recovery in the decoding process, and each generated 3-bit flag bit is completely stored in the flash memory cell.
An example of implementing the elimination of the B and E states is shown in fig. 5.
After all the original data with the length of 1 word line is coded as a code segment by taking each 4 cells, a flag bit cell sequence with the length of 1 word line and the length of 1/4 word lines of the coded data with the double-target state elimination is obtained, and the two data are respectively stored in different blocks of the flash memory.
The decoder operation is shown in fig. 6, which is basically the reverse of the encoder operation, and the main function is to remap the data-modulated 4-cell code segment to the original data according to the flag bits. It should be noted that, in the user area data reading step, the cells falling within the threshold voltage window of the dual target erase state need to be corrected according to the method shown in fig. 3, that is, the left boundary read reference voltage of the threshold voltage window of the dual target erase state is properly shifted to the right, and the remaining cells falling within the threshold voltage window of the dual target erase state are corrected to the right adjacent state.
The work flow of the decoder is as follows:
s1: the left boundary of the threshold voltage window of the dual-target elimination state is shifted to the right to read the reference voltage, and the right bias error of the left adjacent state of the elimination state is restrained;
s2: reading data of a word line from the NAND flash memory;
s3: correcting the cell in the threshold voltage window of the elimination state as the right adjacent state of the elimination state by default, and inhibiting the left deviation error of the right adjacent state of the elimination state;
s4: reading a flag bit cell sequence corresponding to the word line;
s5: splitting data to be decoded into a group of code segments according to 4 cells;
s6: judging whether the data of the word line are decoded, if not, performing step S7, and if so, performing step S8;
s7: for each 4-cell modulation data split, reflecting the original 4-cell data back according to the corresponding zone bit cell;
s8: the demapped 4-cell code segments are integrated into the original data stream output of 1 word line.
The 3d tlc type NAND flash memory is programmed in a data form of eliminating two states in such a manner that 1 flag bit cell is added per 4 cell code segment, and has an effect that a state transition error caused by the two states can be eliminated.
The read reference voltage at the lower boundary of the erase state threshold voltage window is appropriately shifted to the right before the read operation is performed on the 3D TLC type NAND flash memory, with the effect that a right bias error of a left-adjacent state of the erase state can be suppressed.
After data is read out from the 3D TLC type NAND flash memory and before being input to the decoder, cells within the erase state threshold voltage window are corrected by default to the right-adjacent state of the erase state, which has the effect of suppressing left-bias errors in the right-adjacent state of the erase state.
The 3D TLC type NAND flash memory reliability improvement effect of the encoding and decoding method is as follows:
as shown in fig. 7, after writing random data and modulated data into a flash memory block subjected to 1500 write/erase cycles, respectively, and placing the flash memory block in an environment of 85 ℃ to generate a retention effect equivalent to 1 year at normal temperature, it is observed that the overall error rate is reduced by 86% on average when data is stored according to the proposed encoding and decoding method.
The above describes in detail a dual-target state elimination encoding and decoding method adapted to 3D TLC type NAND flash data storage proposed by the present invention, and a numerical simulation example is applied in the text to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (6)

1. A double-target state elimination coding and decoding method adaptive to data storage of a 3DTLC type NAND flash memory is characterized by comprising the following steps:
the method comprises the following steps:
the method comprises the following steps: preprocessing cell data through an encoder, wherein 3-bit information can be stored in each cell, and the cells have 8 states N, namely ER, A, B, C, D, E, F and G;
step two: pairwise pairing the 8 states into 4 groups, and marking as GiWherein i is 1,2, 3, 4; set one group GXFor the eliminated double-target state, dividing the original data stream according to the length of a word line, taking 4 cells as a coded code segment, recording the number num (N) of 8 states in the 4 cell code segment, and combining the states in the code segment to obtain a remapping coding method;
step three: storing the remapped and encoded information into different blocks of the flash memory;
step four: the decoder remaps the 4-cell code segment from step three to the original data according to the flag bit.
2. The method of claim 1, further comprising:
let the threshold voltage of the cell be identified as [ V ]TH-1，VTH]Wherein TH ═ a, b, c, d, e, f, g;
the right adjacent state is that the threshold voltage is increased to exceed the right boundary V of the threshold voltage window of the right adjacent state in the data storage process of the current cellTHThe current cell state N will be converted to the next cell state N +1, the right neighbor state causing a left bias error;
the left adjacent state is that the threshold voltage is reduced by more than the left boundary V of the threshold voltage window of the left adjacent state in the data storage process of the current cellTH-1The current cell state N will be converted to the last cell state N-1, which results in a right bias error.
3. The method of claim 2, further comprising:
let X be GXThe state in (1), starting with i-1 and incrementally searching,
when there are two states of a certain group that are not present in the 4-cell code segment, i.e., there is GyTwo states Y therein1And Y2Satisfy num (Y)1)+num(Y2) 0; according to the eliminated dual target state GXWherein the two target states GXAre each X1And X2Since 4 cells are used as a code segment for coding, there are four possibilities for this case, and the remapping method is X1→Y1，X1→Y2，X2→Y1And X2→Y2；
If all the states of all the groups appear, the number of the states appearing in each group is 1, namely G existszLet two of the missing states be Z1And Z2I.e. satisfies num (X)n) 1 and num (Z)n) 0, wherein n is 1, 2; then the remapping method adopted for the 4-cell code segment to be encoded at this time is Xn→ZnI.e. G which may occur in 4 cells to be codedxAnd GzThe combination has four possibilities, X1→Z1，X1→Z2，X2→Z1And X2→Z2。
4. The method of claim 3, further comprising: the 4 cell code segments to be coded have 8 kinds of remapping conditions to realize the elimination of double-target states, the 8 kinds of remapping conditions are respectively recorded by using 1 flag bit of 3-bit, the 8 kinds of remapping conditions are used for data recovery in the decoding process, and each generated 3-bit flag bit is completely stored in a flash memory cell.
5. The method of claim 4, further comprising: after all the original data with the length of 1 word line is coded as a code segment by taking each 4 cells, a flag bit cell sequence with the length of 1 word line and the length of 1/4 word lines of the coded data with the double-target state elimination is obtained, and the two data are respectively stored in different blocks of the flash memory.
6. The method of claim 5, further comprising:
the work flow of the decoder is as follows:
s1: shifting right the left boundary reference voltage of the dual-target elimination state threshold voltage window, and inhibiting the right bias error of the left adjacent state of the dual-target elimination state;
s2: reading data of a word line from the NAND flash memory;
s3: correcting the cell element in the threshold voltage window of the double-target elimination state as the right adjacent state of the double-target elimination state by default, and inhibiting the left deviation error of the right adjacent state of the double-target elimination state;
s4: reading a flag bit cell sequence corresponding to the word line;
s5: splitting data to be decoded into a group of code segments according to 4 cells;
s6: judging whether the data of the word line are decoded, if not, performing step S7, and if so, performing step S8;
s7: for each 4-cell modulation data split, reflecting the original 4-cell data back according to the corresponding zone bit cell;
s8: the demapped 4-cell code segments are integrated into the original data stream output of 1 word line.
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