CN113327854A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN113327854A
CN113327854A CN202110537232.0A CN202110537232A CN113327854A CN 113327854 A CN113327854 A CN 113327854A CN 202110537232 A CN202110537232 A CN 202110537232A CN 113327854 A CN113327854 A CN 113327854A
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semiconductor device
type
grooves
groove
manufacturing
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姜春亮
赵浩宇
李伟聪
林泳浩
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Vanguard Semiconductor Co Ltd
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Vanguard Semiconductor Co Ltd
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Priority to CN202110537232.0A priority Critical patent/CN113327854A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

Abstract

The application discloses a preparation method of a semiconductor device, the method comprises the steps that a plurality of grooves which are arranged in an array mode are etched in a first conduction type drift region formed on a semiconductor substrate of a first conduction type, connecting holes which are arranged in an array mode are further etched in partial grooves of the grooves, and the formed grooves with the connecting holes can greatly reduce the distance between the grooves, so that the number of cells in a unit area of a chip is greatly increased, a current path is increased, and the through-current capacity of the unit area of the chip is further improved; the enhancement of the through-current capability can greatly improve the extreme impact resistance of the chip; in addition, the groove provided with the connecting hole is connected with the top electrode through the connecting hole, a carrier channel is formed when the groove is opened, in order to maintain electric neutrality, another opposite carrier is induced in the grid groove, the electron concentration is increased when the channel is conducted, the channel resistance is reduced, and the on resistance Rds (on) of the whole semiconductor device is reduced.

Description

Method for manufacturing semiconductor device
Technical Field
The application relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
The gate trench of a Semiconductor device is formed into a U-shaped trench, for example, a gate trench of a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is formed into a U-shaped trench, that is, a U-shaped Double-diffused MOSFET (udmos) is formed. Referring to fig. 1, a conventional semiconductor device (e.g., UDMOS) usually requires a connection hole formed between trenches by an etching process to connect an emitter metal and a substrate together, thereby forming a via between an emitter and a drain. Due to the limitation of process capability, the distance between a part of the trenches is usually sacrificed when the connection holes are formed, thereby limiting the number of cells in a unit area of the chip.
For this reason, development of a semiconductor device that facilitates reduction in the distance from trench to trench is urgently required.
Disclosure of Invention
In view of the above, the present application provides a method for manufacturing a semiconductor device, so as to obtain a semiconductor device capable of improving a distance between trenches.
The application provides a preparation method of a semiconductor device, which comprises the following steps: s1, providing a semiconductor substrate of a first conductivity type having a bottom electrode on one surface, and forming a drift region of the first conductivity type on the other surface of the semiconductor substrate disposed opposite to the one surface; s2, forming a plurality of grooves in the first conductive type drift region by adopting first etching, wherein the grooves are arranged at intervals and distributed in an array manner; s3, growing a gate oxide layer along the wall of the groove by adopting silicon thermal oxidation, then filling a gate material in the groove to form a gate by adopting chemical vapor deposition, wherein the top of the gate is lower than the opening of the groove, and then continuously growing the gate oxide layer on the gate to reach the opening of the groove; s4, forming connecting holes on partial grooves in the plurality of grooves by adopting second etching, wherein the connecting holes are in contact with the grid electrodes in the grooves and are distributed in an array; and S5, depositing a top electrode material in the connecting hole and on the first conductive type drift region and the groove by adopting magnetron sputtering to form a top electrode.
In some embodiments, the bottom electrode is a drain and the top electrode is a source; or, the bottom electrode is a collector electrode, and the top electrode is an emitter electrode.
In some embodiments, the first conductivity type is N-type or P-type.
In some embodiments, in step S2, the first etching manner is reactive ion etching; and/or in step S4, the second etching mode is plasma etching.
In some embodiments, after step S3 and before step S4, further comprising: s31, forming body regions of a second conduction type in the drift region of the first conduction type by adopting first ion implantation and matching with high-temperature propulsion, wherein the body regions are distributed around the groove and are lower than the opening of the groove; and S32, forming a first conductive type source region in the first conductive type drift region by adopting second ion implantation and matching with high-temperature propulsion, wherein the first conductive type source region is distributed around the groove and on the second conductive type body region, and the top of the first conductive type source region and the opening of the groove are positioned on the same horizontal plane.
In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.
In some embodiments, in step S31, the first ion implantation is a boron ion implantation; and/or in step S32, the second ion implantation is arsenic ion implantation.
In some embodiments, the groove is a U-shaped groove; and/or the grooves with the connecting holes and the grooves without the connecting holes are alternately arranged along the horizontal direction.
In some embodiments, the distance between the center lines of two adjacent trenches is defined as a cell size, and in step S2, the ratio between the width of the trench and the cell size is 0.5-0.7.
In some embodiments, the gate material is polysilicon; and/or the gate oxide layer material is silicon dioxide.
According to the preparation method of the semiconductor device, the first conduction type drift region formed on the first conduction type semiconductor substrate is etched to form the grooves arranged in the array mode, the connecting holes arranged in the array mode are further etched on the partial grooves in the grooves, the formed grooves with the connecting holes can greatly reduce the distance between the grooves, the number of unit cells in the unit area of a chip is greatly increased, and therefore the semiconductor device has the beneficial effects that: (1) along with the increase of the number of the cells in the unit area of the chip, the current path is increased, so that the through-current capacity of the unit area of the chip is improved; (2) the enhancement of the current capacity can greatly improve the extreme impact (short-time large current and high voltage) resistance of the chip; (3) the trenches provided with the connecting holes are connected with the top electrode through the connecting holes, one type of carrier (such as holes) channels can be formed when the trenches are opened, and in order to maintain electric neutrality, the other type of opposite carrier (such as electrons) is induced in the grid trenches, so that the electron concentration is increased when the channels are conducted, the channel resistance is reduced, and the integral on-resistance Rds (on) of the semiconductor device is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a UDMOS in the prior art;
fig. 2 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application;
fig. 3 is a schematic cross-sectional structure view of the semiconductor substrate of the first conductivity type obtained after the processing of steps S1 and S2 shown in fig. 2;
fig. 4 is a schematic cross-sectional structure view of the semiconductor substrate of the first conductivity type obtained after the processing of steps S1 to S3 shown in fig. 2;
fig. 5 is a schematic cross-sectional structure view of the semiconductor substrate of the first conductivity type obtained after the processing of steps S1 to S4 shown in fig. 2;
fig. 6 is a schematic cross-sectional structure of a semiconductor device fabricated by the fabrication method shown in fig. 2;
fig. 7 is a flowchart of another method of manufacturing a semiconductor device according to an embodiment of the present application;
fig. 8 is a schematic cross-sectional structure view of the semiconductor substrate of the first conductivity type shown in fig. 4 after the semiconductor substrate of the first conductivity type is processed through steps S31 and S32.
Fig. 9 is a schematic cross-sectional structure of a semiconductor device fabricated by the fabrication method shown in fig. 7.
Each reference numeral represents: 1. a bottom electrode; 2. a semiconductor substrate of a first conductivity type; 3. a first conductivity type drift region; 4. a trench; 5. a gate oxide layer; 6. a gate electrode; 7. connecting holes; 8. a top electrode; 9. a body region of a second conductivity type; 10. a source region of a first conductivity type; 21. one side; 22. the other side; 41. a groove formed with a connection hole; 42. a trench of the connection hole is not formed.
Detailed Description
The technical solutions in the embodiments of the present application are described below with reference to the accompanying drawings, and the embodiments and technical features thereof described below may be combined with each other without conflict.
Referring to fig. 2, an embodiment of the present application provides a method for manufacturing a semiconductor device, which includes the following steps S1-S5.
Referring to fig. 3 to 6, S1, a semiconductor substrate 2 of a first conductivity type having a bottom electrode 1 on one surface 21 is provided, and a drift region 3 of the first conductivity type is formed on another surface 22 of the semiconductor substrate 2 opposite to the one surface 21. Alternatively, the bottom electrode 1 may be a metal electrode or a non-metal electrode. The semiconductor substrate 2 may be a silicon-based semiconductor substrate, and by way of example only, the semiconductor substrate 2 may be a silicon wafer. It is to be understood that the first conductive-type drift region 3 is formed by a process known in the art, such as chemical vapor deposition, epitaxial growth, etc.
And S2, forming a plurality of grooves 4 in the first conductive type drift region 3 by adopting first etching, wherein the grooves 4 are arranged at intervals and distributed in an array manner. The cross-sectional structure of the semiconductor substrate 2 of the first conductivity type after being processed through steps S1, S2 shown in fig. 2 is shown in fig. 3. Alternatively, the first etching manner may be, but is not limited to, Reactive Ion Etching (RIE).
S3, growing a gate oxide layer 5 along the walls of the trench 4 by thermal oxidation of silicon, then filling a gate material in the trench 4 by Chemical Vapor Deposition (CVD) to form a gate 6, where the top of the gate 6 is lower than the opening of the trench 4, and then continuing to grow the gate oxide layer 5 on the gate 4 to reach the opening of the trench 4; the cross-sectional structure of the semiconductor substrate 2 of the first conductivity type after being processed through steps S1 to S3 shown in fig. 2 is shown in fig. 4. Alternatively, the gate electrode 6 may have a stripe structure or a column structure, for example, the column structure may be a quadrangular prism, a cylinder, or the like. Alternatively, the gate material may be polysilicon (polycrystalline silicon); the gate oxide layer material may be silicon dioxide (SiO)2). Optionally, the thermal oxidation of silicon is dry oxygen oxidation. The gas atmosphere of the silicon thermal oxidation is O2HCl and N2The temperature of the silicon thermal oxidation is 900-2000 ℃ and the time of the silicon thermal oxidation is 10-500 minutes (min).
And S4, forming connecting holes 7 on part of the grooves 41 in the plurality of grooves 4 by adopting second etching, wherein the connecting holes 7 are in contact with the grid electrodes 6 in the grooves 41, and the connecting holes 7 are distributed in an array. The cross-sectional structure of the semiconductor substrate 2 of the first conductivity type after being processed through steps S1 to S4 shown in fig. 2 is shown in fig. 5. Alternatively, the second etching manner may be, but is not limited to, Plasma etching (Plasma etching). In some embodiments, the connection hole 7 may have an inverted trapezoidal structure, and a length of a lower bottom of the connection hole 7 is greater than a width of the groove 4. The lower bottom means a bottom of the connection hole 7 contacting the groove 41 formed with the connection hole 7.
And S5, depositing a top electrode material in the connecting hole 7 and on the first conductive type drift region 3 and the groove 42 by adopting magnetron sputtering to form a top electrode 8. The cross-sectional structure of the semiconductor device fabricated through steps S1 to S5 shown in fig. 2 is shown in fig. 6. Alternatively, the top electrode material may be a conductive metal, which may be, for example only, aluminum (Al), copper (Cu), aluminum-copper alloy, or the like.
In this embodiment, a plurality of trenches arranged in an array are etched in a first conductive type drift region formed on a semiconductor substrate of a first conductive type, and connecting holes arranged in an array are further etched in a part of the trenches in the plurality of trenches, so that the distance between the trenches and the trenches can be greatly reduced by forming the trenches with the connecting holes, and the number of cells in a unit area of a chip is greatly increased, and thus, the semiconductor chip has the following beneficial effects: (1) along with the increase of the number of the cells in the unit area of the chip, the current path is increased, so that the through-current capacity of the unit area of the chip is improved; (2) the enhancement of the current capacity can greatly improve the extreme impact (short-time large current and high voltage) resistance of the chip; (3) the trenches provided with the connecting holes are connected with the top electrode through the connecting holes, one type of carrier (such as holes) channels can be formed when the trenches are opened, and in order to maintain electric neutrality, the other type of opposite carrier (such as electrons) is induced in the grid trenches, so that the electron concentration is increased when the channels are conducted, the channel resistance is reduced, and the integral on-resistance Rds (on) of the semiconductor device is reduced.
In some embodiments, the semiconductor device may be a power MOSFET, in which case the bottom electrode 1 is the drain and the top electrode 8 is the source. In other embodiments, the semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor), in which case the bottom electrode 1 is a collector and the top electrode 8 is an emitter.
In some embodiments, the first conductivity type is N-type or P-type.
In some embodiments, the groove 4 is a U-shaped groove. Set up slot 4 into U type groove, for V type groove or bar groove, can prevent 4 bottoms of slot electric leakages to prevent that the device from becoming invalid, be favorable to prolonging the life of device.
In other embodiments, the grooves 41 in which the connection holes 7 are formed and the grooves 42 in which the connection holes 7 are not formed (i.e., the grooves in which the connection holes are not provided) are alternately arranged in the horizontal direction.
Referring to fig. 3 to 6, 8 and 9, in some embodiments, the distance a between the center lines of two adjacent trenches 4 is defined as a cell size, and in step S2, the ratio between the width b of the trench 4 and the cell size a is 0.5-0.7. That is, b/a is 0.5 to 0.7. Further, the cell size a is equal to the sum of the distance c between two adjacent trenches 4 and the width b of the trench 4, i.e., a ═ b + c. Within the above-mentioned condition range, the top electrode trench 41 of the prepared semiconductor device (the structure is shown in fig. 6 and 9) connected to the top electrode 8 forms a channel of one kind of carriers (for example, holes) when being opened, and in order to maintain electrical neutrality between the trenches 4, another kind of carriers (for example, electrons) are induced in the gate trench 42, so that the electron concentration when the channel is conducted is increased, thereby reducing the channel resistance and reducing the overall on-resistance (rds (on)) of the semiconductor device. Alternatively, b/a may be 0.5, and c-a-b, that is, the distance between two adjacent trenches 4 is equal to the width of the trench 4; under such conditions, the rds (on) of the entire semiconductor device can be reduced more sufficiently.
Referring to fig. 7, a method for manufacturing a semiconductor device according to another embodiment of the present disclosure, after step S3 and before step S4, may further include: s31, forming body regions 9 of a second conductivity type in the drift region 3 of the first conductivity type by using first ion implantation and matching with high temperature propulsion, the body regions being distributed around the trench 4 and lower than the opening of the trench 4; and S32, forming a first conductive type source region 10 in the first conductive type drift region 3 by adopting second ion implantation and matching with high-temperature propulsion, wherein the first conductive type source region 10 is distributed around the trench 4 and on the second conductive type body region 9, and the top of the first conductive type source region 10 and the opening of the trench 4 are positioned on the same horizontal plane. The cross-sectional structure of the semiconductor substrate of the first conductivity type obtained after the processing in steps S1 to S3, S31, S32 is shown in fig. 8. The cross-sectional structure of the semiconductor device fabricated by subjecting the semiconductor substrate of the first conductivity type shown in fig. 8 to the processes of steps S4 and S5 is shown in fig. 9.
Further, in some embodiments, the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.
Further, in some embodiments, in step S31, the first ion implantation is a Boron (Boron, B) ion implantation. In step S32, the second ion implantation is arsenic (As) ion implantation.
Further, in some embodiments, the temperature of the high temperature ramp is 900-. Optionally, the high temperature propelled gas atmosphere is N2。
The application also provides a semiconductor device which is prepared by adopting the preparation method. Referring to fig. 6 and 9, in a cross section of the semiconductor device, the semiconductor device includes: a semiconductor substrate 2 of a first conductivity type, said semiconductor substrate 2 having a first main surface 21 and a second main surface 22 arranged oppositely; a bottom electrode 1 provided on the first main surface 21; the first conductive type drift region 3 is arranged on the second main surface 22 and comprises a plurality of grooves 4, the grooves 4 are arranged at intervals and distributed in an array manner, grid electrodes 6 are arranged in the grooves 4, a grid oxide layer 5 is filled between the grid electrodes 6 and the groove walls of the grooves 4, the tops of the grid electrodes 6 are lower than openings of the grooves 4, and the grid electrodes 6 are covered with the grid oxide layer 6; connecting holes 7 are formed in part of the grooves 41 in the plurality of grooves 4 from the opening end to the bottom, the connecting holes 7 are in contact with the grid electrodes 6 in the grooves, and the connecting holes 7 are distributed in an array; and a top electrode 8 disposed on the first conductive type drift region 3 and the trench 4, filling the connection hole 7, and connected to the gate electrode 6 through the connection hole 7.
In some embodiments, the connection hole 7 is formed by etching downward from an open end of the partial trench (i.e., the trench in which the connection hole is formed) 41, is located in the first conductivity type drift region 3, is located on the partial trench 41, and is in contact with the partial trench 41.
Although the application has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. This application is intended to embrace all such modifications and variations and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.
In addition, in the description of the present application, it is to be understood that the terms "center", "length", "width", "upper", "lower", "horizontal", "top", "bottom", "inner", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. In addition, structural elements having the same or similar characteristics may be identified by the same or different reference numerals. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising the steps of:
s1, providing a semiconductor substrate of a first conductivity type having a bottom electrode on one surface, and forming a drift region of the first conductivity type on the other surface of the semiconductor substrate disposed opposite to the one surface;
s2, forming a plurality of grooves in the first conductive type drift region by adopting first etching, wherein the grooves are arranged at intervals and distributed in an array manner;
s3, growing a gate oxide layer along the wall of the groove by adopting silicon thermal oxidation, then filling a gate material in the groove to form a gate by adopting chemical vapor deposition, wherein the top of the gate is lower than the opening of the groove, and then continuously growing the gate oxide layer on the gate to reach the opening of the groove;
s4, forming connecting holes on partial grooves in the plurality of grooves by adopting second etching, wherein the connecting holes are in contact with the grid electrodes in the grooves and are distributed in an array;
and S5, depositing a top electrode material in the connecting hole and on the first conductive type drift region and the groove by adopting magnetron sputtering to form a top electrode.
2. The method according to claim 1, wherein the bottom electrode is a drain electrode, and the top electrode is a source electrode; alternatively, the first and second electrodes may be,
the bottom electrode is a collector electrode, and the top electrode is an emitter electrode.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is an N-type or a P-type.
4. The method for manufacturing a semiconductor device according to claim 1, wherein in step S2, the first etching mode is reactive ion etching; and/or the presence of a gas in the gas,
in step S4, the second etching mode is plasma etching.
5. The method for manufacturing a semiconductor device according to claim 1, further comprising, after step S3 and before step S4:
s31, forming body regions of a second conduction type in the drift region of the first conduction type by adopting first ion implantation and matching with high-temperature propulsion, wherein the body regions are distributed around the groove and are lower than the opening of the groove;
and S32, forming a first conductive type source region in the first conductive type drift region by adopting second ion implantation and matching with high-temperature propulsion, wherein the first conductive type source region is distributed around the groove and on the second conductive type body region, and the top of the first conductive type source region and the opening of the groove are positioned on the same horizontal plane.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the first conductivity type is an N-type, and the second conductivity type is a P-type; alternatively, the first and second electrodes may be,
the first conductive type is a P type, and the second conductive type is an N type.
7. The method for manufacturing a semiconductor device according to claim 5, wherein in step S31, the first ion implantation is boron ion implantation; and/or the presence of a gas in the gas,
in step S32, the second ion implantation is arsenic ion implantation.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the trench is a U-shaped trench; and/or the presence of a gas in the gas,
the trenches in which the connection holes are formed and the trenches in which the connection holes are not formed are alternately arranged in a horizontal direction.
9. The method of manufacturing a semiconductor device according to claim 8, wherein a distance between center lines of two adjacent trenches is defined as a cell size, and a ratio between a width of the trench and the cell size in step S2 is 0.5 to 0.7.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the gate material is polysilicon; and/or the presence of a gas in the gas,
the gate oxide layer is made of silicon dioxide.
CN202110537232.0A 2021-05-14 2021-05-14 Method for manufacturing semiconductor device Pending CN113327854A (en)

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Citations (4)

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CN102201437A (en) * 2010-03-25 2011-09-28 力士科技股份有限公司 Trench insulated gate bipolar transistor and manufacturing method thereof
US20110254088A1 (en) * 2010-04-20 2011-10-20 Maxpower Semiconductor Inc. Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication
US20140042535A1 (en) * 2012-02-13 2014-02-13 Maxpower Semiconductor, Inc. Trench transistors and methods with low-voltage-drop shunt to body diode
US20140084362A1 (en) * 2012-09-26 2014-03-27 Infineon Technologies Ag Semiconductor Device and Method for Manufacturing a Semiconductor Device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102201437A (en) * 2010-03-25 2011-09-28 力士科技股份有限公司 Trench insulated gate bipolar transistor and manufacturing method thereof
US20110254088A1 (en) * 2010-04-20 2011-10-20 Maxpower Semiconductor Inc. Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication
US20140042535A1 (en) * 2012-02-13 2014-02-13 Maxpower Semiconductor, Inc. Trench transistors and methods with low-voltage-drop shunt to body diode
US20140084362A1 (en) * 2012-09-26 2014-03-27 Infineon Technologies Ag Semiconductor Device and Method for Manufacturing a Semiconductor Device

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Application publication date: 20210831