CN113326212A

CN113326212A - Data processing method and device and related equipment

Info

Publication number: CN113326212A
Application number: CN202110210210.3A
Authority: CN
Inventors: 徐达人; 石亚飞
Original assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Current assignee: Calterah Semiconductor Technology Shanghai Co Ltd
Priority date: 2020-02-28
Filing date: 2021-02-25
Publication date: 2021-08-31
Anticipated expiration: 2041-02-25
Also published as: CN113326212B

Abstract

The application discloses a data processing method, a data processing device and related equipment, wherein the data processing method comprises the following steps: determining the type of a target detection window; when the type of the target detection window is characterized as a first type of detection window, reading first target data from a target storage device on a chip according to an addressing mode corresponding to the first type of detection window; when the type of the target detection window is characterized as a second type of detection window, reading second target data from a target storage device according to an addressing mode corresponding to the second type of detection window; the target storage device comprises a plurality of target storage units, the number and the size of the target storage units are not lower than the window width size of a first type of detection window and a second type of detection window, and the first type of detection window is different from the second type of detection window. Therefore, the same target storage device can be applied to different application scenes corresponding to different detection window types, and the flexibility of constant false alarm detection can be effectively improved.

Description

Data processing method and device and related equipment

The present application claims priority from the chinese patent application entitled "a data processing method, apparatus, and device" filed by the chinese patent office at 28.02/2020, application number 202010131628.0, the entire contents of which are incorporated herein by reference.

Technical Field

The present application relates to the field of target detection technologies, and in particular, to a data processing method, apparatus, and related device.

Background

When the interference intensity of an external signal changes in the process of detecting a target, the sensor can automatically adjust the sensitivity of the sensor, so that the false alarm probability (namely the probability that the target does not exist actually but is judged to exist) is kept unchanged, and the characteristic is called as a constant false alarm rate characteristic. The probability of correctly detecting the target may be maximized while maintaining a constant false alarm probability.

At present, for a digital signal processing module in a sensor, due to the limitation that only a single type of constant false alarm rate detection window and other factors can be adopted, the digital signal processing module can only be specified and developed for a certain specific application scene, so that the sensor can only be applicable to the scene generally, but cannot be applicable to other scenes, and the flexibility is poor.

Disclosure of Invention

The embodiment of the application provides a data processing method, a data processing device and data processing equipment, so that a hardware acceleration chip can be suitable for more scenes, and the flexibility of the hardware acceleration chip is improved.

In a first aspect, an embodiment of the present application provides a data processing method, where the method includes: determining the type of a target detection window; when the type of the target detection window is characterized as a first type of detection window, reading first target data from a target storage device on a chip according to an addressing mode corresponding to the first type of detection window; when the type of the target detection window is characterized as a second type of detection window, reading second target data from the target storage device according to an addressing mode corresponding to the second type of detection window; the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width size of the first type of detection window and the second type of detection window, and the first type of detection window is different from the second type of detection window.

In this embodiment, on one hand, according to configuration operations of a user, the hardware acceleration chip can adopt different types of detection windows to perform data addressing, so that the hardware acceleration chip can be suitable for different application scenarios corresponding to different detection window types, and the flexibility of the hardware acceleration chip is improved; moreover, when the hardware acceleration chip adopts different types of detection windows for addressing, data can be read from the same target storage device, namely the different types of detection windows can multiplex the same data path, so that the hardware complexity is not increased.

In some possible embodiments, the first type of detection window is a square window, the first target data includes at least first square window data of a first node and second square window data of a second node, and the first node is adjacent to the second node; the reading of the first target data from the plurality of target storage units on the chip according to the addressing mode corresponding to the detection window of the first type includes: reading the first square window data from the target storage units on the chip according to the addressing mode corresponding to the square window; reading first data corresponding to the second node from the target storage units, wherein the first data is data which is not overlapped with the first square window data in the second square window data, and the second square window data further comprises data which is overlapped with the first square window data. In this embodiment, repeated reading of data overlapping the first square window data and the second square window data is not required, and thus the amount of data to be read can be reduced, thereby reducing consumption of hardware resources and improving the efficiency of data processing.

In some possible embodiments, the method further comprises: adding third raw data of a third node in the external storage device to the target storage device, the third node not being adjacent to the second node. In this embodiment, while the square window data is read, the original data of the next node in the external storage device can be added to the target storage device at the same time, and the original data of the next node is read from the external storage device without waiting for the square window to be read, so that the data processing efficiency can be improved.

In some possible embodiments, the second type of detection window is a cross window, and the second target data includes at least first cross window data of a first node and second cross window data of a second node, the first node being adjacent to the second node; the reading second target data from the plurality of target storage units on the slice according to the addressing mode corresponding to the detection window of the second type includes: reading the first cross window data from a plurality of target storage units on the chip according to an addressing mode corresponding to a cross window; and reading second data corresponding to the second node from the plurality of target storage units, wherein the second data is different from the first cross window data in the second cross window data, and the second cross window data also comprises data which is the same as the first cross window data. In this embodiment, repeated reading of data overlapping the first cross window data and the second cross window data is not required, and thus the amount of data to be read can be reduced, thereby reducing consumption of hardware resources and improving the efficiency of data processing.

In some possible embodiments, the method further comprises: adding original data of a third node in an external storage device to the target storage device, the third node not being adjacent to the second node. In this embodiment, while reading the cross window data, the original data of the next node in the external storage device may be added to the target storage device at the same time, and it is not necessary to read the original data of the next node from the external storage device after the cross window is read, so that the data processing efficiency may be improved.

In some possible embodiments, the method further comprises: when the target detection window type is characterized by other types of detection windows (namely the number of the target detection window types is at least three types), reading third target data from the target storage device according to the addressing mode corresponding to each other type of detection window; the number of the target storage units in the target storage device is not less than the window width of the other types of detection windows, and the other types of detection windows are different from the first type of detection windows and the second type of detection windows. In this embodiment, the same hardware resource may also support a third type of detection window to implement target detection, so that the universality of implementation of the scheme may be further improved.

In some possible embodiments, the method further comprises: and denoising the first target data and/or the second target data to obtain fourth target data, wherein the data volume of the fourth target data is smaller than that of the first target data or that of the second target data. In this embodiment, by performing the data drying process in advance, the influence of the noise data on the target detection result can be reduced, and the detection accuracy can be improved.

In a second aspect, an embodiment of the present application further provides a data processing apparatus, where the apparatus includes a determining module, configured to determine a type of a target detection window; the first reading module is used for reading first target data from a target storage device on a chip according to an addressing mode corresponding to the detection window of the first type when the type of the target detection window is characterized as the detection window of the first type; the second reading module is used for reading second target data from the target storage device according to an addressing mode corresponding to the detection window of the second type when the type of the target detection window is characterized as the detection window of the second type; the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width size of the first type of detection window and the second type of detection window, and the first type of detection window is different from the second type of detection window.

In some possible embodiments, the apparatus further comprises: a third reading module, configured to, when the type of the target detection window is characterized by other types of detection windows, read third target data from the target storage device according to addressing manners corresponding to the other types of detection windows; the number of the target storage units in the target storage device is not less than the window width of the other types of detection windows, and the other types of detection windows are different from the first type of detection windows and the second type of detection windows.

In some possible embodiments, the first type of detection window is a square window, the first target data includes at least first square window data of a first node and second square window data of a second node, and the first node is adjacent to the second node; the first reading module includes: a first reading unit configured to read the first square window data from a plurality of target storage units on the slice in an addressing manner corresponding to the square window; a second reading unit, configured to read first data corresponding to the second node from the multiple target storage units, where the first data is data that does not overlap with the first square window data in the second square window data, and the second square window data further includes data that overlaps with the first square window data.

In some possible embodiments, the apparatus further comprises: a first adding module, configured to add original data of a third node in an external storage device to the target storage device, where the third node is not adjacent to the second node.

In some possible embodiments, the second type of detection window is a cross window, and the second target data includes at least first cross window data of a first node and second cross window data of a second node, the first node being adjacent to the second node; the second reading module includes: a third reading unit, configured to read the first cross window data from the multiple target storage units on the slice according to an addressing manner corresponding to a cross window; a fourth reading unit, configured to read second data corresponding to the second node from the multiple target storage units, where the second data is data of the second cross window that is different from the first cross window data, and the second cross window data further includes data that is the same as the first cross window data.

In some possible embodiments, the apparatus further comprises: a second adding module, configured to add third original data of a third node in an external storage device to the target storage device, where the original data is data of a third thirty-word window of the third node that is different from the second twenty-word window of the third node, and the third node is not adjacent to the second node.

In some possible embodiments, the apparatus further comprises: and the denoising module is used for denoising the first target data and/or the second target data to obtain fourth target data, wherein the data volume of the fourth target data is smaller than that of the first target data or that of the second target data.

The data processing apparatus described in the second aspect corresponds to the data processing method described in the first aspect, and therefore, the technical effect of any implementation manner in the second aspect can be referred to the technical effect description of the implementation manner in the first aspect, and details thereof are not repeated.

In a third aspect, an embodiment of the present application further provides a computer device, where the device includes a processor and a memory: the memory is used for storing program codes and transmitting the program codes to the processor; the processor is configured to perform the data processing method according to any one of the above first aspect according to instructions in the program code.

In a fourth aspect, an embodiment of the present application further provides a constant false alarm detection apparatus, including: the first storage module is used for storing data to be detected; the determining module is used for determining a detection window of a currently required use type; the buffer is used for buffering part of the data to be detected based on the detection window of the current required use type; and the detection module is used for carrying out constant false alarm detection on the data to be detected cached by the cache based on the detection window of the current required use type.

In this embodiment, the constant false alarm detection apparatus may cache data and perform constant false alarm detection using the detection window of the determined type, so that the constant false alarm detection apparatus may be applicable to different application scenarios corresponding to different detection window types, thereby improving the flexibility of the constant false alarm detection apparatus; moreover, different types of detection windows can multiplex the same data path, so that the complexity of hardware is not increased.

In one possible embodiment, the constant false alarm apparatus further comprises: the second storage module stores at least two types of detection windows; wherein the determining module is configured to select one of the at least two types of detection windows as the detection window of the currently required usage type based on the received instruction or the scene parameter. In this embodiment, the second storage module may store multiple types of detection windows, so that the constant false alarm device may support application scenarios corresponding to the multiple different types of detection windows.

In one possible embodiment, the at least two types of detection windows include at least two of a cross-shaped detection window, a square-shaped detection window, a rectangular-shaped detection window, a triangular-shaped detection window, and a trapezoidal-shaped detection window. Thus, the constant false alarm device can be suitable for more application scenes.

In a possible implementation manner, the data to be detected is a two-dimensional matrix data structure; when the constant false alarm detection is performed on any test node in the two-dimensional matrix data structure, the buffer is used for caching all data covered by the detection window of the current required use type. Therefore, the constant false alarm device can cache and detect the data corresponding to the detection window meeting the specific type each time.

In a possible implementation manner, the buffer includes a plurality of storage units, and a first dimension direction in the two-dimensional matrix data structure is defined as a row direction, and a second dimension direction is defined as a column direction; when all data covered by the detection window of the currently required use type is cached in the cache, the same column of data in the two-dimensional matrix data structure is stored in the same storage unit, and each storage unit can only store one column of data in the two-dimensional matrix data structure. In this embodiment, the buffering of the data corresponding to the detection window is implemented using a plurality of storage units.

In one possible embodiment, the first dimension is a range dimension and the second dimension is a doppler dimension; or the first dimension is a doppler dimension and the second dimension is a range dimension.

In a possible implementation manner, a manner of sharing partial data is adopted to perform constant false alarm detection on two adjacent test nodes in the two-dimensional matrix data structure respectively. Therefore, the overlapping part between the window data corresponding to the two adjacent test nodes can be read without repetition, so that the read data volume can be reduced, the consumption of hardware resources can be reduced, and the data processing efficiency is improved.

In a possible embodiment, the buffer and the first storage module are located in different physical storage means independent from each other; and/or the first storage module and the second storage module are located in the same physical storage means.

In a possible implementation, the constant false alarm detection device is an integrated circuit, and the detection module is a CPU or a DSP in the integrated circuit.

In one possible embodiment, the integrated circuit is a chip structure; wherein, the buffer is a static random access memory.

In one possible implementation, the integrated circuit is a millimeter wave radar chip.

In a fifth aspect, embodiments of the present application further provide a radio device, including: a carrier; the device according to any of the above fourth aspects, disposed on a carrier; an antenna disposed on the carrier or on the carrier with an AiP structure integral with the device; the device is connected with the antenna and used for transmitting and receiving radio signals by the antenna.

In a sixth aspect, an embodiment of the present application further provides an apparatus, including: an apparatus body; and a radio device as described in the fifth aspect as set forth above provided on the apparatus body; wherein the radio device is used for object detection and/or communication.

In the foregoing implementation manner of the embodiment of the present application, after a user completes configuration operation on a detection window type on a user interface, a target detection window type corresponding to the configuration operation may be determined in response to the configuration operation; when the target detection window type is determined to be characterized as a first type of detection window, reading first target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the first type of detection window, and when the target detection window type is determined to be characterized as a second type of detection window, reading second target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the second type of detection window; the number of the target storage devices is not less than the window width of the first type of detection window and the second type of detection window, and the first type of detection window is different from the second type of detection window. Therefore, on one hand, according to configuration operation of a user, the hardware acceleration chip can adopt different types of detection windows to carry out data addressing, so that the hardware acceleration chip can be suitable for different application scenes corresponding to different detection window types, and the flexibility of the hardware acceleration chip is improved; moreover, when the hardware acceleration chip adopts different types of detection windows for addressing, data can be read from the same target storage device, namely the different types of detection windows can multiplex the same data path, so that the hardware complexity is not increased.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a schematic flow chart illustrating a data processing method according to an embodiment of the present application;

FIG. 2 is a schematic diagram of square window data and addressing modes of a first node and a second node;

FIG. 3 is a schematic diagram of cross window data and addressing of a first node and a second node;

FIG. 4 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a constant false alarm device according to an embodiment of the present application;

fig. 6 is a schematic hardware structure diagram of an apparatus in an embodiment of the present application.

Detailed Description

In the following, taking a radar as an example, how to perform constant false alarm detection in the process of performing target detection by a sensor is described in detail; it should be noted that the technical contents set forth in the embodiments of the present application can also be applied to other types of sensors.

At present, a radar digital signal processing module on a hardware acceleration chip is generally subjected to specification formulation and development based on a certain specific application scene, and a specific type of target detection window is adopted for the application scene, so that the developed hardware acceleration chip is often only suitable for the scene, but not flexibly suitable for various scenes.

Based on this, the embodiment of the application provides a data processing method, so that the hardware acceleration chip can be applied to various application scenarios, and the flexibility of the hardware acceleration chip is improved. Specifically, after a user (such as a technician) completes configuration operation on a detection window type on a user interface, a target detection window type corresponding to the configuration operation may be determined in response to the configuration operation; meanwhile, the radar can automatically determine a target detection window of a type adapted to the current application scene according to the current environment information. When the target detection window type is determined to be characterized as a first type of detection window, reading first target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the first type of detection window, and when the target detection window type is determined to be characterized as a second type of detection window, reading second target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the second type of detection window; the number of the target storage devices is not less than the window width of the first type of detection window and the second type of detection window, and the first type of detection window is different from the second type of detection window. Therefore, on one hand, according to configuration operation of a user, the hardware acceleration chip can adopt different types of detection windows to carry out data addressing, so that the hardware acceleration chip can be suitable for different application scenes corresponding to different detection window types, and the flexibility of the hardware acceleration chip is improved; moreover, when the hardware acceleration chip adopts different types of detection windows for addressing, data can be read from the same target storage device on the chip, namely the different types of detection windows can multiplex the same data path, so that the hardware complexity is not increased.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, various non-limiting embodiments accompanying the present application examples are described below with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, fig. 1 shows a schematic flow chart of a data processing method in an embodiment of the present application, where the method may specifically include:

s101: and determining the type of the target detection window.

In some embodiments of practical applications, a configuration interface for window type selection may be presented to a user (e.g., a technician, etc.), so that the user may select a detection window type to be used on the configuration interface, and specifically, may perform a corresponding configuration operation. For example, the user may configure the usage time (which may be a period of time in the future, etc.) of a specific type of detection window, the width size of the detection window, etc. on the configuration interface. Of course, the user may also complete the configuration of the detection window type by developing a corresponding configuration file.

Meanwhile, the sensor (such as radar) can also automatically judge and/or select the type of the detection window adaptive to the current application scene based on the collected or received information parameters.

As some examples, the detection Window types in the present embodiment may include a Square Window (SW), a Cross Window (CW), a Rectangular Window (RW), a triangular Window (Triangle Window), a trapezoidal Window (Trapezoid Window), and the like. A user or a sensor may select one of the detection window types to perform a corresponding configuration operation according to an application scenario in which an actual application is located, so as to determine a detection window type (hereinafter, referred to as a target detection window type for convenience of description) used by the radar system for target detection. In practical applications, the detection window may specifically refer to a detection window configured for a Constant False-Alarm Rate (CRAR) module in the digital signal processing module.

S102: and when the type of the target detection window is characterized as a first type of detection window, reading first target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the first type of detection window.

S103: when the type of the target detection window is characterized as a second type of detection window, reading second target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the second type of detection window, wherein the number of the storage units of the target storage device is not less than the window width of the first type of detection window and the window width of the second type of detection window, and the first type of detection window is different from the second type of detection window. For example, the number of storage units of the target storage device is equal to or greater than the target number of detection windows, and the target storage device can support the same target number of detection windows in different target value ranges.

In this embodiment, when the radar system performs target detection, a transmitting end (transmitting antenna) in the radar system may be used to transmit a signal, and after the signal is reflected by an object located in a detectable region of the radar system, a receiving end (receiving antenna) in the radar system receives a reflected signal (e.g., an echo signal), and performs corresponding processing on the reflected signal, such as performing fast fourier transform processing on a distance dimension or fast fourier transform processing on a speed dimension, to obtain original data that needs to be processed with a constant false alarm rate.

The original data can be stored in an external memory in advance, and when the original data needs to be processed correspondingly, the original data can be written into a plurality of target storage units on a hardware acceleration chip by the external memory, and the original data on the target data storage device is processed by adopting a corresponding detection window. It should be noted that the external memory is located outside the data signal processing module with respect to the target storage device in the data signal processing module, but is still configured in the hardware acceleration chip or module. As an example, the external Memory may be a Static Random-Access Memory (SRAM) located in a hardware acceleration chip or module.

In an exemplary embodiment, the hardware acceleration chip may be configured by software, so that the hardware acceleration chip may read data from the plurality of on-chip memories according to addressing manners corresponding to at least two different detection window types, and thus the hardware acceleration chip may support data reading and target detection for the at least two detection window types. Taking a hardware acceleration chip supporting different types of first-type detection windows and second-type detection windows (for example, a square window and a cross window, respectively), when a target detection window type determined based on a user configuration operation is specifically the first-type detection window, first target data may be read from a plurality of target storage units on a chip according to an addressing manner corresponding to the first-type detection window, and when the target detection window type is specifically the second-type detection window, second target data may be read from a plurality of target storage units on the chip according to an addressing manner corresponding to the second-type detection window. When the types of the two detection windows are different, the addressing modes corresponding to the two detection windows respectively can also be different.

As an example, the detection window of the first type may specifically be a square window, and the detection window of the second type may specifically be a cross window. Thus, when the target detection window type is determined to be a square window, the square window data corresponding to two adjacent nodes (e.g., a target node, hereinafter referred to as a first node and a second node, respectively) can be sequentially read according to the addressing mode of the square window, that is, after the first square window data corresponding to the first node is read according to the addressing mode of the square window, the second square window data corresponding to the second node is read according to the same addressing mode. And when the target detection window is determined to be the cross window, sequentially reading first cross window data corresponding to the first node and second cross window data corresponding to the second node according to the addressing mode of the cross window. The first node is adjacent to the second node, and may be adjacent to the second node left and right, or adjacent to the second node up and down. It should be noted that, only two adjacent nodes are exemplified here, the number of nodes processed by the hardware acceleration chip in practical application may be more than 2, for example, 256, 512, and so on, and for square window data or cross window data corresponding to other nodes, the analogy may be described with reference to the above process.

For the convenience of understanding, the following description will be given by taking the square window data corresponding to the first node and the second node as an example. As shown in fig. 2, the left side of fig. 2 shows first square window data corresponding to a first node and second square window data corresponding to a second node (the second node is located at the right side of the first node), where the square window data corresponding to each node includes (N +1) × (N +1) data. It is assumed that the hardware acceleration chip includes N +1 on-chip memories (i.e. the above target storage devices are respectively an on-chip memory 0 to an on-chip memory N; in practical applications, the value of N may be an even number not equal to 0 based on the object of window design) for caching raw data of 1 to N +1 of a Range Gate (Range Gate), and the inside of each on-chip memory is continuously cached with raw data of a Doppler Gate (Doppler Gate) dimension, which can be written into the on-chip memory from an external memory in advance. When the first square window data of the first node is read, the data of the range gate dimension may be continuously read from the N +1 on-chip memories at the same time (or the N +1 on-chip memories may also be regarded as continuously sending data to the lower-level processing module at the same time), and when the original data of the N +1 th doppler gate dimension of the first node is read, the reading of the first square window data of the first node is completed. At this time, the writing of the second square window data of the second node stored in the external memory into the N +1 on-chip memories may be continued, and the data of the range gate dimension may be continuously read from the N +1 on-chip memories at the same time until the original data of the N +1 th doppler gate dimension of the second node is completed.

When the cross window data corresponding to the first node and the second node are read according to the addressing mode of the cross window, referring to fig. 3, the left side of fig. 3 shows the first cross window data corresponding to the first node and the second cross window data corresponding to the second node (the second node is located on the right side of the first node), and the width (including the original data) and the length of the cross window data corresponding to each node are both N + 1. Assuming that the hardware acceleration chip comprises N +1 on-chip memories (respectively from 0 to N), and data of an upper window part (High Wing), data of a Test point (DUT), and data of a lower window part (Low Wing) of a distance gate dimension are cached in three parts, original data of the doppler gate dimension are continuously cached in each on-chip memory, and the original data can be written into the on-chip memories from external memories in advance. When reading the first cross window data of the first node, the cache data of the on-chip memory can be addressed from three parts of the doppler gate dimension division, namely, a Left window part (Left Wind), a DUT, and a Right window part (Right Wind), according to the window characteristics of the cross window. Specifically, N/2 original data (Left Wind) can be continuously read in the doppler gate dimension, then k (k is a natural number, i.e., when k is equal to 0, the next original data can be directly read without the need of skipping the k, the value of k can be preset according to actual requirements, or can be adaptively adjusted according to the current application scenario) on-chip memory addresses to read data of one DUT, then k on-chip memory addresses are continuously skipped to read N/2 original data (Right Wind), and the reading of the first cross window data of the first node is completed. At this time, the writing of the second window data of the second node stored in the external memory into the N +1 on-chip memories may be continued, and the data of the range gate dimension may be continuously read from the N +1 on-chip memories at the same time by referring to the above process until the original data of the N +1 th doppler gate dimension of the second node is completed.

It can be understood that, in practical applications, since the first node and the second node are two adjacent nodes, this causes a partial data overlap between the square window data (or cross window data) corresponding to the first node and the square window data (or cross window data) corresponding to the second node. Therefore, in some possible embodiments, after the square window data (or the cross window data) corresponding to the first node is read, only the non-overlapping data in the external storage device may be written into the target storage units on the chip and the non-overlapping part of the data may be read out from the target storage units without repeatedly writing and reading the overlapping data into the target storage units on the chip. As an example, when the first type of detection window is specifically a square window, first square window data corresponding to a first node may be read from a plurality of target storage units on the chip in an addressing manner corresponding to the square window, and then, when reading second square window data corresponding to a second node, only first data corresponding to the second node, that is, data that does not overlap with the first square window data in the second square window data corresponding to the second node, may be read from the plurality of target storage units, and for data that overlaps with the first square window data in the second square window data, since the part of data is already read when reading the first square window data, it may not be read repeatedly, and the square window data corresponding to the second node is the first data and the overlapping data.

Similarly, when the first type of detection window is specifically a cross window, first cross window data corresponding to the first node may be read from a plurality of target storage units on the chip according to an addressing manner corresponding to the cross window, and then, when second cross window data corresponding to the second node is read, only second data corresponding to the second node may be read from the plurality of target storage units, where the second data is data that does not overlap with the first cross window data in the second cross window data corresponding to the second node, and for data that overlaps with the first cross window data in the second cross window data, since the part of data is already read when the first cross window data is read, it may not be necessary to repeat reading, and the cross window data corresponding to the second node is the second data and the overlapping data.

Still taking the above-mentioned reading of the first square window data of the first node and the second square window data of the second node as an example, the data of the range gate dimension may be continuously read from the N +1 on-chip memories at the same time according to the addressing mode of the square window until the reading of the original data of the N +1 doppler dimension is completed; then, because the raw data of the 2 nd to N +1 th doppler dimensions in the first square window data corresponding to the first node are overlapped with the raw data of the 1 st to N th doppler dimensions in the second square window data corresponding to the second node, as shown by the shaded portion in fig. 2, the raw data of the N +1 th doppler dimensions of the second node can be read from the corresponding target storage device, and the raw data of the 1 st to N th doppler dimensions in the second square window data has been read, and does not need to be read again, so that the reading of the second square window data can be completed.

Taking the above-mentioned reading of the first cross window data of the first node and the second cross window data of the second node shown in fig. 3 as an example, N/2 original data (i.e., Left window) may be sequentially and continuously read according to the addressing mode of the cross window, k (k is a natural number) on-chip memory addresses are skipped to read data of one DUT, and then k on-chip memory addresses are skipped to read N/2 original data (i.e., Right window) to complete the reading of the first cross window data of the first node. Then, because the raw data of the 2 nd to N/2 th doppler dimensions, (N/2+2K +2) to (N +2K +1) th doppler dimensions in the first cross-window data of the first node overlap with the raw data in the second cross-window data of the second node, only the raw data which does not overlap with the first cross-window data in the second cross-window data can be read, that is, the raw data of the N/2 th, the (N/2+ K +1) th and the (N +2K +1) th doppler dimensions in the data in the second cross-window can be read, and the raw data of the 1 st to (N/2-1) th and the (N/2+2K +1) to (N +2K +1) th doppler dimensions in the data in the second cross-window overlap with the raw data of the 2 nd to N/2 nd and the (N/2+2K +2) th to (N +2K +1) th doppler dimensions in the first cross-window data respectively, as shown by the shaded part in fig. 2, so that repeated reading is not needed, thereby reducing the consumption of hardware resources and improving the efficiency of data processing.

In practical applications, the number of the processed nodes is usually much more than 2, and therefore, after the square window data or the cross window data corresponding to the second node is read, the square window data or the cross window data corresponding to the next node (adjacent to the second node) can be read continuously. The cache space of the target storage device on the chip is usually small, and all the original data of all the nodes in the external storage device cannot be cached at one time, so that when the square window data or the cross window data corresponding to the first node/the second node is read, the original data corresponding to the third node in the external storage device can be written into the corresponding target storage device on the chip, the address space of the used target storage device is the address space corresponding to the read data, and when the square window data or the cross window data of other nodes are subsequently read, the read data cannot be read for use.

For example, it is assumed that the square window data of the first node and the second node are sequentially read from left to right, and the square window data corresponding to the first node includes original data of 9 nodes (i.e., 3 rows and 3 columns), and node 1, node 2, … …, and node 9 are numbered respectively, where the number of the first node is node 5, and the number of the second node is node 6, and after the square window data corresponding to the first node is read, when the square window data of node 6, node 7, and other nodes are subsequently read, the original data of the node 1 does not need to be read, and at this time, the original data of the node to be subsequently read (i.e., the third node) can be written into the storage area (address space) corresponding to the original data of node 1 in the target storage device from the external storage device. Similarly, after the square window data corresponding to the second node is read, when the square window data of other nodes such as the node 7 and the node 8 are subsequently read, the original data of the node 2 does not need to be read any more, and at this time, the original data of other nodes which need to be subsequently read can be written into the storage area corresponding to the original data of the node 2 in the target storage device from the external storage device.

In this way, when data corresponding to the first node/the second node is read, the original data of the new node can be written into the target storage device, so that when data corresponding to other nodes (corresponding to windows such as a square window or a cross window) is subsequently read, time is not wasted for waiting for writing the original data corresponding to the third node into the target storage device on the chip from the external storage device.

Based on this, in another possible embodiment, when the target detection window type is a square window or a cross window, the original data of the third node in the external storage device may be added to the target storage device. And the third node and the second node are not adjacent nodes.

It should be noted that, in this embodiment, a hardware acceleration chip is configured by software, so that the hardware acceleration chip can support two different types of detection windows to perform data reading as an example for illustration, and in practical application, three or more types of detection windows can be simultaneously supported to perform data reading. For example, when it is determined that the target detection window type is the other types of detection windows (that is, the target detection window types are at least three) based on the configuration operation of the user, the third target data may be read from the plurality of target storage units on the chip according to the addressing modes corresponding to the other types of detection windows, of course, the number of the target storage units is also not lower than the window width size of the other types of detection windows, and the other types of detection windows are different from the first type of detection windows and the second type of detection windows, for example, may be a triangular window or the like different from a square window and a cross window.

In another possible implementation manner, after data (such as square window data, cross window data, and the like) corresponding to the first node and/or the node is read, denoising processing may be performed on the read data, and fourth target data may be obtained after noise data is filtered out, so that a subsequent processing process is performed based on the fourth target data corresponding to each node, for example, target detection is performed according to the fourth target data corresponding to each node, and the like. In general, the data amount of the fourth target data obtained after filtering is smaller than the data amount of the first target data or the data amount of the second target data before filtering. The specific implementation process of the denoising process may be a denoising process performed by a preset algorithm through software or the like.

In this embodiment, in response to a configuration operation of a user for a detection window type, a target detection window type corresponding to the configuration operation is determined, or the type of the detection window is automatically determined based on received or acquired scene information; when the target detection window type is determined to be characterized as a first type of detection window, reading first target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the first type of detection window, and when the target detection window type is determined to be characterized as a second type of detection window, reading second target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the second type of detection window; wherein the number of the target storage devices is not less than the window width size of a first type of detection window and a second type of detection window, and the first type of detection window is different from the second type of detection window. Therefore, on one hand, according to configuration operation of a user, the hardware acceleration chip can adopt different types of detection windows for addressing, so that the hardware acceleration chip can be suitable for different application scenes corresponding to different detection window types, and the flexibility of the hardware acceleration chip is improved; moreover, when the hardware acceleration chip adopts different types of detection windows for addressing, data can be read from the same target storage device, namely the different types of detection windows can multiplex the same data path, so that the hardware complexity is not increased.

In addition, the embodiment of the application also provides a data processing device. Referring to fig. 4, fig. 4 is a schematic structural diagram illustrating a data processing apparatus in an embodiment of the present application, where the apparatus 400 may include:

a determining module 401, configured to determine a type of a target detection window;

a first reading module 402, configured to, when the type of the target detection window is characterized as a first type of detection window, read first target data from a target storage device on a chip according to an addressing manner corresponding to the first type of detection window;

a second reading module 403, configured to, when the type of the target detection window is characterized as a second type of detection window, read second target data from the target storage device according to an addressing manner corresponding to the second type of detection window;

the target storage device comprises a plurality of target storage units, the number and the size of the plurality of target storage units are not lower than the window width size of the first type of detection window and the second type of detection window, and the first type of detection window is different from the second type of detection window.

In some possible embodiments, the apparatus 400 further comprises:

a third reading module, configured to, when the type of the target detection window is characterized by other types of detection windows, read third target data from the target storage device according to addressing manners corresponding to the other types of detection windows;

the number of the target storage units in the target storage device is not less than the window width of the other types of detection windows, and the other types of detection windows are different from the first type of detection windows and the second type of detection windows.

In some possible embodiments, the first type of detection window is a square window, the first target data includes at least first square window data of a first node and second square window data of a second node, and the first node is adjacent to the second node;

the first reading module 402 includes:

a first reading unit configured to read the first square window data from a plurality of target storage units on the slice in an addressing manner corresponding to the square window;

a second reading unit, configured to read first data corresponding to the second node from the multiple target storage units, where the first data is data that does not overlap with the first square window data in the second square window data, and the second square window data further includes data that overlaps with the first square window data.

In some possible embodiments, the apparatus 400 further comprises:

a first adding module, configured to add original data of a third node in an external storage device to the target storage device, where the third node is not adjacent to the second node.

In some possible embodiments, the second type of detection window is a cross window, and the second target data includes at least first cross window data of a first node and second cross window data of a second node, the first node being adjacent to the second node;

the second reading module 403 includes:

a third reading unit, configured to read the first cross window data from the multiple target storage units on the slice according to an addressing manner corresponding to a cross window;

a fourth reading unit, configured to read second data corresponding to the second node from the multiple target storage units, where the second data is data of the second cross window that is different from the first cross window data, and the second cross window data further includes data that is the same as the first cross window data.

In some possible embodiments, the apparatus 400 further comprises:

a second adding module, configured to add third original data of a third node in an external storage device to the target storage device, where the original data is data of a third thirty-word window of the third node that is different from the second twenty-word window of the third node, and the third node is not adjacent to the second node.

In some possible embodiments, the apparatus 400 further comprises:

and the denoising module is used for denoising the first target data and/or the second target data to obtain fourth target data, wherein the data volume of the fourth target data is smaller than that of the first target data or that of the second target data.

It should be noted that, in the data processing apparatus in this embodiment, corresponding to the data processing method in the foregoing method embodiment, specific implementations of each module and unit in this embodiment may be obtained by referring to descriptions of relevant parts in the foregoing method embodiment, and details are not described herein.

In addition, this application embodiment still provides a permanent false alarm detection device. Referring to fig. 5, fig. 5 shows a schematic structural diagram of a constant false alarm detection apparatus, and the apparatus 500 may include a first storage module 501, a determination module 502, a buffer 503, and a detection module 504.

The first storage module 501 may be configured to store data to be detected. In practical application, in the process of target detection, the radar system may transmit a signal by using a transmitting terminal (transmitting antenna) in the radar system, and after the signal is reflected by an object located in a detectable region of the radar system, a receiving terminal (receiving antenna) in the radar system receives a reflected signal (such as an echo signal), and performs corresponding processing on the reflected signal, such as fast fourier transform processing of a distance dimension or fast fourier transform processing of a speed dimension, to obtain data to be detected which needs to be processed by a constant false alarm rate. As an example, the first storage module 501 may be, for example, a memory, such as an SRAM located in a hardware acceleration chip or module; the data to be detected stored in the first storage module 501 may be a two-dimensional matrix data structure.

A determining module 502, configured to determine a detection window of a currently required usage type. As an example, the types of detection windows may include a square window, a cross window, a rectangular window, a triangular window, a trapezoidal window, and the like. During actual application, a user may select one of the detection window types to perform a corresponding configuration operation according to an application scenario in which the actual application is located, and correspondingly, the determining module 502 may determine the type of the detection window based on the selection operation performed by the user; in other embodiments, the determining module 502 may also automatically determine the type of the detection window by using the application scene sensed by the sensor, which is not limited in this embodiment.

As a specific implementation example of determining the type of the detection window, the constant false alarm detection apparatus may further include a second storage module, where the second storage module may store at least two types of detection windows, so that the determining module 502 may select one of the at least two types of detection windows as the detection window of the currently required usage type based on the received instruction or the scene parameter. Wherein the second memory module may be located in the same physical memory means as the first memory module 501.

The buffer 503 is configured to read a part of the data to be detected from the first storage module 501 through the detection window of the determined type, and buffer the read part of the data to be detected. It should be understood that each time the constant false alarm detection device performs constant false alarm detection using the detection window, only part of the data to be detected is processed each time, and correspondingly, the buffer 503 may buffer only part of the data to be detected each time. The buffer 503 may be located in a different physical storage means independent of the first storage module.

Illustratively, when the read data to be detected is a two-dimensional matrix data structure and constant false alarm detection is performed on any test node in the two-dimensional matrix data structure (i.e., a node when the two-dimensional matrix data structure is detected), the data cached by the buffer 503 is all data covered by the detection window of the type that needs to be used currently. Wherein the two-dimensional matrix data structure may comprise two dimensions. For convenience of description, the first dimension direction in the two-dimensional matrix data structure is defined as a row direction, and the second dimension direction is defined as a column direction. In practice, the first dimension may be, for example, a distance dimension, and the second dimension may be, for example, a doppler dimension; of course, the first dimension may also be a doppler dimension, and the second dimension is a distance dimension, which is not limited in this embodiment.

The buffer 503 may include a plurality of storage units, and when all data covered by the detection window of the currently required usage type is buffered in the buffer 503, the same column of data in the two-dimensional matrix data structure is stored in the same storage unit, and each storage unit may store only one column of data in the two-dimensional matrix data structure.

The detection module 504 is configured to perform constant false alarm detection on a portion of the data to be detected cached by the cache 503 based on the detection window of the determined currently required usage type, and a specific implementation process of performing constant false alarm detection by using the detection window may refer to the description of relevant parts in the foregoing embodiments, which is not described herein again.

In practical application, because partial data overlap exists between window data corresponding to two adjacent test nodes, when the constant false alarm device 500 respectively performs constant false alarm detection on two connected test nodes in the two-dimensional matrix data structure, the constant false alarm device can perform constant false alarm detection on the two connected test nodes in a manner of sharing partial data, so that after the window data corresponding to one test node is read, data overlapping with the test node in the window data corresponding to the other test node does not need to be read repeatedly, and only data not overlapping with the test node in the window data corresponding to the other test node can be read, so that the read data amount can be reduced, thereby reducing consumption of hardware resources and improving efficiency of data processing.

In practical applications, the constant false alarm apparatus 500 may be implemented in an integrated circuit, and accordingly, the detection module 504 in the constant false alarm apparatus 500 may be a CPU (central Processing unit) or a DSP (Digital Signal Processing) element in the integrated circuit.

Further, when the constant false alarm device 500 is implemented by an integrated circuit, the integrated circuit may be a chip structure, such as a millimeter wave radar chip. Of course, other hardware implementations of the integrated circuit are possible. The buffer may be a static random access memory, but of course, may be other types of memory.

In addition, the embodiment of the application also provides equipment. Referring to fig. 6, fig. 6 shows a schematic hardware structure diagram of an apparatus in an embodiment of the present application, where the apparatus 600 includes a processor 601 and a memory 602:

the memory 602 is used for storing program codes and transmitting the program codes to the processor 601;

the processor 601 is configured to perform the following steps according to instructions in the program code:

determining the type of a target detection window;

when the type of the target detection window is characterized as a first type of detection window, reading first target data from a target storage device on a chip according to an addressing mode corresponding to the first type of detection window;

when the type of the target detection window is characterized as a second type of detection window, reading second target data from the target storage device according to an addressing mode corresponding to the second type of detection window;

Further, the processor 601 is configured to execute specific steps or other steps described in the above method embodiments according to instructions in the program code, or to implement functions described in the above apparatus embodiments.

In one embodiment, the present application also provides a radio device comprising: a carrier; the integrated circuit of the above embodiment is disposed on the carrier; an antenna disposed on the carrier; the integrated circuit is connected with the antenna through the first transmission line and used for receiving and transmitting radio signals. The carrier can be a Printed Circuit Board (PCB), and the first transmission line can be a PCB wiring line. In addition, the integrated circuit can be integrated with the antenna to form a device such as AiP.

In one embodiment, the present application further provides an apparatus comprising: an apparatus body; and a radio device as in the above embodiment provided on the apparatus body; wherein the radio device is used for object detection and/or communication.

Specifically, on the basis of the above-described embodiments, in one embodiment of the present application, the radio device may be provided outside the apparatus body, in another embodiment of the present application, the radio device may be provided inside the apparatus body, and in other embodiments of the present application, the radio device may be provided partly inside the apparatus body and partly outside the apparatus body. The present application is not limited thereto, as the case may be.

It should be noted that the radio device can perform functions such as object detection and communication by transmitting and receiving signals.

In an alternative embodiment, the device body may be a component and a product applied to fields such as smart home, transportation, smart home, consumer electronics, monitoring, industrial automation, in-cabin detection, health care, and the like; for example, the device body can be an intelligent transportation device (such as an automobile, a bicycle, a motorcycle, a ship, a subway, a train and the like), a security device (such as a camera), an intelligent wearable device (such as a bracelet, glasses and the like), an intelligent household device (such as a television, an air conditioner, an intelligent lamp and the like), various communication devices (such as a mobile phone, a tablet personal computer and the like), a barrier gate, an intelligent traffic indicator lamp, an intelligent indicator board, a traffic camera, various industrial manipulators (or robots) and the like, and can also be various instruments for detecting vital sign parameters and various devices carrying the instruments. The radio device may be a radio device as set forth in any embodiment of the present application, and the structure and the operation principle of the radio device have been described in detail in the above embodiments, which are not described in detail herein.

The embodiment of the application also provides a computer readable storage medium. The methods described in the above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media may include computer storage media and communication media, and may include any medium that can communicate a computer program from one place to another. A storage medium may be any target medium that can be accessed by a computer.

As an alternative design, a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that is targeted for carriage or stores desired program code in the form of instructions or data structures and that is accessible by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Such a concatenation is also intended to be included within the scope of computer readable media.

It should be noted that "of, corresponding to" and "corresponding" may be sometimes used in combination in the present application, and it should be noted that the intended meaning is consistent when the difference is not emphasized.

It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present application, "at least one" means one or more. "plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any concatenation of these items, including any concatenation of single item(s) or plural item(s). For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple. In addition, in order to facilitate clear description of technical solutions of the embodiments of the present application, in the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by software plus a general hardware platform. Based on such understanding, the technical solution of the present application may be embodied in the form of a software product, which may be stored in a storage medium, such as a read-only memory (ROM)/RAM, a magnetic disk, an optical disk, or the like, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the method according to the embodiments or some parts of the embodiments of the present application.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the modules described as separate parts may or may not be physically separate, and the parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

The above description is only an exemplary embodiment of the present application, and is not intended to limit the scope of the present application.

Claims

1. A method of data processing, the method comprising:

determining the type of a target detection window;

2. The method of claim 1, wherein the first type of detection window is a square window, and the first target data comprises at least first square window data of a first node and second square window data of a second node, the first node being adjacent to the second node;

the reading of the first target data from the target storage device on the chip according to the addressing mode corresponding to the detection window of the first type includes:

reading the first square window data from the target storage units on the chip according to the addressing mode corresponding to the square window;

reading first data corresponding to the second node from the target storage units, wherein the first data is data which is not overlapped with the first square window data in the second square window data, and the second square window data further comprises data which is overlapped with the first square window data.

3. The method of claim 2, further comprising:

adding original data of a third node in an external storage device to the target storage device, the third node not being adjacent to the second node.

4. The method of claim 1, wherein the second type of detection window is a cross window, and the second target data comprises at least first cross window data of a first node and second cross window data of a second node, the first node being adjacent to the second node;

the reading second target data from the plurality of target storage units on the slice according to the addressing mode corresponding to the detection window of the second type includes:

reading the first cross window data from a plurality of target storage units on the chip according to an addressing mode corresponding to a cross window;

and reading second data corresponding to the second node from the plurality of target storage units, wherein the second data is different from the first cross window data in the second cross window data, and the second cross window data also comprises data which is the same as the first cross window data.

5. The method of claim 4, further comprising:

6. The method of claim 1, further comprising:

when the type of the target detection window is characterized by other types of detection windows, reading third target data from the target storage device according to the addressing modes corresponding to the other types of detection windows respectively;

7. The method according to any one of claims 1 to 6, further comprising:

and denoising the first target data and/or the second target data to obtain fourth target data, wherein the data volume of the fourth target data is smaller than that of the first target data or that of the second target data.

8. A data processing apparatus, characterized in that the apparatus comprises:

the determining module is used for responding to the configuration operation of a user aiming at the detection window type and determining the target detection window type;

the first reading module is used for reading first target data from a plurality of target storage units on the chip according to an addressing mode corresponding to the detection window of the first type when the type of the target detection window is characterized as the detection window of the first type;

a second reading module, configured to, when the type of the target detection window is characterized as a second type of detection window, read second target data from the multiple target storage units on the slice according to an addressing manner corresponding to the second type of detection window;

the number and the size of the target storage devices are not lower than the window width sizes of the first type of detection window and the second type of detection window, and the first type of detection window is different from the second type of detection window.

9. The apparatus of claim 8, further comprising:

a third reading module, configured to, when the type of the target detection window is characterized by other types of detection windows, read third target data from the multiple target storage units on the slice according to an addressing manner corresponding to each of the other types of detection windows;

the number of the target storage devices is not less than the window width of the other types of detection windows, and the other types of detection windows are different from the first type of detection windows and the second type of detection windows.

10. A computer device, the device comprising a processor and a memory:

the memory is used for storing program codes and transmitting the program codes to the processor;

the processor is configured to perform the data processing method of any one of claims 1 to 7 according to instructions in the program code.

11. A constant false alarm detection device, comprising:

the first storage module is used for storing data to be detected;

the determining module is used for determining a detection window of a currently required use type;

the buffer is used for buffering part of the data to be detected based on the detection window of the current required use type; and

and the detection module is used for carrying out constant false alarm detection on the data to be detected cached by the cache based on the detection window of the current required use type.

12. The apparatus of claim 11, further comprising:

the second storage module stores at least two types of detection windows;

wherein the determining module is configured to select one of the at least two types of detection windows as the detection window of the currently required usage type based on the received instruction or the scene parameter.

13. The apparatus of claim 12, wherein the at least two types of detection windows comprise at least two of a cross-shaped detection window, a square-shaped detection window, a rectangular-shaped detection window, a triangular-shaped detection window, and a trapezoidal-shaped detection window.

14. The apparatus according to any one of claims 11-13, wherein the data to be detected is a two-dimensional matrix data structure;

when the constant false alarm detection is performed on any test node in the two-dimensional matrix data structure, the buffer is used for caching all data covered by the detection window of the current required use type.

15. The apparatus of claim 14, wherein the buffer comprises a plurality of storage cells, and a first dimension direction of the two-dimensional matrix data structure is defined as a row direction, and a second dimension direction is defined as a column direction;

when all data covered by the detection window of the currently required use type is cached in the cache, the same column of data in the two-dimensional matrix data structure is stored in the same storage unit, and each storage unit can only store one column of data in the two-dimensional matrix data structure.

16. The apparatus of claim 15, wherein the first dimension is a distance dimension and the second dimension is a doppler dimension; or

The first dimension is a doppler dimension and the second dimension is a range dimension.

17. The apparatus of claim 14, wherein the two adjacent test nodes in the two-dimensional matrix data structure are respectively subjected to constant false alarm detection by sharing partial data.

18. The apparatus of claim 14, wherein the buffer and the first storage module are located in separate physical storage components; and/or

The first storage module and the second storage module are located in the same physical storage means.

19. The apparatus of claim 18, wherein the constant false alarm detection apparatus is an integrated circuit, and the detection module is a CPU or a DSP in the integrated circuit.

20. The apparatus of claim 19, wherein the integrated circuit is a chip structure;

wherein, the buffer is a static random access memory.

21. The apparatus of claim 20, wherein the integrated circuit is a millimeter wave radar chip.

22. A radio device, comprising:

a carrier;

the device of any one of claims 11-21, disposed on a carrier;

an antenna disposed on the carrier or on the carrier with an AiP structure integral with the device;

the device is connected with the antenna and used for transmitting and receiving radio signals by the antenna.

23. An apparatus, comprising:

an apparatus body; and

the radio of claim 22 disposed on the equipment body;

wherein the radio device is used for object detection and/or communication.