CN113322512A - Process method for improving consistency of transition region of epitaxial wafer - Google Patents
Process method for improving consistency of transition region of epitaxial wafer Download PDFInfo
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- CN113322512A CN113322512A CN202110883669.XA CN202110883669A CN113322512A CN 113322512 A CN113322512 A CN 113322512A CN 202110883669 A CN202110883669 A CN 202110883669A CN 113322512 A CN113322512 A CN 113322512A
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/14—Feed and outlet means for the gases; Modifying the flow of the reactive gases
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/16—Controlling or regulating
- C30B25/165—Controlling or regulating the flow of the reactive gases
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Abstract
The invention discloses a process method for improving consistency of transition regions of epitaxial wafers, which comprises the following steps: preparing a substrate sheet: selecting a heavily As-doped substrate slice with the resistivity of 0.002-0.004 omega-cm, and carrying out epitaxial growth: the source adopts ultra-pure trichlorosilane, an epitaxial layer with the target thickness is grown, and meanwhile, a corresponding doping source is introduced. The doping source introduction amount is divided into two sections: the first section adopts a variable doping mode, the initial doping flow set value is 0.1 omega cm or less, the corresponding heavy doping quality with the resistivity of 0.5 omega cm or less, the end point doping flow set value is the doping amount corresponding to the target resistivity of the epitaxial layer, the doping amount change rate is constant, and the change interval can be 15% -30% of the total thickness; the doping input amount of the second section is constant, and the doping amount set value is the doping amount corresponding to the target resistivity of the epitaxial layer. By adopting the process method provided by the invention, the deviation of the center and the edge in the chip is obviously reduced.
Description
Technical Field
The invention relates to a semiconductor base material silicon epitaxial wafer, in particular to an epitaxial wafer grown by using a heavily doped substrate.
Background
An epitaxial growth process is a method of depositing a thin layer of single crystal on the surface of a single crystal substrate. Vapor phase epitaxy has been most widely used due to good control of impurity concentrations and the ability to obtain crystalline integrity.
However, the uniformity of the transition region at the center and the edge of the epitaxial wafer is greatly influenced by the influence of the substrate self-doping factor in the epitaxial process, and the wafer throwing result of the device is further influenced.
Therefore, it is desired to solve the above problems.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to reduce the influence of autodoping introduced by a heavily doped substrate on an epitaxial process and improve the consistency of transition regions in an epitaxial wafer.
The technical scheme is as follows: in order to achieve the above object, the present invention provides a process method for improving the consistency of an epitaxial wafer transition region, which comprises the following steps:
A. preparing a substrate slice;
B. and (3) epitaxial growth: growing an epitaxial layer with a target thickness by using ultra-high-purity trichlorosilane as a silicon source, and simultaneously introducing a corresponding doping source; the doping source introduction amount is divided into two sections:
a first stage: a variable doping mode is adopted, the initial doping flow set value is 0.1 omega-cm or less, the corresponding heavy doping quality with the resistivity of 0.5 omega-cm or less, the end point doping flow set value is the doping amount corresponding to the target resistivity of the epitaxial layer, the doping amount change rate is constant, and the change interval can be selected to be 15% -30% of the total thickness;
and a second stage: the doping input amount is constant, and the doping amount set value is the doping amount corresponding to the target resistivity of the epitaxial layer.
Has the advantages that: compared with the prior art, the consistency of the transition regions of the center and the edge in the epitaxial wafer prepared by the process method for improving the consistency of the transition regions of the epitaxial wafer is obviously improved. For comparison, under the process conditions of the prior art, the percentage deviation of the transition region between the center and the edge in the wafer to the total thickness of the epitaxy is about 20%; by adopting the process method provided by the invention, the deviation of the center and the edge in the chip is obviously reduced.
Drawings
FIG. 1 is a schematic view of an apparatus used in the process of the present invention.
Fig. 2 is a longitudinal structure diagram of the in-wafer center and edge resistivities of an epitaxial wafer according to an embodiment of the invention.
FIG. 3 is a longitudinal structure diagram of the center and edge resistivities within an epitaxial wafer in accordance with an embodiment of the present invention.
Fig. 4 is a longitudinal structure diagram of the in-wafer center and edge resistivities of three epitaxial wafers according to the embodiment of the present invention.
Fig. 5 is a longitudinal structure diagram of the resistivity of the center and edge of the slice of the comparative example epitaxial wafer of the prior art.
Detailed Description
The technical scheme of the invention is further explained by combining the attached drawings.
As shown in FIG. 1, the equipment which can be used in the present invention is an Italy-produced PE-3061T epitaxial furnace, which comprises a loading and taking area, a transfer chamber and a reaction chamber. The base is made by cracking the surface of high-purity graphite, wrapping high-purity SiC on the surface, and heating by high-frequency induction. The hydrogen purifier is adsorbed by a molecular sieve, and the purity is 99.9999%.
The invention provides a process method for improving consistency of transition regions of epitaxial wafers, which comprises the following steps:
A. preparing a substrate sheet: selecting a heavily-doped As substrate sheet, wherein the resistivity is 0.002-0.004 omega-cm, and the back seal structure can be LTO back seal or POLY + LTO back seal or LTO + POLY back seal;
B. cleaning a reactor: the quartz bell jar and the quartz bracket must be carefully cleaned before high resistance epitaxy is carried out so as to remove impurity atoms and residues adsorbed on the inner wall of the quartz reactor and a quartz piece;
C. treating a graphite base: before epitaxial growth, introducing HCl gas to treat residual silicon and impurities on the surface of the base;
D. and (3) epitaxial growth: the silicon source adopts ultra-high purity trichlorosilane, an epitaxial layer with the target thickness is grown, and meanwhile, a corresponding doping source is introduced. The doping source introduction amount is divided into two sections:
the first section adopts a variable doping mode, the initial doping flow set value is 0.1 omega cm or less, the corresponding heavy doping quality with the resistivity of 0.5 omega cm or less, the end point doping flow set value is the doping amount corresponding to the target resistivity of the epitaxial layer, the doping amount change rate is constant, and the change interval can be 15% -30% of the total thickness; the correspondence between the resistivity and the doping amount of the epitaxial layer is influenced by various factors such as doping source concentration, growth temperature, growth rate and the like, and no clear correspondence exists. In the production operation process, a doping value is generally preset, the resistivity parameter is tested through trial production, and then the doping setting amount is adjusted on the basis of the result to realize the expected resistivity parameter.
The doping input amount of the second section is constant, and the doping amount set value is the doping amount corresponding to the target resistivity of the epitaxial layer. The growth temperature in the epitaxial growth process is 1040-1060 ℃, and the growth rate is 2.3-2.8 mu m/min.
Specifically, the following examples are compared with comparative examples to illustrate the application effects of the process of the present invention in the specific examples.
In the first embodiment, a preliminary substrate piece having a resistivity of 0.002 Ω. cm was selected. The first section adopts a variable doping mode to select a variable interval, which is 15% of the total thickness and corresponds to the resistivity of 0.1 omega cm. The doping input amount of the second section is constant, and the doping amount set value is the doping amount corresponding to the target resistivity of the epitaxial layer. The growth temperature in the epitaxial growth process is 1040 ℃, the growth rate is 2.3 mu m/min, and the growth rate can be seen by combining the longitudinal structure diagram of the electrical resistivity of the center and the edge of the epitaxial wafer in the figure 2. The longitudinal structure diagram of the resistivity of the center and the edge in the epitaxial wafer is as follows, and the percentage deviation of the transition region of the center and the edge in the wafer, which is obtained by tests, in the total thickness of the epitaxy is about 13%.
In the second example, a preliminary substrate piece having a resistivity of 0.003 Ω. cm was selected. The first section adopts a variable doping mode to select a variation interval which is 25 percent of the total thickness and corresponds to the resistivity of 0.3 omega cm. The doping input amount of the second section is constant, and the doping amount set value is the doping amount corresponding to the target resistivity of the epitaxial layer. The growth temperature in the epitaxial growth process is 1050 ℃, the growth rate is 2.5 mu m/min, and can be seen by combining the longitudinal structure diagram of the electrical resistivity of the center and the edge in the epitaxial wafer in the figure 3. The deviation of the percentage of the transition region between the center and the edge of the wafer in the total thickness of the epitaxy is about 1 percent.
In the third example, a preliminary substrate sheet having a resistivity of 0.004. omega. cm was selected. The first section adopts a variable doping mode to select a variable interval which is 30 percent of the total thickness and corresponds to the resistivity of 0.5 omega cm. The doping input amount of the second section is constant, and the doping amount set value is the doping amount corresponding to the target resistivity of the epitaxial layer. The growth temperature in the epitaxial growth process is 1060 ℃, the growth rate is 2.8 mu m/min, and can be seen by combining the longitudinal structure diagram of the electrical resistivity of the center and the edge in the epitaxial wafer in the figure 4. The deviation of the percentage of the transition region between the center and the edge of the wafer in the total thickness of the epitaxy is about 4 percent.
As a comparative example of the prior art, under the prior art process conditions, it can be seen from the longitudinal structure diagram of the resistivity of the center and the edge in the epitaxial wafer in fig. 5 that the percentage deviation of the transition region of the center and the edge in the wafer to the total thickness of the epitaxy is about 21%, which is poor in quality.
Therefore, the comparison shows that the deviation of the center and the edge in the epitaxial wafer manufactured by the technical scheme of the invention is obviously reduced.
Claims (10)
1. A process method for improving consistency of a transition region of an epitaxial wafer is characterized by comprising the following steps:
A. preparing a substrate slice;
B. and (3) epitaxial growth: growing an epitaxial layer with a target thickness by using ultra-high-purity trichlorosilane as a silicon source, and simultaneously introducing a corresponding doping source; the doping source introduction amount is divided into two sections:
a first stage: a variable doping mode is adopted, the initial doping flow set value is 0.1 omega-cm or less, the corresponding heavy doping quality with the resistivity of 0.5 omega-cm or less, the end point doping flow set value is the doping amount corresponding to the target resistivity of the epitaxial layer, the doping amount change rate is constant, and the change interval can be selected to be 15% -30% of the total thickness;
and a second stage: the doping input amount is constant, and the doping amount set value is the doping amount corresponding to the target resistivity of the epitaxial layer.
2. The process according to claim 1, characterized in that: the deposition residues on the inner wall of the quartz reactor and quartz parts in the epitaxial equipment are cleaned before the epitaxy is carried out.
3. The process according to claim 1, characterized in that: and selecting a heavily As-doped substrate slice in the step A, wherein the resistivity of the heavily As-doped substrate slice is 0.002-0.004 omega-cm.
4. A process according to claim 3, characterized in that: the back seal structure of the heavily As-doped substrate slice is LTO back seal, POLY + LTO back seal or LTO + POLY back seal.
5. The process according to claim 1, characterized in that: in the second stage of the step B, the growth temperature in the epitaxial growth process is 1040-1060 ℃, and the growth rate is 2.3-2.8 mu m/min.
6. The process according to claim 1, characterized in that: in the first stage of step B, the change rate = (initial doping amount set value-end doping amount set value)/(thickness of change interval/growth rate).
7. The process of claim 2, wherein: before epitaxial growth, HCl gas is introduced to treat residual silicon and impurities on the surface of the susceptor.
8. The process according to any one of claims 1 to 7, characterized in that: step A, selecting a prepared substrate sheet with the resistivity of 0.002 omega-cm; in the first section of the step B, a variable doping mode is adopted to select a variable interval which is 15% of the total thickness and has the corresponding resistivity of 0.1 omega cm; in the second stage of the step B, the growth temperature in the epitaxial growth process is 1040 ℃, and the growth rate is 2.3 mu m/min.
9. The process according to any one of claims 1 to 7, characterized in that: step A, selecting a prepared substrate sheet with the resistivity of 0.003 omega-cm; in the first section of the step B, a variable doping mode is adopted to select a variable interval which is 25 percent of the total thickness and corresponds to the resistivity of 0.3 omega cm; in the second stage of the step B, the growth temperature in the epitaxial growth process is 1050 ℃, and the growth rate is 2.5 mu m/min.
10. The process according to any one of claims 1 to 7, characterized in that: step A, selecting a prepared substrate sheet with the resistivity of 0.004 omega-cm; in the first section of the step B, a variable doping mode is adopted to select a variable interval which is 30 percent of the total thickness and has the corresponding resistivity of 0.5 omega cm; in the second stage of the step B, the growth temperature in the epitaxial growth process is 1060 ℃, and the growth rate is 2.8 mu m/min.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115506010A (en) * | 2022-10-11 | 2022-12-23 | 中环领先半导体材料有限公司 | Process method for improving depth of epitaxial edge flat area of ultra-heavily doped Ph substrate |
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| JP2002020198A (en) * | 2000-06-29 | 2002-01-23 | Shin Etsu Handotai Co Ltd | Method of producing silicon epitaxial wafer |
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| CN104947183A (en) * | 2015-05-29 | 2015-09-30 | 中国电子科技集团公司第四十六研究所 | Production method of heavily phosphorus-doped thin substrate silicon epitaxial layer for Schottky devices |
| CN105575772A (en) * | 2015-12-25 | 2016-05-11 | 河北普兴电子科技股份有限公司 | Preparation method of epitaxial wafer for FRD |
| CN106803480A (en) * | 2017-02-14 | 2017-06-06 | 河北普兴电子科技股份有限公司 | The application of the method and epitaxial wafer of P+ Growns N silicon epitaxial wafers under normal pressure |
| CN106952965A (en) * | 2017-03-27 | 2017-07-14 | 河北普兴电子科技股份有限公司 | Silicon epitaxial wafer and preparation method thereof |
| CN108417483A (en) * | 2018-03-29 | 2018-08-17 | 南京国盛电子有限公司 | A kind of preparation method of 8 inches of high-power IGBTs component epitaxial wafer |
-
2021
- 2021-08-03 CN CN202110883669.XA patent/CN113322512B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS5649519A (en) * | 1979-09-29 | 1981-05-06 | Fujitsu Ltd | Vapor growth of compound semiconductor |
| JP2002020198A (en) * | 2000-06-29 | 2002-01-23 | Shin Etsu Handotai Co Ltd | Method of producing silicon epitaxial wafer |
| CN102453958A (en) * | 2010-10-21 | 2012-05-16 | 上海华虹Nec电子有限公司 | Method for reducing epitaxy auto-doping effect |
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| CN106952965A (en) * | 2017-03-27 | 2017-07-14 | 河北普兴电子科技股份有限公司 | Silicon epitaxial wafer and preparation method thereof |
| CN108417483A (en) * | 2018-03-29 | 2018-08-17 | 南京国盛电子有限公司 | A kind of preparation method of 8 inches of high-power IGBTs component epitaxial wafer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115506010A (en) * | 2022-10-11 | 2022-12-23 | 中环领先半导体材料有限公司 | Process method for improving depth of epitaxial edge flat area of ultra-heavily doped Ph substrate |
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