CN113312869A

CN113312869A - Integrated circuit device, method and system for generating integrated circuit layout diagram

Info

Publication number: CN113312869A
Application number: CN202110184515.1A
Authority: CN
Inventors: 赖柏嘉; 郭明璋; 高章瑞; 张玮玲; 陈维仁; 庄惠中; 斯帝芬·鲁苏; 鲁立忠
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-02-27
Filing date: 2021-02-10
Publication date: 2021-08-27
Also published as: TW202133023A; TWI758974B; DE102020127090A1

Abstract

Embodiments of the present application relate to integrated circuit devices, methods and systems for generating integrated circuit layouts. The method includes positioning adjacent first through fourth active regions in a cell of an IC layout, the first active region being of a first type that is n-type or p-type and corresponding to a first total number of fins, the second active region being of a second type that is n-type or p-type and corresponding to a second total number of fins, the third active region being of the second type and corresponding to a third total number of fins, and the fourth active region being of the first type and corresponding to a fourth total number of fins. Each of the first and second total number of fins is greater than each of the third and fourth total number of fins, and locating at least one of the first, second, third, or fourth active regions is performed by the processor.

Description

Integrated circuit device, method and system for generating integrated circuit layout diagram

Technical Field

Embodiments of the present application relate to integrated circuit devices, methods and systems for generating integrated circuit layouts.

Background

The continuing trend to miniaturize Integrated Circuits (ICs) has resulted in increasingly miniaturized devices consuming less power and providing more functionality at higher speeds than earlier technologies. In some cases, the IC technology includes fin field effect transistors (finfets), where the channel geometry is condensed along multiple fin dimensions.

Such miniaturization has been achieved through design and manufacturing innovations associated with increasingly stringent specifications. Various Electronic Design Automation (EDA) tools are used to generate, modify and verify the design of semiconductor devices while ensuring that design and manufacturing specifications are met.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a method of generating an integrated circuit layout diagram, the method including: positioning a first active region in a cell of an integrated circuit layout, the first active region being of a first type, n-type or p-type, and corresponding to a first total number of fins; positioning a second active region in the cell adjacent to the first active region, the second active region being of a second type, n-type or p-type, and corresponding to a second total number of fins; positioning a third active area in the cell adjacent to the second active area, the third active area being of the second type and corresponding to a third total number of fins; and positioning a fourth active area in the cell adjacent to the third active area, the fourth active area being of the first type and corresponding to a fourth total number of fins, wherein each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and positioning at least one of the first, second, third, or fourth active areas is performed by the processor.

According to another aspect of an embodiment of the present application, there is provided an integrated circuit layout generation system including: a processor; and a non-transitory computer readable storage medium comprising computer program code for the one or more programs, the non-transitory computer readable storage medium and the computer program code configured to, with the processor, cause the system to: assigning a first block of circuitry to a first number of fins; arranging a first set of blocks using first and second active regions of an integrated circuit layout cell, the first and second active regions collectively corresponding to a plurality of fins having a first number of fins; arranging a second set of blocks of circuitry using third and fourth active areas of the integrated circuit layout cell, the third and fourth active areas collectively corresponding to a plurality of fins having a second number of fins less than the first number of fins; and generating an integrated circuit layout file based on the integrated circuit layout unit.

According to another aspect of embodiments of the present application, there is provided an integrated circuit device including: a first power rail; a second power rail electrically connected to the first power rail; a third power rail located between and electrically isolated from the first and second power rails; a first active region of a first type adjacent to the first power rail and comprising a first total number of fins; a second active region of a second type, different from the first type, adjacent to the first active region and the third power rail, and comprising a second total number of fins; a third active region of the second type adjacent to the third power rail and comprising a third total number of fins; and a fourth active region of the first type adjacent to the third active region and the second power rail and comprising a fourth total number of fins, wherein a first sum of the first and second total numbers of fins is greater than a second sum of the third and fourth total numbers of fins.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a flow diagram of a method of generating an IC layout diagram according to some embodiments.

Fig. 2 depicts an IC layout diagram according to some embodiments.

Fig. 3 is a flow diagram of a method of generating an IC layout diagram according to some embodiments.

4A-6 illustrate non-limiting examples of operations of methods of generating IC layouts according to some embodiments.

Fig. 7 is a diagram of an IC device according to some embodiments.

Fig. 8 is a block diagram of an IC layout generation system according to some embodiments.

Fig. 9 is a block diagram of an IC manufacturing system and IC manufacturing flow associated therewith, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, etc., are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

In various embodiments, an IC layout and devices fabricated based on the IC layout include transistors distributed between regions having varying fin counts. By distributing transistors between relatively high and low fin counts, a relatively high fin count is selectively applied to critical circuit blocks, thereby reducing circuit power while maintaining speed and area requirements compared to methods that do not allocate transistor blocks for relatively high and low fin counts.

Fig. 1 is a flow diagram of a method 100 of generating an IC layout diagram according to some embodiments. In some embodiments, generating the IC layout includes generating an IC layout, such as IC layout 200 discussed below with respect to fig. 2, that corresponds to an IC device manufactured based on the generated IC layout, such as IC device 700 discussed below with respect to fig. 7. Non-limiting examples of IC devices include logic devices, flip-flops, multiplexers, processing devices, signal processing circuits, and so forth.

In some embodiments, some or all of method 100 is performed by a processor of a computer. In some embodiments, some or all of the method 100 is performed by the processor 802 of the IC layout generation system 800 discussed below with reference to fig. 8.

Some or all of the operations of method 100 can be performed as part of a design process performed in a design room (e.g., design room 920 discussed below with reference to fig. 9).

In some embodiments, the operations of method 100 are performed in the order depicted in fig. 1. In some embodiments, the operations of method 100 are performed simultaneously and/or in a different order than depicted in fig. 1. In some embodiments, one or more operations of method 100 are performed before, during, and/or after performing one or more operations.

In some embodiments, some or all of the operations of method 100 are included in one or more operations of a method of operating an IC manufacturing system, such as operation 340 of method 300 discussed below with respect to fig. 3-6.

Fig. 2 is a depiction of a non-limiting example of an IC layout 200 generated in some embodiments by performing one or more operations of method 100 as described below. For illustrative purposes, the IC layout diagram 200 is simplified. In various embodiments, IC layout diagram 200 includes components other than those shown in fig. 2, such as one or more transistor elements, vias, contacts, isolation structures, wells, conductive elements, and the like.

Fig. 2 shows the cell 200C, X orientation and the Y direction perpendicular to the X direction. For purposes of illustration, the X direction, depicted as horizontal and the Y direction, depicted as vertical, with respect to the page are non-limiting examples. In various embodiments, the X-direction and the Y-direction are perpendicular to each other and have different directions than those shown in FIG. 2. The X direction includes a positive X direction shown in fig. 2 and a negative X direction (not labeled) opposite to the positive X direction. The Y direction includes a positive Y direction shown in fig. 2 and a negative Y direction (not labeled) opposite to the positive Y direction.

The cell 200C includes: a boundary 200B extending in the Y direction from the trajectory T1 to the trajectory T3, thereby having a height CH; active areas AR1-AR4 extending in the X direction; and gate regions GR1-GR3 extending in the Y direction and intersecting each of the active regions AR1-AR 4. The active areas AR1 and AR2 are located in the block area BL1 between the trajectory T1 and the trajectory T2, and the active areas AR3 and AR4 are located in the block area BL2 between the trajectories T2 and T3. The cut polysilicon region CP extends in the X direction along the trajectory T2 and intersects the gate region GR2 between the active regions AR2 and AR 3.

The active regions (e.g., active regions AR1-AR4) are regions included in the IC layout as part of the definition of the active regions in the semiconductor substrate during the fabrication process, also referred to as oxide diffusion Or Definition (OD) in some embodiments.

The active region is a continuous portion of a semiconductor substrate having n-type or p-type doping, which includes various semiconductor structures, including one or more fins of a FinFET in some embodiments. In various embodiments, the active region is located within a well, i.e., an n-well or a p-well, within the semiconductor substrate and/or is electrically isolated from other elements in the semiconductor substrate by one or more isolation structures, such as one or more Shallow Trench Isolation (STI) structures.

The fin is an elevated elongated portion extending in a first direction (e.g., the X direction in the embodiment shown in fig. 2) in the active region, and includes one or more elemental semiconductors (e.g., silicon (Si) or germanium (Ge)), compound semiconductors (e.g., silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (ISb)), or alloy semiconductors (e.g., GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP, etc.).

Each active area corresponds to the total number of fins. In various embodiments, a given active area corresponds to a total number of fins ranging from 1 to 6. In some embodiments, a given active area corresponds to a total number of fins greater than six.

In some embodiments, the active region includes one or more source/drain (S/D) structures corresponding to one or more S/D regions (not shown) within the active region that define the active region. The S/D structure is a semiconductor structure adjacent to or including a portion of the one or more fins within the active region and is configured to have a doping type opposite to a doping type of other portions of the active region. In some embodiments, the S/D structure is configured to have a lower resistivity than other portions of the active region, for example, by including one or more portions with a doping concentration greater than one or more doping concentrations, or otherwise present throughout the active region. In various embodiments, the S/D structure includes an epitaxial region of semiconductor material (e.g., Si, SiGe, and/or SiC).

Gate regions, such as gate regions GR1-GR3, are regions included in the IC layout that are part of the gate structure defined overlying the semiconductor substrate during the fabrication process.

The gate structure is a volume extending in a direction perpendicular to the active area (e.g., the Y-direction in the embodiment shown in fig. 2) and includes a gate electrode substantially surrounded by one or more dielectric layers. The gate electrode includes one or more conductive segments comprising one or more conductive materials (e.g., polysilicon), one or more metals, and/or one or more other suitable materials, and is thus configured to control voltage along the underlying and adjacent dielectric layer. In various embodiments, the dielectric layer comprises one or more of silicon dioxide and/or another suitable material, for example, a dielectric material having a k value greater than 3.8 or 7.0, also referred to as a high-k dielectric material in some embodiments. In some embodiments, the high-k dielectric material comprises aluminum oxide, hafnium oxide, lanthanum oxide, or another suitable material.

In some cases, the location in the IC layout where the gate region intersects the active region corresponds to a transistor in a respective IC device that includes a portion of the corresponding gate structure overlying the corresponding active region, a portion of the active region underlying and surrounded by the gate structure, and an S/D structure adjacent to the gate structure. In various embodiments, the transistor is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor depending on the doping type of the active region corresponding to the associated active region. In other cases, the gate region intersects the active region at a location that does not correspond to a transistor, and in some embodiments, the corresponding gate structure is referred to as a dummy gate structure.

A block region, such as block region BL1 or BL2, is a region of the IC layout that includes a portion of one or more locations in the design process that are a subset of the plurality of transistors that define a circuit, also referred to as a block or block of circuitry in some embodiments. The one or more locations correspond to a total number of fins associated with each active region as described below and associated with circuit block assignments discussed below with respect to method 300 and fig. 3-7.

In the embodiment shown in fig. 2, the position in the block region BL1 where the gate region GR2 intersects the active regions AR1 and AR2 corresponds to a first transistor block (not labeled) configured as a first inverter, for example, and the position in the block region BL2 where the gate region GR2 intersects the active regions AR3 and AR4 corresponds to a second transistor block (not labeled) configured as a second inverter, for example.

A cut polysilicon region, such as cut polysilicon region CP, is a region of the IC layout that is included as part of defining discontinuities in some or all of the gate structure during the fabrication process, such that corresponding gate electrodes are separated into portions that are electrically isolated from one another.

In the embodiment shown in fig. 2, the cut polysilicon region CP partially defines a discontinuity in the gate electrode corresponding to the gate region GR2 such that the gate of the transistor corresponding to the bulk region BL1 is electrically isolated from the gate of the transistor corresponding to the bulk region BL 2.

Traces, such as traces T1-T3, are lines included in the IC layout as part of defining the relative position of the IC structure corresponding to the IC layout feature based on the orientation of the trace in the manufacturing process.

In the embodiment shown in fig. 2, the traces T1-T3 correspond to locations of the power rail defined in part by respective power rail regions PR1-PR3, which in some embodiments are also referred to as conductive regions PR1-PR 3.

Conductive regions, such as power rail regions PR1-PR3, are regions of the IC layout that are included in the manufacturing process as part of one or more segments that define one or more conductive layers in the IC device. In various embodiments, one or more of the power rail regions PR1-PR3 correspond to one or more segments of the same or different conductive layers in the IC device. In various embodiments, the one or more power rail regions PR1-PR3 correspond to one or more of a buried metal layer, a first metal layer, a second metal layer, or a higher metal layer in the IC device.

Each active area AR1 and AR4 is one of n-type corresponding to n-type doping or p-type corresponding to p-type doping, and each active area AR2 and AR3 is the other of n-type or p-type. In embodiments where active areas AR1 and AR4 are n-type, each of the adjacent power rail regions PR1 and PR3 corresponds to a reference power rail configured to carry a reference voltage level, and power rail region PR2 adjacent to active areas AR2 and AR3 corresponds to a supply power rail configured to carry a supply voltage level. In embodiments where the active areas AR1 and AR4 are p-type, each of the adjacent power rail regions PR1 and PR3 corresponds to a power rail configured to carry a power voltage level, and the power rail region PR2 corresponds to a reference power rail configured to carry a reference voltage level.

Active area AR1 corresponds to the first total number of fins, active area AR2 corresponds to the second total number of fins, active area AR3 corresponds to the third total number of fins, and active area AR4 corresponds to the fourth total number of fins. Each of the first and second total number of fins is greater than each of the third and fourth total number of fins. Therefore, the total number of fins corresponding to the active areas AR1 and AR2 is larger than the total number of fins corresponding to the active areas AR3 and AR 4.

In various embodiments, the first and second total number of fins are the same total number of fins or different total number of fins. In various embodiments, the third and fourth total number of fins are the same total number of fins or different total numbers of fins. In some embodiments, each of the first total number of fins and the second total number of fins is greater than or equal to three, and each of the third total number of fins and the fourth total number of fins is less than three. In some embodiments, one or both of the first total number of fins or the second total number of fins is equal to three or four. In some embodiments, one or both of the third total number of fins or the fourth total number of fins is equal to one or two.

In some embodiments, the width of the active area, e.g., active areas AR1-AR4, varies according to the total number of fins corresponding to the active area. In the embodiment shown in fig. 2, active areas AR1 and AR2 have the same total number of fins, e.g., three fins, with active area AR1 having a height in the Y direction of AH1 and active area AR2 having a height in the Y direction of AH2, equal to height AH 1. Active areas AR3 and AR4 have the same total number of fins, e.g., two fins, active area AR3 has a height AH3 in the Y direction, while active area AR4 has a height AH4 in the Y direction equal to height AH 3. In various embodiments, height AH2 is not equal to height AH1 and/or height AH4 is not equal to height AH 3.

In the embodiment shown in fig. 2, heights AH1 and AH2 are greater than heights AH3 and AH4, according to each of active areas AR1 and AR2 corresponding to a greater total number of fins than a total number of fins corresponding to each active area AR3 and AR 4. In various embodiments, active regions corresponding to the same total number of fins have different heights and/or active regions corresponding to different total numbers of fins have the same height.

In the embodiment shown in fig. 2, adjacent active areas AR1 and AR2 are spaced apart by a distance D1, and adjacent active areas AR3 and AR4 are spaced apart by a distance D2. Corresponding to heights AH3 and AH4 being less than heights AH1 and AH2, distance D2 is greater than distance D1. In various embodiments, the distances between adjacent pairs of active regions having different heights are the same and/or the distances between adjacent pairs of active regions having the same height are different from each other.

Two active regions are considered to be adjacent based on no other active region being located between the two active regions, regardless of another IC layout component located between the two active regions. In the embodiment shown in fig. 2, active areas AR1 and AR2 are adjacent to each other, active areas AR2 and AR3 are adjacent to each other, and active areas AR3 and AR4 are adjacent to each other.

In the embodiment shown in fig. 2, each active region AR1-AR4 extends in the X-direction between gate regions GR1 and GR 3. In various embodiments, one or more active regions AR1-AR4 extend between the gate region GR2 and one of the gate regions GR1 or GR3 and/or extend beyond the boundary 200B in the X-direction, e.g., into a cell (not shown) adjacent to the cell 200C.

The tracks T1-T3 are spaced apart in the Y direction based on the pitch TP such that tracks T1 and T2 are spaced apart by a distance equal to the pitch TP and tracks T2 and T3 are spaced apart by a distance equal to the pitch TP. The pitch TP corresponds to the standard cell height and, in some embodiments, is referred to as the standard cell height TP. Height CH thus corresponds to a distance equal to twice pitch TP, and in some embodiments, cell 200C is referred to as a double-height cell having cell height CH.

In the embodiment shown in FIG. 2, the power rail regions PR1-PR3 overlap the cell 200C such that the cell 200C is considered to include a portion of each of the power rail regions PR1-PR 3. In some embodiments, some or all of the power rail regions PR1-PR3 are not considered to be included in cell 200C and are aligned with respect to cell 200C based on traces T1-T3.

In the embodiment shown in fig. 2, the entirety (not labeled) of the widths of the gate regions GR1 and GR3 in the X direction overlaps the cell 200C within the boundary 200B. In various embodiments, part or all of the width of one or both of the gate regions GR1 and GR3 is located outside of the boundary 200B so as not to overlap the cell 200C. In various embodiments, one or more gate regions GR1-GR3 are part of a gate region shared with one or more cells (not shown) other than cell 200C.

In the embodiment shown in FIG. 2, a total of three gate regions GR1-GR3 overlap cell 200C. In various embodiments, less or more than three gate regions in total overlap cell 200C.

In the embodiment shown in fig. 2, the cut polysilicon region CP is aligned with the trace T2, intersects the gate region GR2 between the active regions AR2 and AR3, and does not intersect either of the gate regions GR1 or GR 3. In various embodiments, the cut polysilicon region CP is not aligned with the trace T2 and intersects the gate region GR2 between the active regions AR2 and AR3, intersects the gate region GR2 between the active regions AR1 and AR2, or intersects the gate region GR2 between the active regions AR3 and AR 4. In various embodiments, the cut polysilicon region CP intersects one or both of the gate regions GR1 or GR3, does not intersect the gate region GR2, and/or extends beyond the boundary 200B outside of the cell 200C.

In the embodiment shown in fig. 2, IC layout 200 includes a single cut polysilicon region CP. In some embodiments, IC layout 200 does not include cut polysilicon regions CP. In various embodiments, IC layout 200 includes one or more instances of cut polysilicon region CP (not shown in fig. 2) in addition to the instance of cut polysilicon region CP depicted in fig. 2.

Thus, one or more instances of the cut polysilicon region CP at least partially define discontinuities in the gate structure corresponding to the gate regions, e.g., gate regions GR1-GR3, such that the circuit portions or blocks located in block region BL1 are electrically isolated from the circuit portions located in block region BL 2. Thus, the electrically isolated circuit portions can be independently electrically connected to other circuit portions of the same circuit or to one or more separate circuits. Thus, circuit portions in the block regions BL1 and BL2 corresponding to one or more gate regions intersecting one or more instances of the uncut polysilicon region CP are electrically connected to each other through the one or more gate regions.

In operation 110, a first active region is positioned in a cell of the IC layout, the first active region corresponding to a first total number of fins and being of a first type that is either n-type or p-type. Positioning the first active region in the cell includes positioning the first active region to extend in a first direction and to have a first height in a second direction perpendicular to the first direction. In some embodiments, the first active region having the first height comprises the first active region having the first height corresponding to a total number of the first fins.

The first active region corresponding to the first total number of fins includes the first total number of fins greater than a threshold number of fins. In various embodiments, the threshold fin number is equal to one, two, or three fins. In some embodiments, the first active region corresponding to the first total number of fins includes the first total number of fins equal to three or four.

In some embodiments, positioning the first active region in the cell includes positioning the first active region in a first region of a double height cell, the first region corresponding to a standard cell height, and the double height cell being twice the standard cell height. In some embodiments, positioning the first active area in a cell of the IC layout includes positioning active area AR1 in block area BL1 of double height cell 200C in IC layout 200.

In operation 120, a second active region is positioned in the cell adjacent to the first active region, the second active region being of a second type, n-type or p-type, and corresponding to a second total number of fins. Positioning the second active region in the cell includes positioning the second active region to extend in the first direction and to have a second height in the second direction. In some embodiments, the second active region having the second height comprises the second active region having the second height corresponding to the total number of second fins.

The second active region corresponding to the second total number of fins includes the second total number of fins greater than a threshold number of fins. In some embodiments, the second active area corresponding to the second total number of fins includes the second total number of fins equal to the first total number of fins. In some embodiments, the second active region corresponding to the second total number of fins includes the second total number of fins equal to three or four.

In some embodiments, positioning the second active region in the cell comprises positioning the second active region in a double height cell. In some embodiments, positioning the second active region adjacent to the first active region in the cell comprises: the first and second active areas are positioned between the same two of the total three traces, the same two traces corresponding to standard height cells and the three traces corresponding to double height cells.

In some embodiments, positioning the second active area adjacent to the first active area in the cell includes positioning an active area AR2 adjacent to active area AR1 in a block area BL1 of a double height cell 200C of IC layout diagram 200.

In operation 130, a third active region is positioned in the cell adjacent to the second active region, the third active region being of a second type, n-type or p-type, and corresponding to a third total number of fins. Positioning the third active area in the cell includes positioning the third active area to extend in the first direction and to have a third height in the second direction. In some embodiments, the third active region having the third height comprises the third active region having the third height corresponding to the total number of third fins.

The third active region corresponding to the third total number of fins includes the third total number of fins less than or equal to the threshold number of fins. In some embodiments, the third active region corresponding to the third total number of fins includes the third total number of fins equal to one or two.

In some embodiments, positioning the third active region in the cell includes positioning the third active region in a double height cell. In some embodiments, positioning the third active region adjacent to the second active region in the cell comprises: the second active area is positioned between the first two tracks corresponding to the standard height cell out of the total three tracks corresponding to the double height cell, and the third active area is positioned between the last two tracks out of the total three tracks, the last two tracks also corresponding to the standard height cell.

In some embodiments, positioning the third active region adjacent the second active region in the cell includes bridging the power supply trace with the second and third active regions. In various embodiments, either the power supply rail corresponds to the reference power supply rail and the second type is n-type, or the power supply rail corresponds to the supply power supply rail and the second type is p-type.

In some embodiments, positioning the third active region adjacent to the second active region in the cell comprises positioning active region AR3 in block region BL2 adjacent to active region AR2 in block region BL1 in cell 200C of IC layout 200.

In operation 140, a fourth active area is positioned in the cell adjacent to the third active area, the fourth active area being of the first type, n-type or p-type, and corresponding to a fourth total number of fins. Positioning the fourth active area in the cell includes positioning the fourth active area to extend in the first direction and to have a fourth height in the second direction. In some embodiments, the fourth active area having a fourth height comprises the fourth active area having a fourth height corresponding to the fourth total number of fins.

The fourth active area corresponding to the fourth total number of fins includes the fourth total number of fins less than or equal to the threshold number of fins. In some embodiments, the fourth active area corresponding to the fourth total number of fins includes the fourth total number of fins equal to the fourth total number of fins. In some embodiments, the fourth active area corresponding to the total number of fourth fins includes the total number of fourth fins equal to one or two.

In some embodiments, positioning the fourth active area in a cell includes positioning the fourth active area in a double height cell. In some embodiments, positioning the fourth active region adjacent to the third active region in the cell comprises: the third and fourth active areas are positioned between the same last two tracks of the total of three tracks corresponding to double-height cells.

In some embodiments, positioning the fourth active region adjacent to the third active region in the cell comprises positioning active region AR4 in block region BL2 adjacent to active region AR3 in block region BL2 in cell 200C of IC layout 200.

In operation 150, in some embodiments, each of the first to fourth active regions is intersected by a gate region. Intersecting each of the first through fourth active regions with the gate region includes at least partially defining at least one location of a transistor formed based on an IC layout (e.g., IC layout 200). In some embodiments, intersecting each of the first through fourth active regions with the gate region includes at least partially defining a location in a plurality of block regions (e.g., block regions BL1 and BL2) of a plurality of transistors formed based on the IC layout, the plurality of transistors including at least one transistor having a total number of first or second fins and at least one transistor having a total number of third or fourth fins. In some embodiments, intersecting each of the first through fourth active regions with the gate region includes at least partially defining locations of a plurality of transistors including at least one transistor having each of the first, second, third, and fourth total numbers of fins. In some embodiments, intersecting each of the first through fourth active regions with the gate region includes at least one location that at least partially defines a dummy gate.

In some embodiments, intersecting each of the first through fourth active regions with the gate region is part of intersecting one or more of the first through fourth active regions with more than one of the plurality of gate regions. In some embodiments, intersecting each of the first through fourth active regions with a gate region includes intersecting each of the active regions AR1-AR4 with at least one of the gate regions GR1-GR3 in the IC layout diagram 200.

In operation 160, in some embodiments, the gate region is intersected by the cut polysilicon region. Intersecting the gate region with the cut polysilicon region is a portion of a location defining a discontinuity in a gate electrode fabricated based on the gate region such that the corresponding gate electrodes are divided into portions that are electrically isolated from each other.

In various embodiments, intersecting the gate region with the cut polysilicon region is a portion of intersecting one or more of the plurality of gate regions with one or more of the plurality of cut polysilicon regions.

In some embodiments, intersecting the gate region with the cut polysilicon region includes intersecting the gate region GR2 with the cut polysilicon region CP in the IC layout 200.

In operation 170, in some embodiments, an IC map is generated and stored in a memory device. Generating the IC layout is performed by a processor, such as the processor 802 of the IC layout generation system 800 discussed below with reference to fig. 8.

In some embodiments, generating the IC layout comprises: one or more components (not shown), for example, contacts, vias, or conductive regions, are positioned corresponding to one or more IC structures fabricated on the basis of the one or more components and configured to provide electrical connections to one or more active regions corresponding to active regions AR1-AR4 and/or gate electrodes corresponding to gate regions GR1-GR 3.

In various embodiments, storing the IC layout in the storage device includes storing the IC layout in a non-volatile computer-readable memory or a cell library, such as a database, and/or includes storing the IC layout over a network. In various embodiments, storing the IC layout in the memory device includes storing the IC layout in a cell library 807 of the IC layout generation system 800 and/or via a network 814, discussed below with respect to FIG. 8.

In various embodiments, generating and storing an IC layout includes generating and storing one or more of IC layout 200 discussed above with respect to fig. 2 or

IC layout

400C, 400E, or 400G discussed below with respect to fig. 4A-4I.

In operation 180, in some embodiments, at least one of the one or more semiconductor masks or at least one component in a layer of the semiconductor IC is fabricated based on the IC layout. Fabricating one or more semiconductor masks or at least one component of a layer of a semiconductor IC is discussed below with respect to IC fabrication system 900 and fig. 9.

In various embodiments, fabricating one or more semiconductor masks or at least one component of a layer of a semiconductor IC is based on one or more of IC layout 200 discussed above with respect to fig. 2 or

IC layout

400C, 400E, or 400G discussed below with respect to fig. 4A-4I.

In operation 190, in some embodiments, one or more manufacturing operations are performed based on the IC layout. In some embodiments, performing the one or more manufacturing operations includes performing one or more lithographic exposures based on the IC layout. Performing one or more manufacturing operations, such as one or more lithographic exposures, based on the IC layout is discussed below with reference to fig. 9.

In various embodiments, performing one or more manufacturing operations is based on one or more of IC layout 200 discussed above with respect to fig. 2 or

IC layout

400C, 400E, or 400G discussed below with respect to fig. 4A-4I.

By performing some or all of the operations of method 100, an IC layout, such as IC layout 200, is generated in which a set of transistors is defined having a subset including relatively higher and lower fin counts, such that a circuit corresponding to the IC layout includes transistors having a combination of fin counts. Since power and drive capability and speed increase with increasing fin count, defining a set of transistors with a combination of fin counts enables the selective application of a relatively high fin count to circuit blocks where timing is most critical to overall circuit speed targets. Thus, circuit power can be reduced while maintaining speed and area requirements, as compared to methods in which the circuit corresponds to an IC layout that does not include relatively high and low fin counts.

FIG. 3 is a flow diagram of a method 300 of operating an IC manufacturing system according to some embodiments. In some embodiments, operating the IC manufacturing system includes generating an IC layout, such as IC layout 200 discussed above with respect to fig. 1 and 2 or

IC layout

400C, 400E, or 400G discussed below with respect to fig. 4A-4I, that corresponds to an IC structure manufactured based on the generated IC layout, such as IC device 700 discussed below with respect to fig. 7.

In some embodiments, some or all of method 300 is performed by a processor of a computer. In some embodiments, some or all of method 300 is performed by processor 802 of IC layout generation system 800 discussed below with reference to fig. 8.

Some or all of the operations of method 300 can be performed as part of a design process performed in a design room (e.g., design room 920 discussed below with reference to fig. 9).

In some embodiments, the operations of method 300 are performed in the order depicted in fig. 3. In some embodiments, the operations of method 300 are performed simultaneously and/or in a different order than depicted in fig. 3. In some embodiments, one or more operations of method 300 are performed before, during, and/or after performing one or more operations.

Fig. 4A-6 illustrate non-limiting examples of the operation of method 300 according to some embodiments. 4A-4I illustrate non-limiting examples of flip-flop based circuits and include IC layout diagrams 400C, 400E, and 400G shown in FIG. 4C, FIG. 4E, and FIG. 4G, respectively. Fig. 4A is a schematic diagram of a flip-flop circuit corresponding to performance of operation 310, fig. 4B and 4C are schematic layout diagrams corresponding to a first non-limiting example of performing some or all of

operations

312 and 340 on the flip-flop circuit, respectively, fig. 4D and 4E are schematic layout diagrams corresponding to a second non-limiting example of performing some or all of

operations

312 and 340 on the flip-flop circuit, respectively, and fig. 4F and 4G are schematic layout diagrams corresponding to a third non-limiting example of performing some or all of

operations

312 and 340 on the flip-flop circuit, respectively. Fig. 4H and 4I illustrate operating parameters corresponding to the non-limiting example of fig. 4A-4G.

As discussed further below, fig. 5 shows a non-limiting example based on performing some or all of

operations

310 and 340 on adder circuitry, and fig. 6 shows a non-limiting example based on performing some or all of

operations

310 and 340 on Multiplexer (MUX) circuitry.

Each of IC layout diagrams 400C, 400E, and 400G is an embodiment of IC layout diagram 200 discussed above with respect to fig. 1 and 2, and is simplified for clarity. In various embodiments, one or more of

IC layouts

400C, 400E, or 400G includes components other than those shown in fig. 4C, 4E, and 4G, such as one or more transistor elements, power rails, isolation structures, wells, conductive elements, and the like. Each of fig. 4C, 4E, and 4G also shows the X and Y directions discussed above with respect to fig. 2.

In operation 310, a first chunk of circuitry is assigned to a first number of fins. The circuit includes a plurality of PMOS and NMOS transistors, and assigning the first group of blocks to the first fin count includes assigning at least one circuit block including at least one PMOS transistor and at least one NMOS transistor. The first number of fins is a sum of a first total number of fins corresponding to one of the at least one PMOS transistor or the at least one NMOS transistor and a second total number of fins corresponding to the other of the at least one PMOS transistor or the at least one NMOS transistor. In some embodiments, the circuit includes some or all of a plurality of PMOS and NMOS transistors configured as transistor pairs, such as inverters and/or transmission gates.

In some embodiments, assigning the first chunk to the first number of fins includes the first number of fins being greater than or equal to six. In various embodiments, assigning the first set of blocks to the first number of fins includes the first total number of fins being equal to the second total number of fins or the first total number of fins being different from the second total number of fins. In various embodiments, assigning the first chunk to the first number of fins includes one or both of the first or second total number of fins being equal to three or four. In some embodiments, assigning the first set of blocks to the first number of fins includes assigning the first set of blocks to block region BL1, which includes active area AR1 corresponding to the first total number of fins and active area AR2 corresponding to the second total number of fins, as discussed above with respect to fig. 1 and 2.

In some embodiments, assigning the first set of blocks to the first number of fins includes receiving IC layout cells from a cell library. In some embodiments, receiving an IC layout cell from a cell library includes receiving a plurality of PMOS and NMOS transistors pre-assigned to a second number of fins lower than the first number of fins. In some embodiments, assigning the first set of blocks to the first number of fins includes assigning the remaining second set of blocks to the second number of fins. In some embodiments, assigning the first set of blocks to the first number of fins includes receiving block assignments, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8).

In various embodiments, the circuit block includes an equal number of PMOS and NMOS transistors, more PMOS transistors than NMOS transistors, or more NMOS transistors than PMOS transistors.

In some embodiments, assigning the first set of blocks to the first number of fins includes analyzing (e.g., applying an algorithm to) the circuit to divide the circuit into blocks. Analyzing the circuit includes applying a set of criteria to the circuit, i.e., total number of transistors, block definitions or signal paths, logic gates, control portions, branches, or other functional arrangements, based on one or more circuit dimensions. Non-limiting examples of analyzing a circuit to divide the circuit into blocks are discussed below with respect to flip-flop circuit 400A and FIG. 4.

In various embodiments, applying the criteria based on circuit size includes using functional capabilities to determine a total number of transistors to be considered for inclusion in the circuit. In various embodiments, functional capabilities include performing one or more logical or mathematical functions, signal processing, timing, generating, selecting, level shifting, delaying, or responding functions, and/or one or more other suitable IC functions. Non-limiting examples of circuits having sizes based on functional capabilities include latches, flip-flops (e.g., flip-flop circuit 400A), addition circuits (e.g., adder circuit 500), selection circuits (e.g., MUX 600), level shifters, drivers, oscillators, voltage references, amplifiers, memory cells, and so forth.

In some embodiments, the total number of transistors increases as the functional capability increases. In some embodiments, determining the total number of transistors of the circuit includes a total number of transistors ranging from four to over 100. In some embodiments, determining the total number of transistors of the circuit includes a total number of transistors ranging from 16 to 96. In some embodiments, determining the total number of transistors of the circuit includes a total number of transistors ranging from 32 to 64.

In various embodiments, defining application criteria based on blocks includes identifying transistors arranged to implement particular circuit functions or sub-functions, e.g., propagating, blocking, inverting, isolating, and/or delaying signals or enabling or disabling, e.g., powering up or powering down some or all of the circuits. In some embodiments, the identification transistor comprises an identification PMOS and NMOS transistor pair.

In some embodiments, identifying the transistors includes identifying a number of transistors based on the target block size. In some embodiments, the target block size is based on the minimum number of transistors needed to implement a particular circuit function or sub-function, e.g., at least four transistors are needed to implement a tri-state inverter or two transistors are needed to implement a transmission gate. In some embodiments, the target block size is based on layout considerations, e.g., two transistors targeted to achieve maximum layout flexibility in a double-height cell.

In various embodiments, applying the criteria based on the signal path includes identifying transistors included in a particular signal path (e.g., one of a plurality of signal paths) and/or included in one or more predetermined portions of the particular signal path (e.g., time-critical locations and/or feedback segments). In various embodiments, identifying the transistors included in a particular signal path includes identifying a PMOS transistor, an NMOS transistor, or a pair of PMOS and NMOS transistors.

In various embodiments, the application criteria based on the inclusion of logic gates includes identifying transistors arranged to perform a particular logic function OR sub-function, such as some OR all of the OR other logic gates arranged as inverters, ANDs, ORs, NANDs, NOR, XOR.

In various embodiments, the inclusion of application criteria based on the control portion includes identifying transistors arranged to perform a particular circuit control function, e.g., selectively enabling some or all of the circuits in response to one or more enable, control or other signals.

In various embodiments, the branch-based inclusion criteria includes identifying a transistor disposed within a particular portion of the circuit (e.g., one of a plurality of selectable input paths).

In some embodiments, assigning the first set of blocks to the first fin number includes receiving block partitioning information, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8).

In some embodiments, assigning the first set of blocks to the first number of fins includes performing timing analysis on some or all of the circuits, e.g., identifying one or more critical high speed signal paths. In some embodiments, performing the timing analysis includes assigning a timing criticality level to each circuit portion, e.g., a plurality of signal paths. In various embodiments, assigning the first set of blocks to the first number of fins includes applying a timing analysis to determine that a particular block is included in the first set of blocks, e.g., included or excluded based on the block being part of a particular signal path.

In various embodiments, the timing analysis is performed after dividing the circuit into blocks, the circuit is divided into blocks after performing the timing analysis, or the timing analysis and the circuit block division are combined or iterated. In some embodiments, performing the timing analysis includes receiving timing information, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8).

In various embodiments, performing the timing analysis includes analyzing the timing of the one or more transistors based on one or both of the first or second total number of fins. In various embodiments, performing the timing analysis includes analyzing the timing of the one or more transistors based on a number of fins other than the total number of first and second fins. In some embodiments, performing the timing analysis includes calculating one or more switching speeds of one or more transistors.

In some embodiments, assigning the first chunk to the first number of fins includes assigning the first chunk based on a timing analysis independent of the circuit, e.g., based on a non-critical indication of circuit speed in the timing information.

In some embodiments, assigning the first chunk to the first fin count includes performing a power analysis on some or all of the circuitry, e.g., identifying one or more critical high power circuit portions. In some embodiments, performing the timing analysis includes assigning power criticality levels to various circuit portions, such as multiple signal paths. In various embodiments, assigning the first set of blocks to the first number of fins includes applying a power analysis to determine that a particular block is included in the first set of blocks, e.g., included or excluded based on the block being part of a particular signal path.

In various embodiments, the power analysis is performed after dividing the circuit into blocks, the circuit is divided into blocks after performing the power analysis, or the power analysis and the circuit block division are combined or iterated.

In various embodiments, some or all of the power analysis is performed and/or applied in conjunction with performing and/or applying some or all of the timing analysis. In various embodiments, some or all of the power analysis is performed and/or applied and/or some or all of the timing analysis is performed and/or applied to determine the block priority such that the blocks are included or excluded from the first set of blocks based on the block priority (in some embodiments, in combination with other factors (e.g., area efficiency levels as described below)).

In some embodiments, assigning the first chunk to the first number of fins includes calculating a power level of the first chunk based on the first number of fins. The power level, e.g., of the first set of blocks, is calculated to include a power level that varies with respect to the number of fins (e.g., the first number of fins) such that the power level increases as the value of the number of fins increases.

In various embodiments, calculating the power level includes executing a set of software instructions, such as a circuit or device simulation program, to calculate one or more of a Direct Current (DC) and/or Alternating Current (AC) on-state current level, one or more off-state leakage levels, and/or another circuit parameter related to circuit power based on the power information (e.g., one or more operating voltage levels, frequencies, and/or temperatures). In some embodiments, calculating the power level includes calculating the power level based on the proximity of individual transistors, blocks, or other components within the circuit layout and/or one or more additional factors related to the circuit. In some embodiments, calculating the power level includes the power level being based on the circuit layout, e.g., as a result of performing operation 340 discussed below.

In some embodiments, calculating the power level of the first chunk includes receiving power information, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8).

In some embodiments, assigning the first set of blocks to the first number of fins includes adding and/or removing at least one block from an existing first set of blocks, e.g., in response to performing one or more of

operations

312, 322, or 332 discussed below.

In operation 312, in some embodiments, a speed level V of the circuit is calculated based on assigning the first set of blocks to the first number of fins, and the speed level V is compared to a threshold speed level Vth. In various embodiments, calculating the speed level V includes executing a set of software instructions, such as a circuit or device simulation program, to calculate one or more of transistor switching speed, circuit block setup time, frequency response, bandwidth, and/or another circuit parameter related to transistor speed.

Calculating the velocity level V based on assigning the first chunk to the first number of fins includes a velocity level V that varies with respect to one or both of the first or second total number of fins for the first number of fins such that the velocity level V increases with respect to increasing first fin values. The velocity level V, which varies relative to one or both of the first or second total number of fins, corresponds to a velocity level V based on one of the at least one PMOS transistor or the at least one NMOS transistor corresponding to the first total number of fins and/or the other of the at least one PMOS transistor or the at least one NMOS transistor corresponding to the second total number of fins.

In various embodiments, calculating the speed level V includes calculating the speed level V based on all or a subset of the first set of blocks, a subset of transistors within a given block, a hierarchical ordering of the blocks or transistors within a given block, a proximity of individual transistors, blocks, or other components within the circuit layout, and/or one or more additional factors related to circuit speed.

In various embodiments, calculating speed level V includes calculating speed level V based on all, some, or none of the circuit blocks not in the first set of blocks, e.g., the second set of blocks pre-allocated or allocated to the second number of fins, e.g., as a result of performing operation 320 as discussed below. In some embodiments, calculating velocity level V includes velocity level V being based on a circuit layout, e.g., as a result of performing operation 340 discussed below.

In various embodiments, calculating the velocity level V includes summing, algebraically combining, and/or identifying the slowest velocity or velocities corresponding to the various blocks of the first and/or second set of blocks.

In some embodiments, comparing the speed level V to the threshold speed level Vth includes the threshold speed level Vth being based on a performance specification of an application of the circuit. In some embodiments, comparing the speed level V to the threshold speed level Vth includes receiving the threshold speed level Vth, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8).

In some embodiments, operation 314 is performed based on the speed level V being equal to or greater than the threshold speed level Vth, and operation 320 is performed based on the speed level V being less than the threshold speed level Vth.

In operation 314, in some embodiments, one or more additional circuit blocks are assigned to the first fin count by returning to operation 310 based on the speed level V being below the threshold speed level Vth. In various embodiments, assigning one or more additional circuit blocks to the first fin count is based on applying a previously determined block priority, performing further timing analysis, and/or receiving assignment information, e.g., from a database or user interface (such as user interface 842 discussed below with respect to fig. 8).

In operation 320, in some embodiments, a second chunk of circuitry is allocated to a second number of fins lower than the first number of fins. Assigning the second group of blocks to the second fin count includes assigning at least one circuit block including at least one PMOS transistor and at least one NMOS transistor. The second number of fins is a sum of a third total number of fins corresponding to one of the at least one PMOS transistor or the at least one NMOS transistor and a fourth total number of fins corresponding to the other of the at least one PMOS transistor or the at least one NMOS transistor.

In some embodiments, assigning the second chunk to the second number of fins includes the second number of fins being less than or equal to four. In various embodiments, assigning the second set of blocks to the second number of fins includes the third total number of fins being equal to the fourth total number of fins or the third total number of fins being different from the fourth total number of fins. In various embodiments, assigning the second chunk to the second number of fins includes one or both of the third or fourth total number of fins equal to one or two. In some embodiments, assigning the second set of blocks to the second number of fins includes assigning the second set of blocks to block region BL2, which includes active area AR3 corresponding to the third total number of fins and active area AR4 corresponding to the fourth total number of fins, as discussed above with respect to fig. 1 and 2.

In some embodiments, assigning the second chunk to the second number of fins includes receiving the second chunk pre-assigned to the second number of fins, e.g., from a cell bank. In some embodiments, assigning the second chunk to the second fin count includes receiving a chunk assignment, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8).

In some embodiments, assigning the second set of blocks to the second number of fins includes identifying one or more blocks based on a timing analysis (e.g., the timing analysis performed in operation 310). In some embodiments, assigning the second set of blocks to the second number of fins includes assigning one or more blocks based on one or more block functions (e.g., bias, power on/off, or sleep mode functions) independent of one or more operational activities of the circuit.

In some embodiments, assigning the second chunk to the second number of fins includes calculating a power level for the second chunk based on the second number of fins, as discussed above with respect to operation 310. In some embodiments, calculating the power level of the second chunk includes calculating the power level of the first chunk based on the first number of fins.

In various embodiments, calculating the power level for the second chunk includes receiving power information, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8). In some embodiments, allocating the first set of blocks to the first number of fins in operation 310 and the second set of blocks to the second number of fins in operation 320 includes allocating the first and second sets of blocks independently of calculating power levels of the first and second sets of blocks, e.g., based on a non-critical indication of circuit power in the power information.

In operation 322, in some embodiments, the circuit power level P is calculated as the sum of the power level of the first chunk based on the first number of fins and the power level of the second chunk based on the first number of fins, and the circuit power level P is compared to a threshold power level Pth. Calculating the power level of the first chunk based on the first number of fins and the power level of the second chunk based on the second number of fins is discussed above with respect to

operations

310 and 320.

In some embodiments, comparing power level P to threshold power level Pth includes threshold power level Pth being based on a performance specification of an application of the circuit (e.g., a power budget for the entire circuit design). In some embodiments, comparing power level P to threshold power level Pth includes receiving threshold power level Pth, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8).

In some embodiments, operation 324 is performed based on power level P being equal to or below threshold power level Pth, and operation 330 is performed based on power level P exceeding threshold power level Pth.

In operation 324, in some embodiments, the blocks in the first set of blocks are reassigned to the second number of fins based on the circuit power level P exceeding the threshold power level Pth. In various embodiments, reassigning the blocks in the first set of blocks to the second number of fins includes one of the

return operations

310 or 320. In various embodiments, assigning blocks to the second fin number is based on applying previously determined block priorities, performing further timing analysis, and/or receiving assignment information, e.g., from a database or user interface (such as user interface 842 discussed below with respect to fig. 8).

In operation 330, in some embodiments, the area efficiency level EL is calculated based on the first chunk being assigned to the first number of fins and the second chunk being assigned to the second number of fins. In some embodiments, calculating the efficiency level EL includes calculating an efficiency ratio based on a total number of transistors X in the first block and a total number of transistors Y in the second block. In some embodiments, the efficiency level EL is given by:

EL＝(X+Y)/(2 x max(X,Y)) (1)

making the maximum value of the efficiency level EL equal to 1 corresponds to the total number of transistors X being equal to the total number of transistors Y.

In various embodiments, the efficiency level EL is equal to one of the ratios X/Y or Y/X such that the total number of transistors X is equal to the total number of transistors Y corresponding to a value of the efficiency level EL equal to 1.

In operation 332, in some embodiments, the area efficiency level EL is compared to an area efficiency limit. In various embodiments, comparing the area efficiency level EL to the area efficiency limit includes the area efficiency limit being a value greater than and/or less than 1. In some embodiments, comparing the area efficiency level EL to the area efficiency limit comprises the area efficiency limit being 0.7 and/or 1.3.

In some embodiments, comparing the area efficiency level EL to the area efficiency limit comprises comparing the area efficiency level EL to a predetermined manufacturing limit. In some embodiments, comparing the area efficiency level EL to the area efficiency limit includes receiving the area efficiency limit, for example, from a database or a user interface (such as user interface 842 discussed below with respect to fig. 8).

In some embodiments, operation 334 is performed based on the area efficiency level EL being outside the area efficiency limit, and operation 340 is performed based on the area efficiency level EL being equal to or within the area efficiency limit.

In operation 334, in some embodiments, the fin count allocation is rebalanced by at least one of reallocating blocks in the second set of blocks to the first number of fins or reallocating blocks in the first set of blocks to the second number of fins based on the area efficiency level EL being outside the area efficiency limit. In various embodiments, rebalancing the fin count assignment includes one of the

return operations

310 or 330. In various embodiments, rebalancing fin count assignments are based on applying previously determined block priorities, performing further timing analysis, and/or receiving assignment information, e.g., from a database or user interface (such as user interface 842 discussed below with respect to fig. 8).

In operation 340, first and second chunks are arranged based on the respective first and second fin numbers. Arranging the first set of blocks includes using first and second active regions of a first block region of the IC layout cell, the first and second active regions collectively corresponding to a plurality of fins having a first number of fins. Arranging the second set of blocks includes using third and fourth active areas of the second block region of the IC layout cell, the third and fourth active areas collectively corresponding to a plurality of fins having a second number of fins.

In various embodiments, arranging the first and second tiles includes using first and fourth active regions corresponding to PMOS transistors and second and third active regions corresponding to NMOS transistors, or using first and fourth active regions corresponding to NMOS transistors and second and third active regions corresponding to PMOS transistors.

Arranging the first set of blocks in the first block region and the second set of blocks in the second block region includes determining a relative proximity of the respective blocks to each other. In some embodiments, arranging the first set of blocks in the first block region and arranging the second set of blocks in the second block region comprises selecting one of a plurality of possible arrangements such that the relative proximity of the respective blocks to each other is arbitrary.

In some embodiments, determining the relative proximity of the respective blocks to each other includes determining the relative proximity based on a set of one or more criteria. In various embodiments, the criteria include at least one of: circuit speed based on proximity of a given block to another block or external circuit, power dissipation of a given block relative to power dissipation of one or more adjacent components, ease of routing between blocks and/or to external circuits, or design considerations such as minimizing the number of cut polysilicon regions, etc.

In various embodiments, arranging the first and second groups of blocks using the first through fourth active regions includes performing one or more of

operations

110 and 170 of the method 100 to generate the IC layout diagram 200 including the active regions AR1 and AR2 of the region BL1 and the active regions AR3 and AR4 of the block region BL2 of the block cell 200C, as discussed above with respect to fig. 1 and 2.

In various embodiments, the arranging of the first and second chunks using the first through fourth active regions includes arranging chunks a-J using active regions AR1-AR4 of cells 400CC, 400EC, and 400GC, as discussed below with respect to fig. 4C, 4E, and 4G.

In some embodiments, arranging the first and second blocks includes performing one or more of

operations

170 and 190 of the method 100, e.g., to store the IC layout and/or to perform additional operations based on the IC layout, as discussed above with respect to fig. 1 and 2.

By performing some or all of the operations of method 300, an IC floorplan, such as one of

IC floorplans

200, 400C, 400E, or 400G, is generated in which circuit blocks are allocated such that transistors are distributed between relatively higher and lower fin counts, thereby achieving the benefits discussed above with respect to method 100 and IC floorplan 200, and as discussed further below with respect to fig. 4A-6.

In the non-limiting example shown in fig. 4A, flip-flop circuit 400A includes: an input terminal configured to receive control signals SI and SE, data DI, and a clock signal CP; a power supply node configured to receive a supply voltage level VDD and a reference voltage level VSS; and an output terminal configured to output the signal QO. The inverter is configured to generate the internal control signal seb from the control signal SE and to generate the internal clock signals clkb and clkbb from the clock signal CP.

Upon execution of operation 310, flip-flop circuit 400A is divided into ten blocks, as listed in table 1 and discussed below.

TABLE 1

By applying criteria based on the functional capabilities of the flip-flop circuit, i.e., outputting signal QO in response to control signals SI and SE, data DI, and clock signal CP, flip-flop circuit 400A includes a total of 32 transistors, arranged as 16 pairs of PMOS and NMOS transistors and configured as shown in fig. 4A.

The flip-flop circuit 400A is partially divided into blocks a and B by applying a criterion based on defining blocks by identifying transistors arranged as inverters and based on being included in a clock signal path, each block including a pair of transistors arranged as inverters in a path receiving the clock signal CP and sequentially inverted to generate internal clock signals clkb and clkbb.

By applying a method based on defining blocks by identifying transistors arranged as inverters and on criteria included in the selection control section, the flip-flop circuit 400A is further divided into blocks C comprising transistor pairs arranged as inverters configured to generate an internal control signal seb which can be used together with the control signal SE for a selection function.

The flip-flop circuit 400A is further divided into blocks D including two PMOS and two NMOS transistors configured to perform a selection function in response to the control signals SE and SI and the internal control signal seb by applying a criterion based on further identifying a transistor included in the selection control part.

The flip-flop circuit 400A is further divided into blocks E including two PMOS transistors in the first segment E and two NMOS transistors in the second segment E', four transistors configured to selectively input the data DI in response to the control signal SE and the internal control signal seb, by applying a criterion that defines the blocks based on identifying the transistors arranged to perform the data input function.

The flip-flop circuit 400A is further divided into blocks F, including transistor pairs in a first segment F and two PMOS and two NMOS transistors in a second segment F', by applying criteria based on identifying the transistors included in the main latch feedback signal path, six transistors being configured to provide the main latch feedback signal path with timing controlled by the internal clock signals clkb and clkbb.

The flip-flop circuit 400A is further divided into blocks G, which include pairs of transistors arranged as inverters and included in the master latch forward signal path, by applying criteria based on defining the blocks by identifying the transistors arranged as inverters and based on identifying the transistors included in the master latch forward signal path.

By applying criteria based on identifying the transistors included in the slave latch feedback signal path, the flip-flop circuit 400A is further divided into blocks H comprising a pair of transistors arranged as transmission gates in a first segment H and two PMOS and two NMOS transistors in a second segment H', six transistors being configured to provide a slave latch feedback signal path having a timing controlled by the internal clock signals clkb and clkbb.

The flip-flop circuit 400A is further divided into blocks I, which include pairs of transistors arranged as inverters and included in the slave latch forward signal path, by applying criteria based on defining the blocks by identifying the transistors arranged as inverters and based on identifying the transistors included in the slave latch forward signal path.

The flip-flop circuit 400A is further divided into a block J including a pair of transistors arranged as an inverter configured to output the signal Q0 by applying a criterion based on defining the block by identifying the transistors arranged as an inverter and based on identifying the transistors included in the output buffer section.

Thus, as shown in fig. 4A, 4B, 4D, and 4F, the flip-flop circuit 400A is divided into blocks A, B, C, G, I and J including a single inverter, a block D including two PMOS transistors and two NMOS transistors, a block E including two PMOS transistors in the first segment E and two NMOS transistors in the second segment E ', a block F including an inverter in the first segment F and a gated inverter in the second segment F ', and a block H including a transmission gate in the first segment H and a gated inverter in the second segment H '.

In flip-flop circuit 400A, each of the master latch forward signal path, the master latch feedback signal path, and the slave latch feedback path is a critical high speed signal path, such that each of blocks F-H corresponds to a critical high speed signal path. Each of blocks F-H also corresponds to a higher power level relative to the power levels of circuit blocks a-E and J based on design criteria corresponding to operating frequency, data activity, and gate-related current levels and other parasitic capacitance levels.

By performing some or all of operations 310-334, the first and second blocks A-J of the flip-flop circuit 400A are assigned to a first number of fins FC1 or a second number of fins FC2 that is lower than the first number of fins FC1, respectively, such that speed and power requirements are resolved as needed, as shown in the non-limiting example discussed below.

In the embodiments shown in fig. 4B, 4D, and 4E, the flip-

flop circuits

400B, 400D, and 400F include: a first number of fins FC1 as a sum of a first total number of fins F1 corresponding to PMOS transistors and a second total number of fins F2 corresponding to NMOS transistors; and a second number of fins FC2 as a sum of a third total number of fins F3 corresponding to NMOS transistors and a fourth total number of fins F4 corresponding to PMOS transistors. In some embodiments, the first and fourth total number of fins F1 and F4 correspond to NMOS transistors and the second and third total number of fins F2 and F3 correspond to PMOS transistors.

In a first non-limiting example shown in fig. 4B, the flip-flop circuit 400A is configured as the flip-flop circuit 400B based on circuit speed being a non-critical requirement, corresponding to a situation where the circuit power level is minimized. Thus, each of blocks A, C, D, E, I and J is assigned to a first number of fins FC1 based on a low power level relative to blocks F-H, and each of blocks B, F, G and H is assigned to a second number of fins FC2 based on a relatively higher power level. Since circuit speed is not critical and power levels increase as the number of fins increases, the total power level of flip-flop circuit 400B is minimized by block allocation.

In various embodiments, assigning blocks A, C, D, E, I and J to the first number of fins FC1 and assigning blocks B, F, G and H to the second number of fins FC2 includes performing

operations

310 and 334 respectively, either in subset or in total. In some embodiments, blocks A, C, D, E, I and J are assigned to the first number of fins FC1 in operation 310, operation 312 is not performed, blocks B, F, G and H are assigned to the second number of fins FC2 in operation 320, the power level P is calculated and confirmed to be equal to or lower than the threshold power level Pth in operation 322, and the area efficiency level EL is calculated in operation 330.

In some embodiments, in operation 310, one or more blocks other than blocks A, C, D, E, I and J are assigned to the first number of fins FC1, the remaining blocks are assigned to the second number of fins FC2 in operation 320, the power level P is calculated and confirmed to exceed the threshold power level Pth in operation 322, and one or more of blocks A, C, D, E, I or J are reassigned to the first number of fins FC1 in operation 324.

In some embodiments, based on assigning blocks A, C, D, E, I and J to the first number of fins FC1 and assigning blocks B, F, G and H to the second number of fins FC2, the area efficiency level EL is calculated in operation 330 and confirmed to be at or within a predetermined limit based on each of the total number of transistors X and the total number of transistors Y being equal to 16.

In some embodiments, based on one or more blocks other than blocks A, C, D, E, I and J being assigned to the first fin number FC1 and one or more blocks other than blocks B, F, G and H being assigned to the second fin number FC2, the area efficiency level EL is calculated in operation 330 and determined to be outside of a predetermined limit based on a value other than the total number of transistors X and Y being equal to 16, and the block assignment is re-performed in operation 334.

In a second non-limiting example shown in fig. 4D, the flip-flop circuit 400A is configured as the flip-flop circuit 400D based on each of circuit speed and circuit power being critical requirements, corresponding to a situation where a tradeoff between circuit speed and power is achieved. Thus, each of blocks A and D-F is assigned to a first number of fins FC1 and each of blocks B, C and G-J is assigned to a second number of fins FC 2. Based on the relatively high power level and speed criticality of the blocks F assigned to the first number of fins FC1 and the blocks G and H assigned to the second number of fins FC2, the overall circuit speed and power level of the flip-flop circuit 400D is balanced by the block assignments.

Similar to the example discussed above with respect to fig. 4B, in various embodiments, assigning blocks a and D-F to the first number of fins FC1 and assigning blocks B, C and G-J to the second number of fins FC2 includes performing various subsets or all of operations 310-334.

For example, in some embodiments, one or more blocks other than blocks a and D-F are assigned to the first number of fins FC1 in operation 310, a velocity level V is calculated and determined to be below a threshold velocity level Vth in operation 312, and one or more of blocks B, C or G-J are reassigned to the first number of fins FC1 in operation 314.

In a third non-limiting example shown in fig. 4F, the flip-flop circuit 400A is configured as the flip-flop circuit 400F based on the fact that circuit power is a non-critical requirement, corresponding to the case where the circuit speed level is maximized. Thus, blocks A and F-H are each assigned to a first number of fins FC1 based on the relatively high speed criticality of the circuit block F-H, and blocks B-E, I and J are each assigned to a second number of fins FC2 based on the relatively low speed criticality. Since circuit power is not critical and speed levels increase as the number of fins increases, the total power level of flip-flop circuit 400F is maximized by block allocation.

Similar to the example discussed above with respect to fig. 4B and 4D, in various embodiments, assigning blocks a and F-H to the first number of fins FC1 and assigning blocks B-E, I and J to the second number of fins FC2 includes performing

operations

310 and 334, respectively, in various subsets or entireties.

Based on the configuration discussed above, flip-

flop circuits

400B, 400D, and 400F have relative circuit speeds and power levels, as shown in table 2 below.

Circuit arrangement	Speed of rotation	Power of
			400B	Slow	Is low in
4000D	Medium and high grade	Medium and high grade
			400F	Fast-acting toy	Height of

TABLE 2

As shown in table 2, based on the circuit block assignments, flip-flop circuit 400B has a lower speed level and a lower power level relative to flip-

flop circuits

400D and 400F, flip-flop circuit 400D has a medium speed and power level relative to flip-

flop circuits

400B and 400F, and flip-flop circuit 400F has a higher speed level and a higher power level relative to flip-

flop circuits

400B and 400D.

According to some embodiments, flip-

flop circuits

400B, 400D, and 400F are used to generate IC layout diagrams 400C, 400E, and 400G shown in fig. 4C, 4E, and 4G, respectively, based on the execution of operation 340. Each of the IC layout diagrams 400C, 400E, and 400G includes active regions AR1-AR4, gate regions GR1-GR3, and multiple instances of the cut polysilicon region CP (as discussed above with respect to fig. 1 and 2), and additional gate regions GR4-GR11 similar to gate regions GR1-GR 3. Active area AR1 corresponds to a first total number of fins F1, active area AR2 corresponds to a second total number of fins F2, active area AR3 corresponds to a third total number of fins F3, and active area AR4 corresponds to a fourth total number of fins F4.

IC layout 400C includes cell 400CC with boundary 400CB, IC layout 400E includes cell 400EC with boundary 400EB, and IC layout 400G includes cell 400GC with boundary 400 GB. Each of the cells 400CC, 400EC, and 400GC includes a plurality of instances of cut polysilicon CP arranged according to blocks a-J (which represent two instances of the block regions BL1 and BL2 discussed above with reference to fig. 1 and 2) and circuit blocks allocated according to the configuration of the respective flip-

flop circuits

400B, 400D, and 400F.

As shown in the non-limiting example of flip-

flop circuits

400B, 400D, and 400F and

corresponding IC layouts

400C, 400E, and 400G, the multiple circuit configurations produced by performing some or all of the operations of method 300 enable a trade-off between speed and power to be selected. In the options represented by flip-

flop circuits

400B, 400D, and 400F and

corresponding IC layouts

400C, 400E, and 400G, the total circuit area is not affected because each configuration includes a total number of transistors X equal to sixteen in the first set of blocks and a total number of transistors Y equal to sixteen in the second set of blocks. Each of the flip-

flop circuits

400B, 400D, and 400F and the corresponding

IC layouts

400C, 400E, and 400G thus corresponds to an area efficiency level EL equal to one when calculated according to the above-described embodiments.

Each of fig. 4H and 4I illustrates a comparison between a given one of the flip-

flop circuits

400B, 400D, or 400F corresponding to the

respective IC layouts

400C, 400E, and 400G and a flip-flop circuit configured other than by performing some or all of the operations of the method 300.

FIG. 4H shows normalized power as a function of data activity and includes curves 4H1-4H 3. A curve 4H1 represents a flip-flop circuit in which all transistors correspond to a first number of fins FC1, a curve 4H2 represents a given one of the flip-

flop circuits

400B, 400D, or 400F, and a curve 4H3 represents a flip-flop circuit in which all transistors correspond to a second number of fins FC 2. As shown in fig. 4H, a given one of the flip-

flop circuits

400B, 400D, or 400F has a power level P that is between the other power levels for the entire range of data activity levels.

FIG. 4I shows the timing characteristics (clock-Q versus setup time) and includes curves 4I1-4I 3. A curve 4I1 represents a flip-flop circuit in which all transistors correspond to a first number of fins FC1, a curve 4I2 represents a given one of the flip-

flop circuits

400B, 400D, or 400F, and a curve 4I3 represents a flip-flop circuit in which all transistors correspond to a second number of fins FC 2. As shown in fig. 4I, a given one of the flip-

flop circuits

400B, 400D, or 400F has a timing characteristic that is between the timing characteristics of the other flip-flop circuits.

As shown in the non-limiting examples shown in fig. 4H and 4I, a circuit configured by performing some or all of the operations of method 300 can have power and timing characteristics that are consistent with the power and timing characteristics of a circuit configured by not performing some or all of the operations of method 300, while achieving the advantages described above.

Fig. 5 and 6, discussed below, illustrate additional non-limiting examples of circuits configured by performing some or all of the operations of the method 300, and thus can have the benefits discussed above.

Fig. 5 illustrates an adder circuit 500 according to some embodiments, and fig. 6 illustrates a MUX circuit 600 according to some embodiments. Each of the adder circuit 500 and the MUX circuit 600 includes a power supply node configured to receive a supply voltage VDD and a reference voltage VSS, both discussed above with reference to fig. 4A.

The adder circuit 500 includes input terminals configured to receive signals B1, B2, and C1, and terminals configured to output signals S and CO. Based on the execution of operation 310, adder circuit 500 is divided into: a block K including five PMOS transistors and five NMOS transistors arranged as a first functional portion; a block L comprising a transistor pair arranged as an inverter; and a block M including eight PMOS transistors and five NMOS transistors arranged as the second functional portion.

Blocks K and L are assigned to the first number of fins FC1 and block M is assigned to the number of fins FC2 based on performing some or all of

operations

312 and 334 in the manner discussed above with respect to fig. 4B, 4D, and 4G. In the embodiment shown in fig. 5, adder circuit 500 includes: a first number of fins FC1 as a sum of a first total number of fins F1 corresponding to PMOS transistors and a second total number of fins F2 corresponding to NMOS transistors; and a second number of fins FC2 as a sum of a third total number of fins F3 corresponding to NMOS transistors and a fourth total number of fins F4 corresponding to PMOS transistors. In some embodiments, the first and fourth total number of fins F1 and F4 correspond to NMOS transistors and the second and third total number of fins F2 and F3 correspond to PMOS transistors.

The MUX circuit 600 includes input terminals configured to receive the signals I0-I3, S0, and S1, and a terminal configured to output the signal ZO. Based on the execution of operation 310, MUX circuit 600 is divided into: a block N including two transistor pairs arranged as inverters configured to generate an internal signal S0b based on the signal S0 and generate an internal signal S1b based on the signal S1; a block O comprising five PMOS transistors and five NMOS transistors arranged as two gated inverters and a transmission gate; a block Q comprising five PMOS transistors and five NMOS transistors arranged as two gated inverters and a transmission gate; and a block R including a transistor pair arranged as an inverter.

Blocks O and R are assigned to the first number of fins FC1 and blocks N and Q are assigned to the number of fins FC2 based on performing some or all of

operations

312 and 334 in the manner discussed above with respect to fig. 4B, 4D, and 4G. In the embodiment shown in fig. 6, the MUX circuit 600 includes: a first number of fins FC1 as a sum of a first total number of fins F1 corresponding to NMOS transistors and a second total number of fins F2 corresponding to PMOS transistors; and a second number of fins FC2 as a sum of a third total number of fins F3 corresponding to PMOS transistors and a fourth total number of fins F4 corresponding to NMOS transistors. In some embodiments, the first and fourth total number of fins F1 and F4 correspond to PMOS transistors and the second and third total number of fins F2 and F3 correspond to NMOS transistors.

Fig. 7 is a diagram of an IC device 700 according to some embodiments. The IC device 700 includes active areas AA1-AA4, gate structures G1-G3, power rails P1-P3, vias V1 and V2, and metal segment MS 1. The active areas AA1-AA4 correspond to the active areas AR1-AR4, the gate structures G1-G3 correspond to the gate areas GR1-GR3, and the power rails P1-P3 correspond to the power rail areas PR1-PR3, all discussed above with respect to the IC layout diagram 200 and fig. 1 and 2.

The depiction of the IC device 700 is simplified for illustrative purposes. In various embodiments, the IC device 700 includes additional components, such as contacts, S/D structures, additional vias and metal segments, isolation structures, and the like. In some embodiments, IC device 700 includes one or more active regions (not shown) in addition to active regions AA1-AA4 and one or more gate structures (not shown) in addition to gate structures G1-G3, e.g., according to the embodiments discussed above with respect to fig. 3-6.

According to the various embodiments discussed above with respect to IC layout diagrams 200, 400C, 400E, and 400G and FIGS. 1-6, each active area AA1-AA4 is either p-type or n-type, including first through fourth total number of fins F1-F4, and is adjacent to other active areas AA1-AA4 by corresponding to active areas AR1-AR 4. Thus, each of the active areas AA1 and AA4 is one of n-type or p-type, and each of the active areas AA2 and AA3 is the other of n-type or p-type.

Each of the gate structures G1-G4 is configured by corresponding to a gate region GR1-GR3 according to the various embodiments discussed above with respect to

IC layouts

200, 400C, 400E, and 400G and fig. 1-6.

Each of power rails P1-P3 includes one or more conductive segments and is configured as a reference power rail or a supply power rail. Each of vias V1 and V2 includes one or more conductive segments and is electrically connected to a respective one of power rails P1 or P3. Metal segment MS1 includes a conductive segment and is electrically connected to each of vias V1 and V2.

With the configuration shown in fig. 7, the IC device 700 includes power rails P1 and P3 electrically connected to each other and electrically isolated from power rail P2. In various embodiments, the IC device 700 includes power rails P1 and P3 that are otherwise configured to be electrically connected to each other and electrically isolated from power rail P2.

In the embodiment shown in FIG. 7, each of the power rails P1-P3 overlies each of the gate structures G1-G3. In various embodiments, one or more of the power rails P1-P3 comprise a buried power rail such that each of the gate structures G1-G3 overlies each of the power rails P1-P3.

In various embodiments, the third power rail is configured as a reference power rail, each of the active areas AA2 and AA3 is n-type and each of the active areas AA1 and AA4 is p-type, or the third power rail is configured as a supply power rail, each of the active areas AA2 and AA3 is p-type and each of the active areas AA1 and AA4 is n-type.

As described above, various embodiments of IC device 700 are capable of achieving the benefits discussed above with respect to

IC layouts

200, 400C, 400E, and 400G, as well as fig. 1-6, by having a configuration that corresponds to the configuration of various embodiments of IC layout 200.

Fig. 8 is a block diagram of an IC layout generation system 800 according to some embodiments. According to some embodiments, the methods of designing an IC layout described herein according to one or more embodiments are implementable, for example, using IC layout generation system 800.

In some embodiments, the IC layout generation system 800 is a general purpose computing device that includes a hardware processor 802 and a non-transitory computer-readable storage medium 804. The storage medium 804 is encoded, i.e., stores, among other things, computer program code 806, i.e., a set of executable instructions. The instructions 806 executed by the hardware processor 802 represent (at least in part) an EDA tool that implements a portion or all of a method, such as the method of generating an IC layout (hereinafter, the process and/or method described) described above.

The processor 802 is electrically coupled to a computer-readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to an I/O interface 810 through the bus 808. A network interface 812 is also electrically coupled to the processor 802 via the bus 808. The network interface 812 is connected to a network 814, so that the processor 802 and the computer-readable storage medium 804 can be connected to external elements through the network 814. The processor 802 is configured to execute computer program code 806 encoded in a computer-readable storage medium 804 to make the IC layout generation system 800 operable to perform a portion or all of the processes and/or methods. In one or more embodiments, processor 802 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, Application Specific Integrated Circuit (ASIC), and/or suitable processing unit.

In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). Computer-readable storage medium 804 includes, for example, a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium 804 includes a compact disk read only memory (CD-ROM), a compact disk read/write (CD-R/W), and/or a Digital Video Disk (DVD).

In one or more embodiments, the storage medium 804 stores computer program code 806 configured to make the IC layout generation system 800 (where such execution represents, at least in part, an EDA tool) available to perform a portion or all of the processes and/or methods. In one or more embodiments, the storage medium 804 also stores information that facilitates performing a portion or all of the processes and/or methods. In one or more embodiments, the storage medium 804 stores a cell library 807 of cells including such cells as disclosed herein, e.g., the double height cell 200C discussed above with respect to fig. 1 and 2.

The IC layout generation system 800 includes an I/O interface 810. The I/O interface 810 is coupled to external circuitry. In one or more embodiments, I/O interface 810 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and/or cursor direction keys to communicate information and commands to processor 802.

The IC layout generation system 800 also includes a network interface 812 coupled to the processor 802. The network interface 812 allows the system 800 to communicate with a network 814, to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and/or methods are implemented in two or more IC layout generation systems 800.

The IC layout generation system 800 is configured to receive information via the I/O interface 810. Information received via I/O interface 810 includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor 802. Information is transferred to processor 802 via bus 808. IC layout generator 800 is configured to receive information related to a UI through I/O interface 810. This information is stored in the computer-readable storage medium 804 as a User Interface (UI) 842.

In some embodiments, some or all of the processes and/or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the processes and/or methods are implemented as software applications as part of additional software applications. In some embodiments, some or all of the processes and/or methods are implemented as plug-ins to software applications. In some embodiments, at least one of the processes and/or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the processes and/or methods are implemented as software applications used by the IC layout generation system 800. In some embodiments, a device such as those available from CADENCE DESIGN SYSTEMS, Inc. is used

Or other suitable layout generation tool, generates a layout that includes standard cells.

In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/in-machine storage or memory units, for example, one or more of an optical disk (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a ROM, a RAM, a memory card, etc.).

Fig. 9 is a block diagram of an IC manufacturing system 900 and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, at least one of (a) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated based on an IC layout, for example, using the fabrication system 900.

In fig. 9, IC manufacturing system 900 includes entities, such as design chamber 920, mask chamber 930, and IC manufacturer/fab ("fab") 950, that interact with each other during design, development, and manufacturing cycles and/or services related to the manufacture of IC devices 960. The entities in system 900 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more other entities. In some embodiments, two or more of the design chamber 920, mask chamber 930, and IC fab 950 are owned by a single larger company. In some embodiments, two or more of the design chamber 920, the mask chamber 930, and the IC fab 950 coexist in a common facility and use common resources.

Design room (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns, such as the IC layouts discussed above. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layers making up the various components of the IC device 960 being fabricated. The various layers combine to form various IC functions. For example, a portion of IC design layout 922 includes various IC components such as active regions, gate electrodes, source and drain, metal lines or vias for inter-level interconnects, and openings for bond pads formed in a semiconductor substrate (such as a silicon wafer) and various layers of materials disposed on the semiconductor substrate. Design chamber 920 performs the appropriate design process to form an IC design layout 922. The design process includes one or more of logical design, physical design, or placement and routing. The IC design layout 922 is presented in one or more data files having geometry information. For example, the IC design layout 922 may be expressed in a GDSII file format or a DFII file format.

Mask chamber 930 includes data preparation 932 and mask fabrication 944. Mask chamber 930 manufactures one or more masks 945 using IC design layout 922 for fabricating the various layers of IC device 960 according to IC design layout 922. Mask chamber 930 performs mask data preparation 932 in which IC design layout 922 is translated into a representative data file ("RDF"). Mask data preparation 932 provides the RDF to mask fabrication 944. Mask fabrication 944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 945 or a semiconductor wafer 953. Mask layout data preparation 932 processes design layout 922 to conform to the specific features of the mask writer and/or the requirements of the IC fab 950. In FIG. 9, mask data preparation 932 and mask fabrication 944 are shown as separate elements. In some embodiments, mask data preparation 932 and mask fabrication 944 may be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 932 includes Optical Proximity Correction (OPC) that uses lithographic enhancement techniques to compensate for image errors, such as may be caused by diffraction, interference, other processing effects, and so forth. The OPC adjusts the IC design layout 922. In some embodiments, the mask data preparation 932 includes other Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, Inverse Lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, the mask data preparation 932 includes a Mask Rules Checker (MRC) that checks the IC design layout 922 that has been processed in OPC using a set of mask creation rules that contain certain geometric and/or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies IC design layout 922 to compensate for constraints during mask manufacturing 944, which may undo a portion of the modifications performed by OPC to satisfy mask creation rules.

In some embodiments, the mask data preparation 932 includes a photolithographic process check (LPC), which simulates the process to be performed by the IC fab 950 to fabricate the IC device 960. The LPC simulates the process based on IC design layout 922 to create a simulated fabricated device, such as IC device 960. The process parameters in the LPC simulation may include parameters associated with various processes of the IC fabrication cycle, parameters associated with the tool used to fabricate the IC, and/or other aspects of the fabrication process. LPC accounts for various factors such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factors ("MEEF"), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated fabricated devices are created by LPC, if the simulated devices are not close enough in shape to meet the design rules, OPC and/or MRC are repeated to further refine the IC design layout 922.

It should be appreciated that the above description of mask data preparation 932 has been simplified for clarity. In some embodiments, the data preparation 932 includes additional features, such as Logic Operations (LOPs), to modify the IC design layout 922 according to manufacturing rules. Additionally, the processes applied to the IC design layout 922 during the data preparation 932 may be performed in a variety of different orders.

After mask data preparation 932 and during mask fabrication 944, mask 945 or a set of masks 945 is fabricated based on modified IC design layout 922. In some embodiments, mask fabrication 944 includes performing one or more lithographic exposures based on IC design layout 922. In some embodiments, an electron beam (e-beam) or multiple electron beam (e-beam) mechanism is used to pattern a mask (photomask or reticle) 945 based on the modified IC design layout 922. Mask 945 can be formed by various techniques. In some embodiments, mask 945 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) or EUV beam, used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and passes through the transparent regions. In one example, the binary mask version of mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in opaque regions of the binary mask. In another example, mask 945 is formed using a phase shift technique. In a Phase Shift Mask (PSM) version of mask 945, various features in the pattern formed on the phase shift mask are configured with appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The resulting mask from mask fabrication 944 is used in a variety of processes. Such masks may be used, for example, in ion implantation processes to form various doped regions in semiconductor wafer 953, in etching processes to form various etched regions in semiconductor wafer 953, and/or in other suitable processes.

The IC fab 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC Fab 950 is a semiconductor fabrication facility. For example, there may be a manufacturing facility for front end of line (FEOL) manufacturing) of a plurality of IC products, while a second manufacturing facility may provide back end of line (BEOL) manufacturing) for the interconnection and packaging of the IC products, and a third manufacturing facility may provide other services for manufacturing businesses.

IC fab 950 includes a wafer fabrication tool 952 configured to perform various fabrication operations on semiconductor wafer 953 to fabricate IC device 960 from a mask (e.g., mask 945). In various embodiments, the manufacturing tool 952 comprises one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

The IC fab 950 uses the mask 945 manufactured by the mask chamber 930 to manufacture the IC device 960. Thus, the IC fab 950 uses, at least indirectly, the IC design layout 922 to fabricate the IC device 960. In some embodiments, the semiconductor wafer 953 is used by the IC fab 950 to fabricate an IC device 960 using the mask 945. In some embodiments, IC fabrication includes performing one or more lithographic exposures based, at least indirectly, on the IC design layout 922. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate having a layer of material formed thereon. Semiconductor wafer 953 also includes one or more of various doped regions, dielectric features, multi-layer interconnects, etc. (formed in subsequent fabrication steps).

Details regarding IC manufacturing systems (e.g., system 900 of fig. 9) and IC manufacturing flows associated therewith may be found in, for example, united states patent No. 9,256,709 issued on 9/2/2016, united states pre-authorization publication No. 20150278429 issued on 1/10/2015, united states pre-authorization publication No. 20140040838 issued on 6/2/2014, and united states patent No. 7,260,442 issued on 21/8/2007, the entire contents of which are incorporated herein by reference.

In some embodiments, a method of generating an IC layout comprises: positioning a first active area in a cell of an IC layout, the first active area being of a first type, n-type or p-type, and corresponding to a first total number of fins; positioning a second active region in the cell adjacent to the first active region, the second active region being of a second type, n-type or p-type, and corresponding to a second total number of fins; positioning a third active area in the cell adjacent to the second active area, the third active area being of the second type and corresponding to a third total number of fins; and positioning a fourth active area in the cell adjacent to the third active area, the fourth active area being of the first type and corresponding to a fourth total number of fins. Each of the first and second total number of fins is greater than each of the third and fourth total number of fins, and locating at least one of the first, second, third, or fourth active regions is performed by the processor. In some embodiments, the method includes fabricating at least one of the one or more semiconductor masks or at least one component in a layer of the semiconductor IC based on the IC layout. In some embodiments, each of the first and second total number of fins is greater than or equal to three, and each of the third and fourth total number of fins is less than or equal to two. In some embodiments, at least one of: the total number of first fins is equal to the total number of second fins, or the total number of third fins is equal to the total number of fourth fins. In some embodiments, positioning the first through fourth active areas in a cell includes positioning the first through fourth active areas in a double-height cell. In some embodiments, locating the second and third active areas includes crossing the power supply trace with the second and third active areas, and the power supply trace corresponds to the reference power supply trace and the second type is n-type, or the power supply trace corresponds to the supply power supply trace and the second type is p-type. In some embodiments, the method includes intersecting each of the first through fourth active regions with a gate region, and intersecting the gate region with a cut polysilicon region. In some embodiments, the method includes storing the IC layout in a cell library.

In some embodiments, an IC layout generation system includes a processor and a non-transitory computer-readable storage medium including computer program code for one or more programs. The non-transitory computer readable storage medium and the computer program code are configured to, with the processor, cause the system to: assigning a first block of circuitry to a first number of fins; arranging a first set of blocks using first and second active regions of an IC layout cell, the first and second active regions collectively corresponding to a plurality of fins having a first number of fins; arranging a second set of blocks of circuitry using third and fourth active areas of the IC layout cell, the third and fourth active areas collectively corresponding to a plurality of fins having a second number of fins less than the first number of fins; and generating an IC layout file based on the IC layout unit. In some embodiments, the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the system to: a first chunk is assigned to a first number of fins based on a timing analysis of the circuit. In some embodiments, the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the system to: calculating a speed level of the circuit based on the first set of blocks being assigned to the first number of fins; comparing the speed level to a threshold speed level; and allocating additional circuit blocks to the first number of fins based on the speed level being below the threshold speed level. In some embodiments, the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the system to: calculating a circuit power level as a sum of a power level of a first set of blocks based on the first number of fins and a power level of a second set of blocks based on the second number of fins; comparing the circuit power level to a threshold power level; and reassigning blocks of the first set of blocks to the second number of fins based on the circuit power level exceeding the threshold power level. In some embodiments, the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the system to: after reassigning the blocks in the first set of blocks to the second number of fins, a circuit speed level based on the first set of blocks is calculated. In some embodiments, the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the system to: calculating an area efficiency level based on the first set of blocks being assigned to the first number of fins and the second set of blocks being assigned to the second number of fins; comparing the area efficiency level to an area efficiency limit; and rebalancing the fin count allocation by at least one of reallocating blocks in the second chunk to the first fin count or reallocating blocks in the first chunk to the second fin count based on the area efficiency level being outside the area efficiency limit. In some embodiments, the non-transitory computer-readable storage medium and the computer program code are configured to, with the processor, further cause the system to: after rebalancing the fin count assignment, a circuit speed level based on the first chunk is calculated. In some embodiments, the first number of fins is greater than or equal to six and the second number of fins is less than or equal to four.

In some embodiments, an IC device includes: a first power rail; a second power rail electrically connected to the first power rail; a third power rail located between and electrically isolated from the first and second power rails; a first active region of a first type adjacent to the first power rail and comprising a first total number of fins; a second active region of a second type, different from the first type, adjacent to the first active region and the third power rail, and comprising a second total number of fins; a third active region of the second type adjacent to the third power rail and comprising a third total number of fins; and a fourth active area of the first type adjacent to the third active area and the second power rail and comprising a fourth total number of fins. A first sum of a total number of the first and second fins is greater than a second sum of a total number of the third and fourth fins. In some embodiments, the first sum is greater than or equal to six and the second sum is less than or equal to four. In some embodiments, the third power rail is configured as a reference power rail and the second type is n-type, or the third power rail is configured as a supply power rail and the second type is p-type. In some embodiments, at least one of the first power rail, the second power rail, or the third power rail comprises a buried power rail.

It will be seen that one or more of the disclosed embodiments achieves one or more of the advantages set forth above, as would be apparent to one of ordinary skill in the art. Numerous variations, equivalent alterations, and numerous other embodiments as broadly disclosed herein will occur to those of ordinary skill in the art upon reading the foregoing description. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.

Claims

1. A method of generating an integrated circuit layout, the method comprising:

positioning a first active region in a cell of the integrated circuit layout, the first active region being of a first type, n-type or p-type, and corresponding to a first total number of fins;

positioning a second active region in the cell adjacent to the first active region, the second active region being of a second type that is n-type or p-type and corresponding to a second total number of fins;

positioning a third active area in the cell adjacent to the second active area, the third active area being of the second type and corresponding to a third total number of fins; and

positioning a fourth active area in the cell adjacent to the third active area, the fourth active area being of the first type and corresponding to a fourth total number of fins,

wherein

Each of the first and second total number of fins is greater than each of the third and fourth total number of fins, and

locating at least one of the first, second, third or fourth active regions is performed by a processor.

2. The method of claim 1, further comprising fabricating, based on the integrated circuit layout, at least one of:

one or more semiconductor masks, or

At least one component in a layer of a semiconductor integrated circuit.

3. The method of claim 1, wherein

Each of the total number of first and second fins is greater than or equal to three, and

each of the total number of third and fourth fins is less than or equal to two.

4. The method of claim 1, wherein at least one of:

the first total number of fins is equal to the second total number of fins, or

The third total number of fins is equal to the fourth total number of fins.

5. The method of claim 1, wherein positioning first through fourth active areas in a cell comprises positioning first through fourth active areas in a double-height cell.

6. The method of claim 1, wherein

Positioning the second and third active areas includes bridging the power supply traces with the second and third active areas, an

The power supply trace corresponds to a reference power supply trace and the second type is n-type, or the power supply trace corresponds to a supply power supply trace and the second type is p-type.

7. The method of claim 1, further comprising:

each of the first to fourth active regions is made to intersect the gate region, and

the gate region is intersected with a cut polysilicon region.

8. The method of claim 1, further comprising storing the integrated circuit layout in a cell library.

9. An integrated circuit layout generation system, comprising:

a processor; and

a non-transitory computer readable storage medium comprising computer program code for one or more programs, the non-transitory computer readable storage medium and the computer program code configured to, with the processor, cause the system to:

assigning a first block of circuitry to a first number of fins;

arranging the first set of blocks using first and second active regions of an integrated circuit layout cell, the first and second active regions collectively corresponding to a plurality of fins having the first number of fins;

arranging a second chunk of the circuit using third and fourth active areas of the integrated circuit layout cell, the third and fourth active areas collectively corresponding to a plurality of fins having a second number of fins less than the first number of fins; and

an integrated circuit layout file is generated based on the integrated circuit layout unit.

10. An integrated circuit device, comprising:

a first power rail;

a second power rail electrically connected to the first power rail;

a third power rail located between and electrically isolated from the first and second power rails;

a first active region of a first type adjacent to the first power rail and comprising a first total number of fins;

a second active region of a second type different from the first type, adjacent to the first active region and the third power rail, and comprising a second total number of fins;

a third active region of the second type adjacent to the third power rail and comprising a third total number of fins; and

a fourth active region of the first type adjacent to the third active region and the second power rail and comprising a fourth total number of fins,

wherein a first sum of a total number of the first and second fins is greater than a second sum of a total number of the third and fourth fins.