CN113312864A - S-shaped configurable delay line, clock structure and clock delay adjusting method - Google Patents

S-shaped configurable delay line, clock structure and clock delay adjusting method Download PDF

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CN113312864A
CN113312864A CN202110475210.6A CN202110475210A CN113312864A CN 113312864 A CN113312864 A CN 113312864A CN 202110475210 A CN202110475210 A CN 202110475210A CN 113312864 A CN113312864 A CN 113312864A
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clock
delay
delay line
node
net
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CN113312864B (en
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蒋剑锋
栾晓琨
边少鲜
邓宇
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Phytium Technology Co Ltd
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

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Abstract

The invention discloses an S-shaped configurable delay line, a Clock structure and a Clock delay adjusting method, wherein the S-shaped configurable delay line comprises a delay line unit chain, one end of the delay line unit chain is connected with a Clock input Clock through a node B, and the Clock input Clock is a Clock input port; the other end of the delay line unit chain is connected with an internal clock main stem of the main clock structure through a node A to adjust clock latency; the delay line unit chain comprises a processing unit S _ cell and a plurality of delay lines S _ net which are arranged in an S shape. The clock structure and the clock delay adjusting method are realized according to the S-shaped configurable delay line. The invention has the advantages of simple structure, good adjustment flexibility, good control accuracy and the like.

Description

S-shaped configurable delay line, clock structure and clock delay adjusting method
Technical Field
The invention mainly relates to the technical field of high-performance chips, in particular to an S-shaped configurable delay line, a clock structure and a clock delay adjusting method.
Background
For high-performance chip design, the clock latency (clock signal delay, also called clock source insertion delay) of some modules (or some blocks in the modules) in the design can be very long, while some modules have very short requirements, tools are very uncontrollable when designing a clock tree, and the clock latency of different modules (or blocks) needs to be adjusted by performing manual eco for many times in the later period.
The traditional manual eco method is time-consuming and labor-consuming, has the defects of large amount of manual operation, inflexible delay adjustment, poor precision control, serious process angle deviation, need of design iteration for a plurality of times and the like, and is not high in efficiency.
A solution proposed by practitioners, such as US10933742, discloses a dynamic phase adjustment circuit comprising a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an adjustable initial portion and a final portion following the adjustable portion. Multiple registers receive the same data. However, the clock signal that causes the register to sample is received from the corresponding delay element in the last portion of the multi-tap delay line. The edge detection and data decision circuit receives the sampled data value from each register.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the S-shaped configurable delay line, the clock structure and the clock delay adjusting method which have the advantages of simple structure, good adjusting flexibility and good control accuracy.
In order to solve the technical problems, the invention adopts the following technical scheme:
an S-type configurable delay line comprises a delay line unit chain, wherein one end of the delay line unit chain is connected with a Clock input Clock through a node B, and the Clock input Clock is a Clock input port; the other end of the delay line unit chain is connected with an internal clock main stem of the main clock structure through a node A to adjust clock latency; the delay line unit chain comprises a processing unit S _ cell and a plurality of delay lines S _ net which are arranged in an S shape.
As a further improvement of the S-shaped configurable delay line of the invention: each delay line S _ net includes more than one layer of metal layer.
As a further improvement of the S-shaped configurable delay line of the invention: all of the layers are arranged in a perpendicular relationship with the Clock input ports of the Clock input Clock.
As a further improvement of the S-shaped configurable delay line of the invention: each of the layers has a central node J, and is divided into two segments, L1 and L2, by the central node J, and L1 is L2.
As a further improvement of the S-shaped configurable delay line of the invention: the stacking height of all the layers is the stacking height H of the S-shaped configurable delay line, H is the physical distance between the node A and the node B, and H is n (W)layer+Slayer) Wherein W islayerIs the width of the delay line S _ net, SlayerN is the number of delay lines S _ net, which is the minimum distance between the delay line S _ net and the adjacent delay line S _ net in the current process that satisfies the design rule.
The invention further provides a Clock structure based on the S-type configurable delay line, which includes a Clock main structure, a Clock input Clock and the S-type configurable delay line, wherein according to a relationship between delay/early requirement in the Clock main structure and a reference S _ delay, the Clock main structure is connected to the corresponding delay line S _ net of the S-type configurable delay line through the node a, so that the node a and the node B are directly interconnected to realize the delay/early requirement.
As a further improvement of the clock structure of the invention: and the clock main structure is accessed to the corresponding central node J on the delay line S _ net through the node A.
As a further improvement of the clock structure of the invention: the reference S _ delay is a delay value of a combination of a single processing unit S _ cell and a single delay line S _ net, and is referred to as the reference S _ delay.
As a further improvement of the clock structure of the invention: all the delay lines S _ net are in a perpendicular relationship with the clock input port.
The invention further provides a clock delay adjusting method based on the S-shaped configurable delay line, which comprises the following steps:
step S1: obtaining a main clock structure;
step S2: obtaining an S-shaped configurable delay line; the delay line unit chain comprises a processing unit S _ cell and a plurality of delay lines S _ net which are arranged in an S shape; one end of the delay line unit chain is connected with a Clock input Clock through a node B, and the Clock input Clock is a Clock input port; the other end of the delay line unit chain is connected with an internal clock main stem of the main clock structure through a node A to adjust clock latency;
step S3: calculating the relation between the required value and the reference S _ delay according to the delay/early requirement, and then accessing the node A into a corresponding node;
step S4: when some modules need to keep the existing clock latency, the clock backbone can copy one same path, and the adjustment is completed by directly interconnecting the node A and the node B.
The clock delay adjusting method is further improved as follows: the reference S _ delay is a delay value of a combination of a single processing unit S _ cell and a single delay line S _ net, and is referred to as the reference S _ delay.
The clock delay adjusting method is further improved as follows: each layer is provided with a central node J, and the node A is connected with the central node J.
The clock delay adjusting method is further improved as follows: all of the layers are arranged in a perpendicular relationship with the Clock input ports of the Clock input Clock.
Compared with the prior art, the invention has the advantages that:
the S-shaped configurable delay line, the clock structure and the clock delay adjusting method have the advantages of simple structure, good adjusting flexibility and good control accuracy, mainly aim at the design with different requirements on latency in a high-performance chip, and replace manual eco-adjustment of clock latency of different modules (or blocks) by adding the S-shaped configurable delay line design vertical to the clock input port direction. The invention is completed at the beginning of design, can quickly and effectively achieve the design purpose, has little influence on the design, and can avoid the influence of post eco adjustment on the design. The invention combines the inv/buf cell and the net into a series of delay chains, does not need to introduce extra logic, has little influence on the original design structure, saves extra expenses, can keep the delay deviation consistent under different process angles, and can be applied to the design with various different latency requirements.
Drawings
Fig. 1 is a schematic diagram of the structural principle of the S-shaped configurable delay line in a specific application example of the present invention.
FIG. 2 is a schematic diagram of a clock body structure of a clock structure in a specific application example of the present invention.
Fig. 3 is a schematic structural diagram of a clock structure after an S-type configurable delay line in a specific application example of the present invention.
FIG. 4 is a schematic diagram of the method of the present invention in a specific application example.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
As shown in fig. 1, the S-type configurable delay line of the present invention is mainly designed for different requirements on Clock latency in a high performance chip, and includes a delay line unit chain, where one end of the delay line unit chain is connected to a Clock input Clock through a node B, where the Clock input Clock is a Clock input port; the other end of the delay line unit chain is connected with an internal clock main stem of the main clock structure through a node A to adjust clock latency; the delay line unit chain comprises a processing unit S _ cell and a plurality of delay lines S _ net which are arranged in an S shape.
In a specific application example, each of the delay lines S _ net includes more than one layer of metal layer, which may be selected according to needs, for example, three layers of metal layers M9-M11 are used in this example.
In a specific application example, all the layers are arranged in a perpendicular relationship with the Clock input ports of the Clock input Clock. Therefore, all the delay lines S _ net are in a vertical relation with the clock input port, the physical distance between two clock access points of the S-shaped configurable delay line is minimum, and the delay line is composed of unit delay and line delay, so that the delay deviations of the design under different process angles can be kept consistent.
In a specific application example, each layer has a central node J, and is divided into two segments, L1 and L2, by the central node J, wherein L1 is L2.
In a specific application example, the stacking height of all the layers is the stacking height H of the S-shaped configurable delay line, where H represents the physical distance between the node a and the node B, and H is n (W)layer+Slayer) Wherein W islayerIs the width of the delay line S _ net, SlayerIn order to obtain the minimum distance between the delay line S _ net and the adjacent delay line S _ net in the current process, which meets the design rule, n is the number of the delay lines S _ net, so that the physical distance from the node a to the node B is the minimum in practical application.
With reference to fig. 1 to fig. 3, the present invention further provides a Clock structure based on the S-type configurable delay line, which includes a Clock main structure, a Clock input Clock, and the S-type configurable delay line, wherein according to a relationship between delay/early requirement in the Clock main structure and a reference S _ delay, the Clock main structure is connected to the corresponding delay line S _ net of the S-type configurable delay line through the node a, so that the node a and the node B are directly interconnected to implement early requirement.
In a preferred embodiment, the clock body structure is accessed to the corresponding central node J on the delay line S _ net through the node a.
In a specific application example, the reference S _ delay is a delay value of a combination of a single processing unit S _ cell and a single delay line S _ net, and is referred to as the reference S _ delay.
As shown in fig. 4, the present invention further provides a clock delay adjusting method of the S-type configurable delay line, comprising the steps of:
step S1: obtaining a main clock structure; obtaining a main clock structure in the design by analyzing the design characteristics and the clock structure, as shown in fig. 2;
step S2: obtaining an S-shaped configurable delay line; selecting a type of unit commonly used in design, and one or more layers of metal layers for designing the S-shaped configurable delay line. In this example, a D6 Buf cell, referred to as a processing cell S _ cell, is used; using a three-layer metal layer of M9-M11, called a delay line S _ net; through a simulation experiment, a delay value of a combination of a single processing unit S _ cell and a single delay line S _ net is obtained and is called as a reference S _ delay;
step S3: designing an S-shaped configurable delay line;
as shown in fig. 3, the whole structure is a delay line cell chain composed of processing units S _ cell and delay line S _ net, and is designed into an S-shape. The Clock input Clock is a Clock input port, one end of the node B is connected with the Clock port, and the other end of the node B is connected with the S-shaped configurable delay line and is sent into the design; one end of the node A is connected with the internal clock backbone, and the other end is connected with the S-shaped configurable delay line for clock latency adjustment.
Wherein, all layers in the S-type configurable delay line are in vertical relation with the Clock input Clock port; j1 and J2 … … Jn are central nodes of each layer, and J1 is connected with a node B and used as an input end of the S-shaped delay line; l1 and L2 are two segments divided by a layer center node, L1 is L2, for example, L1+ L2 is 100 um; h is the stacking height of the S-shaped configurable delay line and is represented by the physical distance between the node A and the node B, and H is n (W)layer+Slayer) Wherein W islayerIs the width of the delay line S _ net, SlayerIn order to obtain the minimum distance between the delay line S _ net and the adjacent delay line S _ net in the current process, which meets the design rule, n is the number of the delay lines S _ net, so that the physical distance from the node a to the node B is the minimum in practical application. As shown in fig. 3, it is an application of the S-shaped configurable delay line in practical design;
step S4: calculating the relation between the required value and the reference S _ delay according to the delay/early requirement, then accessing the node A into (attachTerm) J1 to a corresponding node in Jn, for example, initially accessing the node A into J8, and if early 3 × S _ delay is required in the design, moving the node A forward by 3 nodes, namely accessing the node A into J5, thereby realizing the early requirement;
step S5: a clock needs a keep logic, i.e. a latency does not need an adjustment module or a Block, a clock backbone can copy an equivalent path and is directly interconnected through a node a and a node B, as shown in a path I in fig. 3;
step S6: and finishing the design.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.

Claims (13)

1. An S-type configurable delay line is characterized by comprising a delay line unit chain, wherein one end of the delay line unit chain is connected with a Clock input Clock through a node B, and the Clock input Clock is a Clock input port; the other end of the delay line unit chain is connected with an internal clock main stem of the main clock structure through a node A to adjust clock latency; the delay line unit chain comprises a processing unit S _ cell and a plurality of delay lines S _ net which are arranged in an S shape.
2. The S-shaped configurable delay line of claim 1, wherein each of said delay lines S _ net comprises more than one layer of metal layer.
3. The S-type configurable delay line of claim 2 wherein all of said layers are arranged in a perpendicular relationship to the Clock input ports of the Clock input Clock.
4. The S-shaped configurable delay line of claim 2, wherein each layer has a central node J, and is divided into two segments L1 and L2 by the central node J, and L1 is L2.
5. The S-shaped configurable delay line according to claim 2, 3 or 4, wherein the stacking height of all the layers is H, H is the physical distance between the node a and the node B, and H ═ n (W ═ n · of the S-shaped configurable delay linelayer+Slayer)，Wherein WlayerIs the width of the delay line S _ net, SlayerN is the number of delay lines S _ net, which is the minimum distance between the delay line S _ net and the adjacent delay line S _ net in the current process that satisfies the design rule.
6. A Clock structure based on the S-type configurable delay line of any one of claims 1 to 5, comprising a Clock body structure, a Clock input Clock and the S-type configurable delay line, wherein the Clock body structure accesses the corresponding delay line S _ net of the S-type configurable delay line through the node A according to the relation between delay/early requirement in the Clock body structure and a reference S _ delay, and directly interconnects the node A and the node B to realize the delay/early requirement.
7. The clock structure according to claim 6, wherein said clock body structure is accessed through said node A to a corresponding central node J on said delay line S _ net.
8. The clock architecture according to claim 6, characterized in that the reference S _ delay is a delay value of a combination of a single processing unit S _ cell plus a single delay line S _ net, called reference S _ delay.
9. The clock structure according to claim 6, wherein all of said delay lines S _ net are in a perpendicular relationship to a clock input port.
10. A clock delay adjustment method based on the S-type configurable delay line of any one of claims 1-5, characterized by the steps of:
step S1: obtaining a main clock structure;
step S2: obtaining an S-shaped configurable delay line; the delay line unit chain comprises a processing unit S _ cell and a plurality of delay lines S _ net which are arranged in an S shape; one end of the delay line unit chain is connected with a Clock input Clock through a node B, and the Clock input Clock is a Clock input port; the other end of the delay line unit chain is connected with an internal clock main stem of the main clock structure through a node A to adjust clock latency;
step S3: calculating the relation between the required value and the reference S _ delay according to the delay/early requirement, and then accessing the node A into a corresponding node;
step S4: the clock backbone replicates an equivalent path and is directly interconnected through node a and node B to complete the adjustment.
11. The clock delay adjustment method according to claim 10, wherein the reference S _ delay is a delay value of a combination of a single processing unit S _ cell and a single delay line S _ net, and is referred to as reference S _ delay.
12. The clock delay adjustment method of claim 10, wherein each layer has a central node J, and the node a is connected to the central node J.
13. The Clock delay adjustment method of claim 10, wherein all of the layers are arranged in a perpendicular relationship with the Clock input ports of the Clock input Clock.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7034597B1 (en) * 2004-09-03 2006-04-25 Ami Semiconductor, Inc. Dynamic phase alignment of a clock and data signal using an adjustable clock delay line
CN101359237A (en) * 2007-08-03 2009-02-04 上海摩波彼克半导体有限公司 High speed synchronous peripheral clock phase control device in SOC system processor chip
DE112007001981T5 (en) * 2006-08-24 2009-07-23 Advantest Corp. Variable delay circuit, clock and semiconductor test device
US20090193377A1 (en) * 2008-01-30 2009-07-30 Ruchir Puri Regular local clock buffer placement and latch clustering by iterative optimization
US20180082724A1 (en) * 2016-09-22 2018-03-22 Qualcomm Incorporated Apparatus and method of clock shaping for memory
CN111046624A (en) * 2019-12-17 2020-04-21 天津飞腾信息技术有限公司 Method, device, equipment and medium for constructing chip module interface clock structure
CN111200434A (en) * 2018-11-20 2020-05-26 长鑫存储技术有限公司 Delay locked loop circuit, method of synchronizing clock signal, and semiconductor memory

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7034597B1 (en) * 2004-09-03 2006-04-25 Ami Semiconductor, Inc. Dynamic phase alignment of a clock and data signal using an adjustable clock delay line
DE112007001981T5 (en) * 2006-08-24 2009-07-23 Advantest Corp. Variable delay circuit, clock and semiconductor test device
CN101359237A (en) * 2007-08-03 2009-02-04 上海摩波彼克半导体有限公司 High speed synchronous peripheral clock phase control device in SOC system processor chip
US20090193377A1 (en) * 2008-01-30 2009-07-30 Ruchir Puri Regular local clock buffer placement and latch clustering by iterative optimization
US20180082724A1 (en) * 2016-09-22 2018-03-22 Qualcomm Incorporated Apparatus and method of clock shaping for memory
CN111200434A (en) * 2018-11-20 2020-05-26 长鑫存储技术有限公司 Delay locked loop circuit, method of synchronizing clock signal, and semiconductor memory
CN111046624A (en) * 2019-12-17 2020-04-21 天津飞腾信息技术有限公司 Method, device, equipment and medium for constructing chip module interface clock structure

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