CN113312001B

CN113312001B - Chip data copying device and method

Info

Publication number: CN113312001B
Application number: CN202110628208.8A
Authority: CN
Inventors: 林示麟
Original assignee: Shenzhen Angke Technology Co ltd
Current assignee: Shenzhen Angke Technology Co ltd
Priority date: 2021-06-06
Filing date: 2021-06-06
Publication date: 2024-02-06
Anticipated expiration: 2041-06-06
Also published as: CN113312001A

Abstract

The invention relates to a chip data copying device and method, wherein a logic control unit is adopted to analyze each partition of a master slice to obtain master slice analysis result files, the participation of a processor is reduced, the data processing speed can be improved, the logic control unit is also used to execute copying, the data buffer space of the processor is not needed, the hardware cost is saved, the data processing speed is further improved, the processor can be matched with the master slice analysis result files to copy, the copy data quantity is effectively reduced, the copy time is shortened, the logic control unit can realize different chip communication protocols, thereby supporting the data copying among chips of various protocols, and the corresponding chip data copying device can maximally use the chip hardware bus bandwidth to achieve the purpose of improving the data copying speed of a large-capacity chip.

Description

Chip data copying device and method

Technical Field

The present disclosure relates to the field of semiconductor memory chips, and in particular, to a chip data copying apparatus and method.

Background

At present, for high-capacity chip data writing (for example, the chip storage data capacity is more than 4 GBytes), most of the data are directly written from a computer to a chip for operation, the data writing operation is carried out under the condition of software participation, the bandwidth of a hardware bus cannot be well utilized, and when a plurality of chips are operated, the copying speed of the data is usually slower; while some devices use hardware to write data, the completion time is too long because of the large data size; it can be seen that the conventional chip data copying scheme has a problem of slow speed when a plurality of chips need to write the copy data.

Disclosure of Invention

In view of the above, it is necessary to provide a chip data copying apparatus with a high copying speed.

In one aspect, the present application provides a chip data copying apparatus, including a processor and a logic control unit; the logic control unit is respectively connected with the master slice and each chip to be written;

the logic control unit analyzes each partition of the master slice to obtain a master slice analysis result file, sends the master slice analysis result file to the processor, receives each execution address setting command returned by the processor, starts a data reading command and a data writing command, and reads the effective data of each partition from the master slice and writes the effective data into each chip to be written by taking the minimum read data quantity as a unit; the master analysis result file records the effective data storage table of each partition; the effective data storage table records the length of effective data in the corresponding partition, the check value and the initial position of the minimum read data volume;

and the processor acquires each effective data storage table of the master analysis result file, obtains the length, the check value and the initial position of the minimum read data quantity of the effective data in each partition of the master, generates an execution address setting command of each partition, and issues each execution address setting command to the logic control unit.

In one embodiment, the processor analyzes each valid data storage table of the master analysis result file one by one to obtain the length of valid data, the check value and the initial position of the minimum read data amount in each partition of the master, generates an ith execution address setting command of an ith partition, and issues the ith execution address setting command to the logic control unit; wherein i is a partition sequence number, and the initial value of i is 1;

the logic control unit receives an ith execution address setting command, starts a data reading and data writing command, reads effective data of an ith partition from the master slice by taking the minimum read data quantity as a unit, writes the effective data of the ith partition into each chip to be written, and feeds back writing completion information to the processor;

and the processor receives the writing completion information, updates i to i+1, and returns to the process of executing the ith execution address setting command for generating the ith partition until the execution address setting command for all the partitions in the master is issued to the logic control unit.

In one embodiment, the process of obtaining the master analysis result file includes:

s11, identifying each partition of the master slice and the partition capacity of each partition;

s12, analyzing an ith partition by taking the minimum read data quantity as a unit, marking the Sector position as a first mark if the minimum read data quantity is blank data, marking the corresponding Sector position as a second mark if the minimum read data quantity is valid data, generating Bit tables corresponding to the Sector positions marked as the second mark, and calculating check values corresponding to the Bit tables; the Sector position is a storage position for recording the corresponding minimum read data quantity; i is a partition sequence number, and the initial value of i is 1;

s13, generating an effective data storage table of the ith partition according to each Bit table and each check value of the ith partition, and enabling the effective data storage table to record the length of effective data, the check value and the initial position of the minimum read data quantity in the corresponding partition;

s14, updating i to i+1, returning to the step S12 until the effective data storage tables of all the partitions are obtained, and generating a master analysis result file according to each effective data storage table.

Specifically, the calculation process of the check value includes:

where Bits represents the check value, area represents the partition capacity of the corresponding partition, and Sector represents the minimum read data amount.

In one embodiment, after writing the valid data of each partition into each chip to be written, the logic control unit reads each group of chip data from each chip to be written, calculates the check value of each valid data in each group of chip data, and obtains each group of test check values, and the processor obtains a group of check values of the master chip, obtains a reference check value, and determines that the data copy of each chip to be written is successful if each group of test check values are consistent with the reference check value.

Specifically, the logic control unit sends check value acquisition information to the processor;

and the processor receives the check value acquisition information, reads each check value of each partition from each effective data storage table of the master analysis result file, obtains the reference check value, and returns the reference check value to the logic control unit.

Specifically, the chip data copying device further comprises a display module; and the logic control unit is used for controlling the display module to display information representing successful data copying after judging successful data copying of each chip to be written.

Specifically, the display module comprises a first indicator light, a second indicator light and a third indicator light; the light colors of the first indicator lamp, the second indicator lamp and the third indicator lamp are different from each other;

and the logic control unit controls the first indicator lamp to be turned on after judging that the data copy of each chip to be written is successful, controls the second indicator lamp to be turned on after judging that the data copy of each chip to be written is failed, and controls the third indicator lamp to be turned on when the data is written into each chip to be written.

In one embodiment, the logic control unit is an FPGA.

In one aspect, the present application provides a method for copying chip data, including:

the logic control unit analyzes each partition of the master slice to obtain a master slice analysis result file, and sends the master slice analysis result file to the processor; the master analysis result file records the effective data storage table of each partition; the effective data storage table records the length of effective data in the corresponding partition, the check value and the initial position of the minimum read data volume; the logic control unit is respectively connected with the master slice and each chip to be written; wherein, each chip to be written is consistent with the protocol type of the master;

the processor acquires each effective data storage table of the master analysis result file, obtains the length, the check value and the initial position of the minimum read data quantity of the effective data in each partition of the master, generates an execution address setting command of each partition, and issues each execution address setting command to the logic control unit;

the logic control unit receives each execution address setting command, starts data reading and data writing commands, and reads the effective data of each partition from the master slice and writes the effective data into each chip to be written by taking the minimum read data quantity as a unit.

According to the chip data copying device and method, the logic control unit is adopted to analyze each partition of the master slice to obtain the master slice analysis result file, the participation of a processor is reduced, the data processing speed can be improved, the logic control unit is used to execute copying, the data buffering space of the processor is not needed, the hardware cost is saved, the data processing speed is further improved, the processor can be matched with the master slice analysis result file to copy, the copy data quantity is effectively reduced, the copy time is shortened, the logic control unit can realize different chip communication protocols, so that the data copying among chips of various protocols is supported, the corresponding chip data copying device can use the chip hardware bus bandwidth to the maximum, and the purpose of improving the high-capacity chip data copying speed is achieved.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 is a schematic diagram of a chip data copying apparatus according to one embodiment;

FIG. 2 is a schematic diagram of the operation of a chip data copying apparatus according to one embodiment;

FIG. 3 is a flow chart of the operation of the chip data copying apparatus of one embodiment.

Detailed Description

The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

As shown in fig. 1, a first aspect of the present application provides a chip data copying apparatus, including a processor 105 and a logic control unit 104; the logic control unit 104 is respectively connected with the master 101 and each chip 102 to be written;

the logic control unit 104 analyzes each partition of the master 101 to obtain a master analysis result file, and sends the master analysis result file to the processor 105;

the processor 105 obtains each valid data storage table of the master analysis result file, obtains the length, the check value and the initial position of the minimum read data quantity of the valid data in each partition of the master 101, generates an execution address setting command of each partition, and issues each execution address setting command to the logic control unit 104; the master analysis result file records the effective data storage table of each partition; the effective data storage table records the length of effective data in the corresponding partition, the check value and the initial position of the minimum read data volume;

the logic control unit 104 receives the respective execution address setting commands returned by the processor 105, starts the data reading and writing commands, and reads the effective data of each partition from the master 101 in units of the minimum read data amount and writes the effective data into each chip to be written 102.

The logic control unit 104 may be an FPGA, and the processor 105 may be an MCU host chip, and is mainly responsible for running programs, including an operating system, a burning application program, and a driver program. The logic control unit 104 is mainly responsible for reading and writing high-capacity chip data, and the processor 105 is connected with the logic control unit 104 by a high-speed bus.

In practical applications, the processor 105 and the logic control unit 104 may be arranged in a copying device, which is connected to the master 101 and each chip 102 to be written, respectively. The master 101, i.e. where the chip raw data is present, is accessed by the logic control unit 104 by read operations. The number of chips 102 to be written may be N; if the current device (logic control unit 104) is designed to allow connection of at most 8 chips at a time, the value of N is 1-8; in other application examples, the above operation method is not limited to 8 chips, and may be more. Corresponding data may be written from the logic control unit 104 into the chip to be written by a write operation, and data of the chip to be written may be read into the logic control unit 104 by a read operation. Alternatively, each chip 102 to be written and master 101 are powered by a copying device. Specifically, the protocol types of the chip to be written 102 and the master 101 may be consistent; or inconsistent, if the protocol types of the two are inconsistent, the data copy between different protocol chips can be realized by loading different FPGA programs.

The chip data copying device adopts the logic control unit 104 to analyze each partition of the master slice to obtain the master slice analysis result file, reduces the participation of a processor, can improve the data processing speed, also uses the logic control unit to execute copying, does not need the data buffer space of the processor, saves the hardware cost, further improves the data processing speed, and the processor 105 can match the master slice analysis result file to copy, effectively reduces the copy data quantity, reduces the copy time, and the logic control unit 104 can realize different chip communication protocols, thereby supporting the data copying among chips of various protocols, enabling the corresponding chip data copying device to use the chip hardware bus bandwidth to the maximum, and achieving the purpose of improving the data copying speed of a large-capacity chip.

Specifically, if the logic control unit is an FPGA, the processor is an MCU, and the working schematic diagram of the chip data copying device may also be shown in fig. 2, where the MCU 105 is responsible for running programs, including an operating system, a burning application program and a driver, the FPGA 104 is responsible for reading and writing high-capacity chip data, performing calculation of a data check value (such as CRC 16), and the MCU and the FPGA are connected by a high-speed bus (106). The master 101 is a place where chip original data exist, and can be accessed by the FPGA through a read operation 107, and a chip N shown in fig. 2 represents each chip to be written, and if the current equipment is designed to allow connection of 8 chips at most at a time, the value of N is 1-8; the protocol type of the chip is consistent with that of the master slice, but the data copy between different protocol chips can be realized by loading different FPGA programs. In other examples, the number of chips to be written is not limited to 8 chips, and may be more. Data may be written from the FPGA into the chip by a write operation 108 and data of the chip may be read into the FPGA by a read operation 109. The master 101 and the chip 102 are powered by a copying device (110 shown in fig. 2). The master analysis result file may be an MIF file, where the suffix is called MIF, and the effective data writing process shown in fig. 2 may be shown with reference to fig. 3, where the master analysis is only performed once, and then a master copy stage is entered, and the FPGA is connected with an empty chip during the copy, which is generally achieved by placing the chip in a corresponding chip holder. The driver running in the MCU 105 calls into the MIF file and then copies it as follows:

1. the MCU 105 parses the valid data table stored in the MIF archive one by one to obtain the StartSector of the valid data (starting position of Sector of the valid data), length (Length of valid data) and CRC16 information (check value of valid data).

2. By 108 telling FPGA 104 to execute the address set command, FPGA 104 sets the data read address of master 101 to StartSector, FPGA and sets the data write address of chip 102 to StartSector, after which FPGA 104 initiates the data read and write commands to read data back from master 101 in Sector units and write data to FPGA 104, 107 can also be implemented synchronously during 108 implementation, since the chip is typically written at a slower speed than read, the later 107 implementation time can be ignored except for the first read, appearing to be always performing the data write action. The write execution number is Length/Sector number, and then stops automatically. FPGA 104 informs MCU 105, via a flag bit, that a record copy action has been performed. If there is a problem in the middle, setting an error flag. MCU 105 can set up multiple records for FPGA 104 at a time. The intermediate MCU does not intervene any more and can do other things.

3. After all records of one valid data table are implemented, step 1 is performed to copy the valid data of other partition tables until the data of all the data tables are copied.

The effective data are non-blank data; the first identifier may be 0, the second identifier may be 1, and the first identifier and the second identifier may be set to other values according to requirements.

The calculation process of the check value comprises the following steps:

Bits＝AreaSize/(Sector×8)，

Specifically, the process of obtaining the master analysis result file in this embodiment may refer to the working process shown in fig. 2, and specifically includes the following contents:

1. FPGA 104 reads the master information through 107 to determine the master chip and the capacity of each partition;

2. all the partition data are read, the partition minimum read data amount (a Sector can be 512 Bytes) is marked by taking the unit of the partition minimum read data amount, the determination of the partition minimum read data amount is usually carried out according to the minimum write unit of a large-capacity chip as a set value, the determination can be obtained from a chip manual, the FPGA confirms whether valid data (non-blank data, general chip default blank data is 0) exists in the current Sector, if the current Sector is all blank data, the Sector position is marked as 0, and if the non-blank data exists, the Sector position is marked as 1. Wherein the mark of each Sector occupies 1 Bit, and finally a Bit table with the size of the partition capacity (area size)/(Sector x 8) can be obtained. And simultaneously obtaining the check value of each Sector.

3. And (3) merging the bits with continuous 1 according to the Bit table information in the step (2), recording the positions and the continuous numbers of the sectors started by each 1, and obtaining the check value of the corresponding data. A valid data storage table is obtained by software arrangement, and each table records the following information, A. The starting position (StartSector) of the Sector of the valid data, B. The Length (Length) of the valid data, C. The check value (CRC 16) of the valid data, how many 1 s are recorded after the continuous 1 s of the Bit table are combined.

4. A partition obtains an effective data storage table, returns to the step 2 to analyze other data partitions to obtain effective data tables of other partitions, and finally stores the tables into the MIF file; thus, the MIF file can be generated by completing the analysis process.

In one embodiment, after writing the valid data of each partition into each chip to be written, the logic control unit reads each group of chip data from each chip to be written, calculates the check value of each valid data in each group of chip data to obtain each group of test check values, and the processor obtains a group of check values of the master chip to obtain a reference check value, and determines that the data copy of each chip to be written is successful if each group of test check values are consistent with the reference check value.

Specifically, if all the test check values are consistent with the reference check values, the data copy of all the chips to be written is successful; if each group of test check values is not completely consistent with the reference check value (such as the size or sequence of some check values, etc.), the data copy of each chip to be written fails.

In this embodiment, after the valid data is written into each chip to be written, the data needs to be read back from the chip to be written, so as to determine whether the data of each chip to be written is copied successfully, so as to perform corresponding prompt, and inform the user of the data copying result. The above process may also adopt the related operation shown in fig. 2, where the read-write process 109 of the data in the chip to be written is similar to the process 107, except that 107 is aimed at the master, and 109 is aimed at a plurality of empty chips; the specific operation method comprises the following steps: based on the partition valid data table in the MIF file (master analysis result file), FPGA 104 reads the data back through 109 and performs CRC16 (test check value) calculation. If the CRC16 value is consistent with the reference check value in the record, it indicates that the data is completely stored in the chip and consistent with the master. If the read or write processes are inconsistent, at least one problem exists in the read or write process, and the error is directly reported. And displaying the related results through a result indicator so that a user classifies the burning chips according to the display results of the indicator.

The display module provided in this embodiment may be, for example, the result indicator 111 shown in fig. 2, so as to accurately indicate each result determined by the logic control unit.

Further, the display module comprises a first indicator light, a second indicator light and a third indicator light; the light colors of the first indicator lamp, the second indicator lamp and the third indicator lamp are different from each other;

In one example, the first indicator light may be set to a red light, the second indicator light may be set to a green light, and the third indicator light may be set to a yellow light, where the red light indicates success, the green light indicates failure, and the yellow light indicates that the operation is in progress. In other examples, the first indicator light, the second indicator light, and the third indicator light may be respectively set to other colors according to specific needs.

In another aspect, the present application provides a method for burning a chip serial number, including:

The method for burning the serial number of the chip has all the beneficial effects of the device for copying the data of each chip provided by the embodiment, and is not described in detail herein.

In the foregoing description of the present specification, the terms "fixed," "mounted," "connected," or "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, in terms of the term "coupled," it may be fixedly coupled, detachably coupled, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intermediaries, or in communication with each other or in interaction with each other. Therefore, unless otherwise specifically defined in the specification, a person skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

Those skilled in the art will also appreciate from the foregoing description that terms such as "upper," "lower," "front," "rear," "left," "right," "length," "width," "thickness," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," "circumferential," "center," "longitudinal," "transverse," "clockwise," or "counterclockwise" and the like are used herein for the purpose of facilitating description and simplifying the description of the present invention, and thus do not necessarily have to have, configure, or operate in, the specific orientations, and thus are not to be construed or construed as limiting the present invention.

In addition, the terms "first" or "second" and the like used in the present specification to refer to the numbers or ordinal numbers are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present specification, the meaning of "plurality" means at least two, for example, two, three or more, etc., unless explicitly defined otherwise.

While various embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Many modifications, changes, and substitutions will now occur to those skilled in the art without departing from the spirit and scope of the invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. The appended claims are intended to define the scope of the invention and to cover such modular compositions, equivalents, or alternatives falling within the scope of the claims.

Claims

1. A chip data copying device, which is characterized by comprising a processor and a logic control unit; the logic control unit is respectively connected with the master slice and each chip to be written;

the master analysis result file obtaining process comprises the following steps:

2. The chip data copying apparatus according to claim 1, wherein said processor parses each valid data storage table of said master analysis result file one by one to obtain a length of valid data, a check value, and a start position of a minimum read data amount in each partition of said master, generates an i-th execution address setting command of an i-th partition, and issues the i-th execution address setting command to said logic control unit; wherein i is a partition sequence number, and the initial value of i is 1;

3. The chip data copying apparatus according to claim 1, wherein the process of calculating the check value includes:

4. A chip data copying apparatus according to any one of claims 1 to 3, wherein said logic control unit reads each set of chip data from each chip to be written after writing the valid data of each partition into each chip to be written, calculates the check value of each valid data in each set of chip data, respectively, to obtain each set of test check values, and said processor acquires a set of check values of said master to obtain a reference check value, and determines that the data copy of each chip to be written is successful from the case that each set of test check values is identical to said reference check value.

5. The chip data copying apparatus according to claim 4, wherein said logic control unit transmits check value acquisition information to said processor;

6. The chip data copying apparatus according to claim 4, further comprising a display module; and the logic control unit is used for controlling the display module to display information representing successful data copying after judging successful data copying of each chip to be written.

7. The chip data copying apparatus according to claim 6, wherein said display module includes a first indicator light, a second indicator light, and a third indicator light; the light colors of the first indicator lamp, the second indicator lamp and the third indicator lamp are different from each other;

8. A chip data copying apparatus according to any one of claims 1 to 3, wherein said logic control unit is an FPGA.

9. A method of copying chip data, comprising:

the logic control unit receives each execution address setting command, starts data reading and data writing commands, and reads the effective data of each partition from the master slice and writes the effective data into each chip to be written by taking the minimum read data quantity as a unit;