CN113311989A - Double-piece NAND FLASH bad block management method based on parallel use - Google Patents
Double-piece NAND FLASH bad block management method based on parallel use Download PDFInfo
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- CN113311989A CN113311989A CN202010118410.1A CN202010118410A CN113311989A CN 113311989 A CN113311989 A CN 113311989A CN 202010118410 A CN202010118410 A CN 202010118410A CN 113311989 A CN113311989 A CN 113311989A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a double-piece NAND FLASH bad block management method based on parallel use, which comprises the following steps: s1, in the starting process, scanning all physical erase blocks of the two pieces NAND FLASH respectively, correspondingly constructing two linked lists which are respectively represented by a table a and a table b, wherein each linked list object at least comprises 'block sequence number' information, and creating a BBT according to bad block information; s2, establishing the association between the logic erasing block and the physical erasing block, establishing a logic block association table, and expressing by a table p, wherein each node in the table is used for describing the block sequence numbers of the two NAND FLASH physical erasing blocks corresponding to the logic erasing block respectively; s3, if a bad block is generated in the using process, after the BBT marks the bad block, the corresponding valid flag in the table a or the table b is updated to be invalid according to the block sequence number of the logic erasing block, and then the tail node is removed to traverse the clean block in NAND FLASH where the bad block is located in a reverse order to replace the corresponding bad block in the table p. The storage space utilization of the parallel doublet NAND FLASH is maximized by the present invention.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a method for managing bad blocks of a biplate NANDFLASH based on parallel use.
Background
With the continuous development of science and technology, particularly NAND FLASH technology is developed. NAND FLASH has a high cost performance per bit storage, so that it can be widely used in embedded systems, but due to the problem of manufacturing process, NAND FLASH leaves factory with bad blocks, so it must be used stably and efficiently in cooperation with a reasonable bad block management mechanism.
The nand logical driver of the Linux kernel provides a set of NAND FLASH bad block management schemes, which can be applied to independent one or more NAND FLASH bad block management, and create one or more BBTs in the memory or create one BBT in each NAND FLASH.
NAND FLASH the double-chip is used in parallel, and the application layer can be regarded as operating a large NANDFLASH, compared with the single-chip NAND FLASH, the total storage space can be doubled, and the speed is doubled; and each chip has its own hardware ECC, and the reliability of the data in NAND FLASH is also guaranteed. However, since the data is used in parallel, one piece of data is divided into two parts by bit and stored in NAND FLASH where two pieces are used in parallel, and there is a dependency relationship between the physical blocks of the two pieces NAND FLASH, the bad block management becomes complicated.
Currently, bad block management for the parallel double-slice NAND FLASH is only considered as a whole slice NAND FLASH at a logical layer, physical erase block sequence numbers of two slices NAND FLASH are simply associated one to one, and a BBT is established for management in a memory or on one of the two slices NAND FLASH by using a bad block management mechanism provided by a linux kernel. Any one of the two physical erase blocks is marked as a bad block, a whole logic erase block of the logic layer is marked as a bad block, and the logic erase block is skipped in each reading and writing process.
The defects in the prior art are as follows:
in the current bad block management for the parallel dual-slice NAND FLASH, as long as one of two associated physical erase blocks is marked as a bad block, a logical erase block corresponding to the logical layer becomes unreliable, so that both physical blocks cannot be used, and thus one physical erase block is wasted.
Common terms in the prior art include:
NAND FLASH: a non-volatile storage medium.
ECC: (Error Correcting Code) Error checking and correction.
BBT: (Bad Block Table) Bad Block Table.
MTD: a (memory technology device) is a subsystem of Linux for accessing memory devices (ROM, FLASH).
And the NAND logic drives: a set of logical operation codes for NAND FLASH provided in the linux kernel. Physical erase block: NAND FLASH minimum unit of erase.
A logic erasing block: and according to the abstract storage space mapped by the physical erasing block, the minimum erasing unit accessed by the user layer.
Purifying blocks: NAND FLASH are erased and the data is a block of all 0 xff.
Disclosure of Invention
In order to solve the above problems, the present invention is directed to: the method of the present invention establishes a bad block management mechanism of the parallel dual-slice NAND FLASH at the logic layer to realize the dynamic association of the physical erase block and the management of the bad block, so as to maximize the storage space utilization of the parallel dual-slice NAND FLASH, as shown in fig. 2.
Specifically, the invention provides a double-slice NAND FLASH bad block management method based on parallel use, which comprises the following steps:
s1, in the starting process, scanning all physical erase blocks of the two pieces NAND FLASH respectively, correspondingly constructing two linked lists which are respectively represented by a table a and a table b, wherein each linked list object at least comprises 'block sequence number' information, and creating a BBT according to bad block information;
s2, establishing the association between the logic erasing block and the physical erasing block, establishing a logic block association table, and expressing by a table p, wherein each node in the table is used for describing the block sequence numbers of the two NAND FLASH physical erasing blocks corresponding to the logic erasing block respectively;
s3, if a bad block is generated in the using process, after the BBT marks the bad block, the corresponding valid flag in the table a or the table b is updated to be invalid according to the block sequence number of the logic erasing block, and then the tail node is removed to traverse the clean block in NAND FLASH where the bad block is located in a reverse order to replace the corresponding bad block in the table p.
Thus, the present application has the advantages that: the method can easily manage the bad blocks of the double-piece NAND FLASH used in parallel, avoids the waste of physical erasing blocks, and has simple method and low cost.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a bad block of a prior art parallel biplate NAND FLASH.
FIG. 2 is a hierarchical diagram of the bad block management mechanism to which the present invention relates.
FIG. 3 is a schematic flow diagram of the method of the present invention.
Fig. 4 is a schematic representation of step S1 of the method of the present invention.
Fig. 5 is a schematic representation of step S2 of the method of the present invention.
Fig. 6 is a schematic representation of step S3 of the method of the present invention.
Detailed Description
In order that the technical contents and advantages of the present invention can be more clearly understood, the present invention will now be described in further detail with reference to the accompanying drawings.
As shown in fig. 3, the present invention relates to a bad block management method based on dual-slice NAND FLASH used in parallel, which comprises the following steps:
s1, in the starting process, scanning all physical erase blocks of the two pieces NAND FLASH respectively, correspondingly constructing two linked lists which are respectively represented by a table a and a table b, wherein each linked list object at least comprises 'block sequence number' information, and creating a BBT according to bad block information;
s2, establishing the association between the logic erasing block and the physical erasing block, establishing a logic block association table, and expressing by a table p, wherein each node in the table is used for describing the block sequence numbers of the two NAND FLASH physical erasing blocks corresponding to the logic erasing block respectively;
s3, if a bad block is generated in the using process, after the BBT marks the bad block, the corresponding valid flag in the table a or the table b is updated to be invalid according to the block sequence number of the logic erasing block, and then the tail node is removed to traverse the clean block in NAND FLASH where the bad block is located in a reverse order to replace the corresponding bad block in the table p.
In step S1, each linked list object further includes information as to whether the block is valid or not and whether the block is a clean block or not.
In step S1, the number of valid blocks, which are respectively denoted as a _ num and b _ num, and the maximum logical erase block number are recorded at the same time.
The maximum number of logical erase blocks is the smallest value of a _ num and b _ num.
In step S3, a _ num, b _ num and the maximum logical erase block number are updated simultaneously.
The dual-slice NAND FLASH bad block management method used in parallel is established at the logical level.
In step S2, only table p is visible to the MTD layer, and the MTD layer can directly access the logical erase block address, and find the corresponding physical erase block address of the two slices NAND FLASH through table p.
Further, the present invention can be further explained as follows:
as shown in fig. 4, in the first part, during the starting process, all physical erase blocks of the two pieces NAND FLASH need to be scanned respectively to construct two linked lists (table a and table b), and each linked list object contains information such as "block sequence number, whether a block is valid, whether it is a pure block", and the like; and creating a BBT according to the bad block information, and simultaneously recording the numbers a _ num and b _ num of the effective blocks.
As shown in FIG. 5, in the second part, an association between a logical erase block and a physical erase block is established. At this time, the total number of logical erase blocks is equal to the smaller value of a _ num and b _ num, and a logical block association table (table p) is created, each node is used to describe the block sequence numbers of two NAND FLASH physical erase blocks respectively corresponding to the logical erase blocks, and only the table p is visible to the MTD layer. The MTD layer can directly access the logical erase block address, and find the corresponding physical erase block address of the two slices NAND FLASH through the table p.
As shown in fig. 6, in the third part, if a bad block is generated during the use process, after the bad block is marked, according to the block sequence number of the logical erase block, the valid flag in table a or table b is updated to be invalid, and then the tail node traverses the bad block in reverse order to see whether there are any clean blocks in NAND FLASH to replace the bad block in table p, and simultaneously updates a _ num, b _ num and the maximum logical erase block number. Specifically, a bad block 1 is scanned in flash (a), a bad block m is scanned in flash (b), the sequence is reversed from a tail node, the tail node m in flash (a) is a good block, the tail node in the corresponding table a is a good block m, and then in flash (b), the corresponding good block 1 is further replaced by the good block n in the corresponding flash (a), and the table a and the table b are correspondingly replaced.
The technical scheme of the invention is a scheme for managing the bad blocks of the parallel double-slice NAND FLASH so as to realize the dynamic association of the physical erase blocks and the management of the bad blocks.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes may be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A double-slice NAND FLASH bad block management method based on parallel use is characterized by comprising the following steps:
s1, in the starting process, scanning all physical erase blocks of the two pieces NAND FLASH respectively, correspondingly constructing two linked lists which are respectively represented by a table a and a table b, wherein each linked list object at least comprises 'block sequence number' information, and creating a BBT according to bad block information;
s2, establishing the association between the logic erasing block and the physical erasing block, establishing a logic block association table, and expressing by a table p, wherein each node in the table is used for describing the block sequence numbers of the two NAND FLASH physical erasing blocks corresponding to the logic erasing block respectively;
s3, if a bad block is generated in the using process, after the BBT marks the bad block, the corresponding valid flag in the table a or the table b is updated to be invalid according to the block sequence number of the logic erasing block, and then the tail node is removed to traverse the clean block in NAND FLASH where the bad block is located in a reverse order to replace the corresponding bad block in the table p.
2. The dual-slice NAND FLASH bad block management method according to claim 1, wherein in step S1, each linked list object further includes information as to whether a block is valid or not and whether it is a clean block or not.
3. The method for managing bad blocks of the dual slice NAND FLASH based on parallel usage of claim 1, wherein in step S1, the number of valid blocks, respectively denoted as a _ num and b _ num, and the maximum number of logical erase blocks are recorded simultaneously.
4. The dual-slice NAND FLASH bad block management method according to claim 3, wherein the maximum number of logical erase blocks is the smallest of a _ num and b _ num.
5. The method for managing bad blocks of the dual slice NAND FLASH based on parallel usage of claim 1, wherein in step S3, a _ num, b _ num and the maximum number of logical erase blocks are updated simultaneously.
6. The dual-slice NAND FLASH bad block management method based on parallel usage of claim 1, wherein the dual-slice NAND FLASH bad block management method based on parallel usage is established at a logical layer.
7. The method for managing bad blocks of the dual-slice NAND FLASH based on parallel usage of claim 1, wherein in step S2, only the table p is visible to the MTD layer, and the MTD layer can directly access the logical erase block address and find the corresponding physical erase block address of the two slices NAND FLASH through the table p.
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