CN113308668A

CN113308668A - Mask plate and method for coating film on memory device

Info

Publication number: CN113308668A
Application number: CN202110554374.8A
Authority: CN
Inventors: 陈博才
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-05-20
Filing date: 2021-05-20
Publication date: 2021-08-27
Anticipated expiration: 2041-05-20
Also published as: CN113308668B

Abstract

The application provides a mask and a method for coating a film on a memory device. The method comprises the following steps: providing a mask; determining two corresponding conductive film plating areas on the memory device corresponding to the same group of contact plugs to be led on the memory device; shielding an area to be shielded on the storage device by using a mask plate; plating a conductive film in a region of the memory device exposed to the first hollowed-out region of the mask; plating an insulating film on a path from the conductive film to a corresponding contact plug to be led in a second hollow region where the memory device is exposed to the contact plug to be led; and plating a conducting wire on a path between the conductive film and the corresponding contact plug to be led in the first hollow area and/or the second hollow area exposed by the memory device so as to electrically connect the contact plug to be led with the corresponding conductive film. The method for coating the film on the storage device utilizes the mask plate to mask the area to be masked on the storage device, thereby reducing the operation difficulty and saving the time and the material.

Description

Mask plate and method for coating film on memory device

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a mask and a method for coating a film on a memory device.

Background

A 3D NAND memory device is an emerging three-dimensional memory device type that solves the problem of limited memory capacity of 2D or planar NAND memory devices by stacking memory chips together. The 3D NAND memory device vertically stacks multiple layers of data storage cells, and its word line length size is extremely large, even up to several millimeters, compared to other memory devices. Therefore, the 3D NAND memory device is prone to word line related problems (e.g., a short type failure between word line layers, between a word line and a source) during the manufacturing process. Then, when the 3D NAND memory device fails, it is important to capture a failure point (referred to as a capture point).

In the process of grabbing points, a test probe is needed to apply voltage to word lines to grab failure points on a test machine, and the test probe cannot be directly and reliably connected with word line contact plugs, so that before grabbing points, an FIB (Focused Ion beam) machine is needed to plate a conductive film on a storage device, the word line contact plugs to be detected are led to the conductive film through a plated lead, and then the test probe is pricked on the conductive film in the test machine to apply voltage to the word lines to be detected for detection.

When FIB coating is performed, the ion beam is sputtered to contaminate the periphery of the target region with sputtered ions (see fig. 1). In addition, as shown in fig. 2, the contact plug 100 to be wired in the memory device 1 needs to be wired to a conductive film. In order to prevent short circuit caused by ion sputtering to the surrounding circuit, the conventional coating method (as shown in fig. 3) is: first, an insulating film 701 is plated on a region where a circuit exists around a conductive film plating region and a region where a circuit exists in a path from the conductive film plating region to a contact plug to be led, and the insulating film 701 is used for preventing ions from being sputtered to a surrounding circuit to cause a short circuit and preventing a wire 703 from being electrically contacted with other circuits to cause a short circuit. Then, the conductive film 702 is plated on the conductive film plating region. Finally, a wiring 703 is plated on the insulating film 701 to electrically connect the contact plug to be led 100 with the conductive film 702. However, this approach has some drawbacks: when there are many circuits around the target region, a large area of the insulating film 701 needs to be plated, which is difficult to operate and time-consuming and material-consuming.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. Therefore, the application provides a mask and a method for coating a film on a storage device, and by adopting the film coating method provided by the application, the operation difficulty of film coating can be reduced, and time and materials can be saved.

The first aspect of the present application provides a mask, the mask is used for assisting in plating a film on a storage device, wherein, the storage device includes that a plurality of word line contact plugs and two conducting films plate and establish the region, including at least a set of contact plug of waiting to draw in the contact plug, each set of contact plug of waiting to draw includes with two conducting films plate and establish two contact plugs of waiting to draw that the region one-to-one was established to the region, the mask includes two first fretwork regions and at least one second fretwork region, two first fretwork regions are used for assisting to plate and establish the conducting film to the conducting film of storage device plates and establishes in the region. The at least one second hollow-out region is used for assisting in plating an insulating film to the conductive film plating region to a path of the corresponding contact plug to be led.

A second aspect of the present application provides a method of plating a film on a memory device, the method comprising: providing a mask according to the first aspect; determining two corresponding conductive film plating areas on the memory device corresponding to two contact plugs to be led of the same group; shielding a region to be shielded on the storage device by using the mask plate, so that two first hollowed-out regions of the mask plate are respectively aligned with the two conductive film plated regions, and at least one second hollowed-out region of the mask plate corresponds to a path from the conductive film plated region to the contact plug to be led, wherein the region to be shielded comprises a circuit region located around the conductive film plated region and a circuit region located around a path from the conductive film plated region to the corresponding contact plug to be led; plating a conductive film in a region of the memory device exposed to the first hollowed-out region of the mask; plating an insulating film on a path between the conductive film and the corresponding contact plug to be led in a second hollow area where the memory device is exposed to the contact plug to be led; and plating a conducting wire on a path between the conductive film and the corresponding contact plug to be led in the first hollow area and/or the second hollow area, which are exposed out of the memory device, so as to electrically connect the contact plug to be led with the corresponding conductive film.

The mask plate provided by the first aspect is adopted to perform auxiliary film coating on the storage device, so that the contact plug to be connected is connected to the conductive film in a leading mode, the first hollow-out area of the mask plate is matched with the conductive film plating area, and the at least one second hollow-out area is matched with the path from the conductive film plating area to the corresponding contact plug to be connected, so that the operation difficulty of film coating can be reduced by using the mask plate to perform auxiliary film coating. In addition, the mask plate shields the area to be masked on the storage device, so that the pollution of ion sputtering on other circuit areas on the storage device can be avoided, a large amount of insulating films are not required to be plated in the film plating process, and the film plating time and the materials can be saved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a schematic view of ion sputtering in ion beam coating.

Fig. 2 is a schematic diagram of the structure of the memory device.

Fig. 3 is a schematic diagram of an application of a conventional method for coating a memory device with a film.

Fig. 4 is a top view of a memory device provided herein.

Fig. 5 is a cross-sectional view of a memory device provided herein.

Fig. 6a is a schematic structural diagram of a mask provided in the first embodiment of the present application.

Fig. 6b is a schematic structural diagram of a mask provided in the second embodiment of the present application.

Fig. 7 is a schematic flow chart of a method for coating a film on a memory device according to a first embodiment of the present application.

Fig. 8a to 8e are schematic diagrams of an application of the method for coating a film on a memory device according to the first embodiment of the present application.

Fig. 9 is a schematic diagram of another application of the method for coating a film on a memory device according to the first embodiment of the present application.

Fig. 10 is a schematic flow chart of a method for coating a film on a memory device according to a second embodiment of the present application.

Fig. 11 is a schematic diagram illustrating an application of a method for plating a film on a memory device according to a third embodiment of the present application.

Fig. 12 is a schematic flow chart illustrating a method for coating a film on a memory device according to a fourth embodiment of the present disclosure.

Fig. 13 a-13 b are schematic diagrams illustrating an application of a method for coating a film on a memory device according to a fourth embodiment of the present application.

Description of the main element symbols:

memory device 1

Storage area 2

Memory cell region 30

Stepped region 10

Masking plate 20

Contact plug 100 to be leaded

Conductive film plating area 2011

Path 2021

Conductive film 702

Insulating

films

701 and 7011

Conducting wire 703

First hollowed-out area 201

Second hollowed-out area 202

Word line contact plug 101

Word line contact plug 1011 to be connected

Array common source 102

P-well contact plug 103

P-well contact plug 1031 to be leaded to

Word line layer 104

Substrate 105

Steps

600, 601, 602, 603,

604、6041、6042、

6043、605

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Focused particle beam technique

The Focused Ion Beam (FIB) system focuses an Ion beam into a micro-cutting instrument with a very small size by using an electric lens, and the Ion beam of the current commercial system is a Liquid Metal Ion Source (LMIS), and the Metal material is Gallium (Ga) because Gallium has a low melting point, a low vapor pressure, and a good oxidation resistance; the typical ion beam microscope includes liquid phase metal ion source, electric lens, scanning electrode, secondary particle detector, 5-6 axially moving test piece base, vacuum system, vibration and magnetic field resisting device, electronic control panel, computer and other hardware, applied electric field (Suppressor) and liquid phase metal ion source can make liquid gallium form fine tip, and then negative electric field (extra) is added to pull gallium at tip to derive gallium ion beam, under the general working voltage, the tip current density is about 1 angstrom 10-8Amp/cm2, the electric lens is used for focusing, the size of ion beam can be determined through a series of Variable Aperture (AVA), and then the ion beam is secondarily focused to the surface of test piece, and the purpose of cutting and deposition can be achieved by physical collision.

The applications of focused ion beams in the semiconductor integrated circuit industry can be mainly classified into five categories: 1. line repair and layout verification; 2. analyzing component faults; 3. analyzing the abnormal process of the production line; IC process monitoring-such as photoresist dicing; 5. manufacturing a transmission electron microscope test piece. In various applications, the work of line repair and layout verification has the greatest economic benefit, the research and development cost of reworking a photomask and performing initial trial can be omitted by local line modification, and the operation mode is absolutely effective for shortening the time from research and development to volume production and simultaneously saves a great deal of research and development cost. Selective material evaporation (selective Deposition), which is the Deposition of a conductor or a nonconductor in a local area by decomposing an organic Metal vapor or a gas phase insulating material with the energy of an ion beam, can provide the Deposition of a Metal and a TEOS Deposition, and the common Metal Deposition includes two types of Platinum (Pt) and tungsten (tungsten, W).

Referring to fig. 4-5 together, fig. 4 and 5 are a top view and a cross-sectional view of a memory device provided by the present application, respectively. The memory device 1 includes a plurality of memory regions 2, and a basic structure of the memory regions 2 includes a substrate 105 and a stacked structure on the substrate 105, the stacked structure being composed of insulating layers and gate layers (e.g., word line layers 104) alternately stacked in a direction perpendicular to the substrate 105. The stacked structure includes a memory cell region 30 and a step region 10 disposed around the memory cell region 30.

Through holes penetrating through the insulating layer are formed in the insulating layer of the stepped region 10 corresponding to the gate layer and the substrate 105, respectively, so as to expose the gate layer and the substrate 105, and the through holes are filled with metal tungsten to form contact plugs (e.g., a word line contact plug 101 led out from a word line layer 104, and a P-well contact plug 103 led out from the substrate 105). The extraction and control of the gate of each memory particle in the memory region 2 are realized by the above-described contact plug. As shown in fig. 4, the memory region 2 further includes a plurality of parallel-arranged array common sources 102, and a plurality of word line contact plugs 101 are arrayed between adjacent array common sources 102.

When the memory device 1 has a word line related problem to cause a memory device failure, before a failure point is grasped, as shown in fig. 3, a FIB (Focused Ion beam) machine is required to plate a conductive film 702 on the memory device 1, then the to-be-led contact plug 100 is led to the conductive film 702 through a plated wire 703, and then a test probe is pricked on the conductive film 702 in a test machine to perform voltage application detection on a word line layer to be detected. It should be noted that, when the memory device 1 fails due to the word line related problem, the memory device 1 at least includes a word line layer and needs to be subjected to voltage application detection, and therefore, the memory device 1 at least includes a set of contact plugs 100 to be led.

In order to solve the problems of high operation difficulty and time consumption and consumables in the process of plating the conductive film 702 to connect the to-be-connected contact plug 100, the present embodiment provides a mask 20 for assisting in plating a film on the memory device 1, wherein the memory device 1 includes a plurality of contact plugs (e.g., the word line contact plug 101 and the P-well contact plug 103) and two conductive film plating regions 2011. The contact plugs include at least one group of contact plugs 100 to be connected, each group of contact plugs 100 to be connected includes two contact plugs 100 to be connected, which correspond to the two conductive film plating regions 2011 one to one, and the mask 20 includes two first hollow regions 201 and at least one second hollow region 202. The two first hollow regions 201 are used to assist in plating the conductive film 702 into the conductive film plating region 2011 of the memory device 1. The second hollow region 202 is used to assist in plating an insulating film 701 to the conductive film plating region 2011 to a path of the contact plug 100 to be connected. It should be noted that the same set of the to-be-leaded contact plugs 100 includes two contact plugs to be leaded to the conductive film 702, wherein the to-be-leaded contact plugs 100 include the to-be-leaded word line contact plugs 1011, and in some embodiments, the to-be-leaded contact plugs 100 further include the to-be-leaded P-well contact plugs 1031.

In the first embodiment, the mask 20 is rectangular, and the mask 20 includes two first hollow-out regions 201 and 4 second hollow-out regions 202, where the two first hollow-out regions 201 are disposed at intervals in a width direction (OA direction shown in fig. 6 a), the 4 second hollow-out regions 202 are disposed at intervals in the width direction (OA direction shown in fig. 6 a), and each of the first hollow-out regions 201 is respectively communicated with the two second hollow-out regions 202. In other embodiments, the mask 20 may include more than 4 second hollow-out regions, so when the mask 20 is used for auxiliary plating, an appropriate second hollow-out region 202 may be selected according to a distance between two contact plugs 100 to be connected in the same group, and the applicability is wide.

In this embodiment, the mask 20 is in a convex shape, the mask 20 includes two first hollow areas 201 with the same shape and size and two second hollow areas 202 with the same shape and size, wherein the two first hollow areas 201 are both arranged at intervals along a width direction (the OA direction shown in fig. 6 b), the two second hollow areas 202 are arranged at intervals along the width direction (the OA direction shown in fig. 6 b), the two first hollow areas 201 are in one-to-one correspondence with the two second hollow areas 202, and the first hollow areas 201 and the second hollow areas 202 which are mutually communicated correspond to the same contact plug 100 to be connected. It is understood that the two first hollow areas 201 may have any suitable shape, such as an oval shape, a rectangular shape, a square shape, a circular shape in a plan view, as long as a test probe is conveniently pricked at the time of testing the memory device 1. Preferably, the two first hollow-out areas 201 and the two second hollow-out areas 202 are rectangular. Further preferably, the length of the first hollow area along the width direction (OA direction shown in fig. 6 b) is greater than or equal to 12 micrometers, and the length along the length direction (OB direction shown in fig. 6 b) is greater than or equal to 5 micrometers. Further preferably, the length of the second hollow area along the width direction (OA direction shown in fig. 6 b) is 2 micrometers, and the length along the length direction (OB direction shown in fig. 6 b) is 30 micrometers. Obviously, the mask 20 is arranged in a convex shape, so that the mask material can be saved.

In other embodiments, the mask 20 may have other shapes as long as it can be used to assist in plating the conductive film 702 and/or the insulating film 701 on the memory device 1.

Referring to fig. 7 and fig. 8 a-8 e together, fig. 7 is a schematic flow chart illustrating a method for coating a film on a memory device according to a first embodiment of the present disclosure. Fig. 8a to 8e are schematic diagrams of an application of the method for coating a film on a memory device according to the first embodiment of the present application.

As shown in fig. 7, the method for coating a memory device includes the steps of:

step 600, a mask 20 is provided.

In this embodiment, a mask 20 as in the embodiment shown in fig. 6b is used to assist in plating the memory device 1.

In step 601, two corresponding conductive film plating regions 2011 are defined on the memory device 1 corresponding to the same set of contact plugs 100 to be connected on the memory device 1.

As shown in fig. 8a, a group of the contact plugs 100 to be connected on the memory device 1 includes two word line contact plugs 1011 to be connected adjacent in the lateral direction. Corresponding to the positions of two to-be-led contact plugs 100, two conductive film plating regions 2011 are defined in the area of the memory device 1 nearest to the two to-be-led contact plugs 100 and having no or little circuit, wherein the lateral direction is a direction perpendicular to the extending direction of the array common source 102 (OY direction shown in fig. 8 a). Preferably, two conductive film plating regions 2011 are selected in the region between the array common source 102 and its corresponding P-well contact plug 103, which is free of circuitry. Further, a path 2021 from the conductive film plating region 2011 to the corresponding contact plug 100 to be connected is determined, wherein the path 2021 is substantially parallel to the extending direction of the array common source 102.

Step 602, using the mask 20 to mask the area to be masked on the storage device 1.

As shown in fig. 8b, the mask 20 is placed such that the two first hollow-out regions 201 of the mask 20 are aligned with the two conductive film plated regions 2011, and the two second hollow-out regions 202 of the mask 20 correspond to a path 2021 from the conductive film plated region 2011 to the corresponding contact plug 100 to be connected, where the region to be masked includes a circuit region around the conductive film plated region 2011 and a circuit region around a path from the conductive film plated region 2011 to the corresponding contact plug 100 to be connected.

Since the first hollow area 201 of the mask 20 is matched with the conductive film plating area 2011, and the second hollow area 202 is matched with the path from the conductive film plating area 2011 to the corresponding contact plug 100 to be connected, the auxiliary plating by using the mask 20 can reduce the difficulty of the plating operation.

Step 603, plating a conductive film 702 in the area of the memory device 1 exposed to the first hollow area 201 of the mask 20.

As shown in fig. 8c, the shape of the conductive film 702 is the same as that of the first hollow area 201, and the area of the first hollow area 201 is slightly larger than that of the conductive film 702. In other embodiments, the conductive film 702 may have any suitable shape, such as an oval shape, a rectangular shape, a square shape, or a circular shape in a plan view, as long as it is formed in the first hollow area 201.

Further, this step forms the conductive film 702 by depositing one of tungsten, cobalt, copper, and aluminum using a focused ion beam. Of course, in other embodiments, the conductive film 702 may be formed by depositing other conductive materials using a focused ion beam.

Obviously, due to the masking effect of the mask 20, when the conductive film 702 is plated, the sputtered ions are shielded by the mask 20 and do not sputter onto other adjacent circuits, so that it is not necessary to plate a large-area insulating film 701 to shield a portion of the conductive film plated area 2011 adjacent to a circuit before the conductive film 702 is plated. Therefore, the operation difficulty can be reduced, and the time and the materials can be saved.

In step 604, an insulating film 701 is plated on a path 2021 from the conductive film 702 to the corresponding contact plug 100 to be connected in the second hollow region 202 where the memory device 1 is exposed to the contact plug 100 to be connected.

Preferably, an insulating film 701 is plated on a circuit region in a path 2021 between the conductive film 702 to its corresponding contact plug 100 to be led. As shown in fig. 8d, in this embodiment, the insulating film 701 is not plated in a portion where no circuit exists in the path 2021 between the conductive film 702 and its corresponding contact plug 100 to be led, so that material can be saved.

Further, this step forms the insulating film 701 by depositing silicon oxide or silicon nitride using a focused ion beam. Of course, in other embodiments, the insulating film 701 may be formed by depositing other insulating materials using a focused ion beam.

The insulating film 701 is plated to cover other circuits in the path 2021 between the conductive film 702 and the corresponding contact plug 100 to be connected, and in addition, when the insulating film 701 is plated, due to the shielding effect of the mask plate 20, sputtered ions are shielded by the mask plate 20 and are not sputtered to other adjacent circuits, so that the plating precision is improved, and the operation difficulty is reduced.

Step 605, plating a conductive line 703 on a path 2021 between the conductive film 702 and the corresponding contact plug 100 to be led in the first hollow area 201 and/or the second hollow area 202 of the memory device 1, so as to electrically connect the contact plug 100 to be led and the corresponding conductive film 702.

As shown in fig. 8e, in the area where there is a circuit on the path 2021 between the conductive film 702 to its corresponding contact plug 100 to be led, the wire 703 is plated over the insulating film 701. In this manner, the conductive line 703 can be electrically isolated from its adjacent circuitry. Preferably, the conductive wire 703 electrically connected between one of the conductive films 702 and its corresponding contact plug 100 to be led is a section of conductive wire parallel to the extending direction of the array common source 102, and in other embodiments, the conductive wire 703 may also be formed by connecting multiple sections of conductive wires.

Further, this step uses a focused ion beam to deposit one of tungsten, cobalt, copper, or aluminum to form the conductive line 703. Of course, in other embodiments, the conductive line 703 may be formed by depositing other conductive materials using a focused ion beam.

When the conductive line 703 is plated, sputtered ions are not sputtered onto an adjacent circuit due to the masking effect of the mask 20 and the insulating film 701, and short-circuiting can be prevented from being caused.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating another application of the method for coating a film on a memory device according to the first embodiment of the present application. The set of contact plugs 100 to be bonded in this embodiment includes two non-adjacent word line contact plugs 1011 to be bonded, so that the mask 20 in the embodiment shown in fig. 6a may be used for auxiliary plating. It should be noted that the positional relationship between two word line contact plugs 1011 to be leaded in the set of contact plugs 100 to be leaded illustrated in the present embodiment is only exemplary, and should not be construed as a limitation to the present application.

Obviously, when each first hollow area 201 of the mask 20 is communicated with a plurality of second hollow areas 202 arranged at intervals, the mask 20 may select a suitable placement position according to the position of the same group of contact plugs 100 to be connected, so that the two second hollow areas 202 of the mask 20 can match with the path from the conductive film plating area 2011 to the contact plugs 100 to be connected. Therefore, the mask 20 can assist in coating films for a plurality of contact plug groups to be connected with different position relationships, and the applicability is wide.

Referring to fig. 10-11 together, fig. 10 is a flow chart illustrating a method for coating a film on a memory device according to a second embodiment of the present disclosure.

As shown in fig. 10, the method for plating a film on a memory device includes the steps of:

step 600, a mask 20 is provided.

As shown in fig. 11, a set of contact plugs to be connected 100 in the memory device 1 of the present embodiment includes a word line contact plug 1011 to be connected and a P well contact plug 1031 to be connected.

The mask 20 is placed so that the two first hollow areas 201 of the mask 20 are aligned with the two conductive film plated areas 2011, and one second hollow area 202 of the mask 20 corresponds to the conductive film plated area 2011 corresponding to the word line contact plug 1011 to be connected.

In step 604, an insulating film 701 is plated on a circuit region in a path 2021 from the conductive film 702 to the corresponding contact plug 100 to be connected, in the second hollow region 202 where the memory device 1 is exposed to the contact plug 100 to be connected.

As shown in fig. 11, the insulating film 701 is plated on a circuit region in a path between the one word line contact plug 1011 to be connected to the corresponding conductive film 702.

In this embodiment, the specific technical details of steps 601 to 604 have been described in detail in the embodiment shown in fig. 7, and are not described herein again.

Step 6041, remove the mask 20.

In this embodiment, the mask 20 is removed from the storage device 1 using a dedicated probe of the FIB machine.

Step 6043, cleaning the insulating film sputtered on the surface of the contact plug 100 to be bonded.

In the step of plating an insulating film, if a small amount of insulating material is sputtered to the surface of the contact plug 100 to be led, the insulating film on the surface of the contact plug 100 to be led is cleaned before the step of plating a wire, and it is possible to ensure that the wire 703 can be reliably electrically connected to the corresponding contact plug 100 to be led when the wire is plated.

As shown in fig. 11, before the mask 20 is removed, the mask 20 blocks the path from the P-well contact 1031 to be bonded to the corresponding conductive film 702, so that after the mask 20 is removed, the conductive wire 703 is plated to electrically connect the P-well contact 1031 to be bonded to the corresponding conductive film 702.

Referring to fig. 12 and fig. 13 a-13 b together, fig. 12 is a flow chart illustrating a method for coating a film on a memory device according to a fourth embodiment of the present disclosure.

As shown in fig. 12, the method for plating a film on a memory device includes the steps of:

step 600, a mask 20 is provided.

As shown in fig. 13a, a set of contact plugs 100 to be connected in the memory device 1 includes two word line contact plugs 1011 to be connected adjacent to each other in a column direction, wherein the column direction is a direction parallel to the extending direction of the array common source 102 (the OX direction shown in fig. 13 a). Specifically, a path extending from one of the word line contact plugs 1011 to be connected close to the P-well contact plug 103 to the corresponding conductive film plating region 2011 along the extending direction of the array common source 102 is determined as a connection path 2021 corresponding to the word line contact plug 1011 to be connected; a path extending from one word line contact plug 1011 to be connected far away from the P well contact plug 103 to an adjacent word line contact plug row and then turning to the conductive film plating region 2011 extending along the extending direction of the array common source 102 is determined as a connection path 2021 corresponding to the word line contact plug 1011 to be connected, wherein the adjacent word line contact plug row is the word line contact plug row adjacent to the row where the two word line contact plugs 1011 to be connected are located.

In this embodiment, the mask 20 in the embodiment shown in fig. 6b is used to block the region to be masked on the memory device 1, so that the extending direction of the two second hollow-out regions 202 is substantially parallel to the extending direction of the array common source 102, and the two word line contact plugs 1011 to be routed are completely exposed in one of the second hollow-out regions 202.

In this embodiment, the specific technical details of steps 603 to 604 are already described in detail in the embodiment shown in fig. 7, and are not described herein again.

Step 6041, remove the mask 20.

In step 6042, an insulating film 7011 is additionally plated on a path from the conductive film 702 to the corresponding contact plug 100 to be led, in a region where the insulating film 701 is not plated but a circuit is present.

As shown in fig. 13b, since a partial region of a path from one of the word line contact plugs 1011 to be connected to the corresponding conductive film 702, which is far from the P-well contact plug 103, to the corresponding conductive film 702 is blocked by the mask 20 before the mask 20 is removed, the partial region is not plated with the insulating film when step 604 is performed, and then, after the mask 20 is removed, the circuit region in the partial region needs to be plated with the insulating film 7011.

In this embodiment, the specific technical details of step 6043 have already been described in detail in the embodiment shown in fig. 10, and are not described again here.

As shown in fig. 13b, in the present embodiment, the conductive line 703 connecting one of the word line contact plugs 1011 to be connected away from the P-well contact plug 103 to the corresponding conductive film 702 is formed by two conductive lines electrically connected.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A mask plate is used for assisting in coating a film on a storage device, wherein the storage device comprises a plurality of word line contact plugs and two conductive film coating areas, the contact plugs comprise at least one group of contact plugs to be led, each group of contact plugs to be led comprises two contact plugs to be led, which are in one-to-one correspondence with the two conductive film coating areas, and the mask plate is characterized by comprising:

two first hollow areas for assisting in plating a conductive film into the conductive film plating area of the memory device;

and the at least one second hollow-out region is used for assisting in plating an insulating film on a path from the conductive film plating region to the corresponding contact plug to be led.

2. The mask of claim 1, wherein any one of the second hollow-out regions is communicated with one of the first hollow-out regions, and the communicated first hollow-out region and second hollow-out region correspond to the same contact plug to be connected.

3. A method of plating a film on a memory device, the method comprising:

providing a mask according to any one of claims 1-2;

determining two corresponding conductive film plating areas on the memory device corresponding to the same group of contact plugs to be led on the memory device;

shielding a region to be shielded on the storage device by using the mask plate, so that two first hollowed-out regions of the mask plate are respectively aligned with two conductive film plated regions, and at least one second hollowed-out region of the mask plate corresponds to a path from the conductive film plated region to the contact plug to be led, wherein the region to be shielded comprises a circuit region located around the conductive film plated region and a circuit region located around a path from the conductive film plated region to the corresponding contact plug to be led;

plating a conductive film in a region of the memory device exposed to the first hollowed-out region of the mask;

plating an insulating film on a path between the conductive film and the corresponding contact plug to be led in a second hollow area where the memory device is exposed to the contact plug to be led;

and plating a conducting wire on a path between the conductive film and the corresponding contact plug to be led in the first hollow area and/or the second hollow area, which are exposed out of the memory device, so as to electrically connect the contact plug to be led with the corresponding conductive film.

4. The method of plating a film on a memory device according to claim 3, wherein plating an insulating film on a path between the conductive film to its corresponding contact plug to be led comprises:

an insulating film is plated on a circuit region in a path between the conductive film to its corresponding contact plug to be led.

5. The method of plating a memory device according to claim 4, wherein prior to the step of plating the conductive lines, the method further comprises: cleaning the insulating film sputtered to the surface of the contact plug to be led.

6. The method for plating a memory device according to claim 5, wherein before the step of cleaning the insulating film sputtered on the surface of the contact plug to be routed, the method further comprises:

the mask is removed.

7. The method of coating a memory device of claim 6, wherein after the step of removing the mask, the method further comprises:

and on the path from the conductive film to the corresponding contact plug to be led, additionally plating an insulating film on the region which has a circuit but is not plated with the insulating film, and then plating a lead.

8. The method for plating a film on a memory device according to claim 3, wherein the step of plating an insulating film forms the insulating film by depositing silicon oxide or silicon nitride using a focused ion beam.

9. The method for plating a film on a memory device according to claim 3, wherein the step of plating the conductive film forms the conductive film by depositing one of tungsten, cobalt, copper, or aluminum using a focused ion beam.

10. The method of coating a memory device according to claim 3, wherein the step of coating the conductive lines uses a focused ion beam to deposit one of tungsten, cobalt, copper, or aluminum to form the conductive lines.