CN113300829B - SM3 algorithm hardware implementation device - Google Patents
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Abstract
The invention relates to a hardware implementation device of an SM3 algorithm, and belongs to the technical field of information security. The device comprises: 16 basic message word registers, first storing the initial 16 message words, then operating on the 16 basic message word registers in a 64-round expansion calculation for the SM3 algorithm, the operations comprising: non-reassignment operations of the 0 th to 11 th rounds, dynamic assignment operations of the 12 th to 63 th rounds: coding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and assigning the message word in the third dynamic message word register to the last basic message word register; and 3 dynamic message word registers for dynamically storing message words in each round of expansion calculation and dynamically updating the message words in each round. The device reduces the number of registers, further reduces the area of the hardware device, saves the cost and the power consumption, and has practical engineering application value.
Description
Technical Field
The invention relates to a hardware implementation device of an SM3 algorithm, and belongs to the technical field of information security.
Background
Hash functions formally introduce cryptography at the end of the seventies of the twentieth century, and were primarily used in message authentication applications in the early days. The method is a unidirectional cryptographic algorithm, has the characteristics of compression, simplicity, antigen root, collision resistance and the like, and ensures that the hash function is widely applied in the fields of cryptography and information security. Typical hash functions are SHA-1, SHA-2, MD4, MDS, SM2, SM3, etc.
The SM3 cryptographic hash algorithm can meet the security requirements of various cryptographic algorithm applications, such as: the message verification code is generated and verified through the SM3 hash algorithm, the digital signature and verification are generated through the SM3 hash algorithm, and meanwhile, a required hash function and the like can be provided for the digital signature of the SM2 cryptographic algorithm. SM3 is widely used because of its high security, and SM3 is formally an international standard in 10 months of 2018.
At present, the information security technology is integrated into all aspects of society economy, life and the like, and the information security is now a safe box for guaranteeing the normal operation of the whole society. With the improvement and importance of information security requirements in various fields and industries and the high-speed development of integrated circuits, information security chips realized in a hardware form are widely applied to the internet of things security industry and the intelligent hardware market, and compared with encryption in a software form, hardware encryption has the advantages of higher security and higher encryption operation speed, and the disadvantage that chip cost and power consumption are increased when hardware encryption is realized.
In conclusion, the SM3 hardware implementation has a large practical engineering application value for the current Internet of things security industry and intelligent hardware market. However, because of the message expansion feature based on the SM3 cryptographic hash algorithm, 132 message words need to be expanded, so that the algorithm needs 132 32-bit message word registers implemented in hardware, resulting in an excessive hardware area and excessive chip cost during hardware design.
Disclosure of Invention
The purpose of the application is to provide a hardware implementation device of an SM3 algorithm, which is used for solving the problems of overlarge hardware area and overlarge cost when the existing SM3 algorithm is implemented on hardware.
In order to achieve the above object, the present application proposes a technical solution of a hardware implementation device of a first SM3 algorithm, where the device includes:
16 basic message word registers, first storing the initial 16 message words, then operating on the 16 basic message word registers in a 64-round expansion calculation for the SM3 algorithm, the operations comprising: the operation of no reassignment from round 0 to round 11 and the operation of dynamic assignment from round 12 to round 63 are as follows: coding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and assigning the message word in the third dynamic message word register to the last basic message word register;
the 3 dynamic message word registers are used for dynamically storing message words in each round of expansion calculation, and the dynamic updating process of the message words from round 0 to round 11 is as follows:
the dynamic updating process of the message words from the 12 th round to the 63 rd round comprises the following steps:
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register; w16 is a third dynamic message word register; WJ is the base message word register, j=0, 1, … …, 15.
The technical scheme of the hardware implementation device of the SM3 algorithm has the advantages that: the device only needs to set 19 registers, including 16 basic message word registers and 3 dynamic message word registers, completes SM3 algorithm through dynamic assignment rule, reduces the number of registers, further reduces the area of hardware device, saves cost and power consumption, and has practical engineering application value.
Further, each message word is 32 bits.
Further, before assigning the 16 basic message word registers, the method further includes the step of determining the number of data bits of the original message:
judging whether the bit number of the original message data meets the set bit, if not, filling in; if the number exceeds the set number, the message blocks are grouped according to the set number, and the remainder does not satisfy the filling of the set number.
Further, the system also comprises an interface module for receiving the original message data and outputting the encryption result of the SM3 algorithm.
Further, the system also comprises a FIFO storage module, wherein the FIFO storage module is connected with the interface module and is used for storing the original message data.
In addition, the application also provides a technical scheme of a hardware implementation device of the second SM3 algorithm, and the device comprises:
16 basic message word registers, first storing the initial 16 message words, then operating on the 16 basic message word registers in a 64-round expansion calculation for the SM3 algorithm, the operations comprising: the operation of no reassignment from round 0 to round 11 and the operation of dynamic assignment from round 12 to round 63 are as follows: encoding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and
assigning the result of (a) to the last basic message word register;
2 dynamic message word registers, which are used for dynamically storing message words in each round of expansion calculation, and the dynamic updating process of the message words from round 0 to round 11 is as follows:
the dynamic updating process of the message words from the 12 th round to the 63 rd round comprises the following steps:
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register; WJ is the base message word register, j=0, 1, … …, 15.
The technical scheme of the hardware implementation device of the second SM3 algorithm has the advantages that: according to the device, only 18 registers are needed to be arranged, each register comprises 16 basic message word registers and 2 dynamic message word registers, an SM3 algorithm is completed through a dynamic assignment rule, the number of one register is reduced on the basis of the first technical scheme, the area of a hardware device is further reduced, the cost and the power consumption are further saved, and the device has practical engineering application value.
Further, each message word is 32 bits.
Further, before assigning the 16 basic message word registers, the method further includes the step of determining the number of data bits of the original message:
judging whether the bit number of the original message data meets the set bit, if not, filling in; if the number exceeds the set number, the message blocks are grouped according to the set number, and the remainder does not satisfy the filling of the set number.
Further, the system also comprises an interface module for receiving the original message data and outputting the encryption result of the SM3 algorithm.
Further, the system also comprises a FIFO storage module, wherein the FIFO storage module is connected with the interface module and is used for storing the original message data.
Drawings
Fig. 1 is a block diagram of a hardware implementation device of the SM3 algorithm of the present invention;
FIG. 2 is a schematic diagram of initial assignment of 16 basic message word registers, dynamic message word registers Wt1 and Wt2 of the present invention;
FIG. 3 is a schematic diagram of dynamic assignment of registers in accordance with the present invention.
Detailed Description
Hardware implementation device of SM3 algorithm example 1:
the main conception of the invention is that the device adopts 16 basic message word registers and 3 dynamic message word registers, and is based on the characteristic of SM3 algorithm: in the calculation of 64 rounds, 16 basic message word registers do not carry out reassignment in the calculation of 0 round to 11 round, and from the calculation of 12 round, 16 basic message word registers carry out dynamic assignment.
The hardware implementation device of the SM3 algorithm, as shown in fig. 1, includes an interface module (AHB interface) for receiving the original Message data (Message) and outputting the encryption Result (Result), where the module can enable the SM3 module to be mounted on the AHB bus, and the SM3 module can be accessed through the AHB bus;
further comprises: the system comprises a FIFO storage module for storing original message Data, a Read Data & Shift Byte module for reading the original message Data and splicing the original message Data, a Padding module Padding1&0 for Padding Data, a Padding length for Padding plaintext length and a A valid block Data module for 512-bit segmentation of the Data, wherein the modules are all used for judging the Data written by an AHB bus and then correspondingly performing Data operation (such as Data Padding) required by an SM3 algorithm, so that the operation Data to be input into the SM3 module accords with the algorithm requirement of the SM 3; inputting effective operation data to the SM3 module;
after the effective operation data is subjected to SM3 calculation expansion in the SM3 module, the calculation encryption Result (Finnal Result) is output through the AHB interface module. The SM3 module includes 16 basic message word registers W0, W1, W2, W3, … …, W15, respectively, with WJ representing the basic message word registers in the following calculations, j=0, 1, … …, 15. The 3 dynamic message word registers are W16 (third dynamic message word register), wt1 (first dynamic message word register), wt2 (second dynamic message word register).
Specifically, the process of implementing the SM3 algorithm by the hardware implementation device is as follows:
1) Input original message data is acquired.
According to the requirements of SM3 algorithm: a message block divided into 512 bits into a set of 16 message words of 32 bits each. The SM3 algorithm needs to expand 16 message words to 132 message words, i.e. 116 message words, and 64 rounds of computation are performed during the expansion process.
The original 16 message words are calculated by assignment and are respectively W 0 、W 1 、W 2 、W 3 、……、W 15 The extended 116 message words are W respectively 16 、W 17 、W 18 、W 19 、……、W 67 、W 0' 、W 1' 、W 2' 、W 3' 、……、W 63' . Of the 64 rounds of calculation, round 0 calculates W 0' Calculation of W in round 1 1' Calculation of W for round 11, … … 16 And W is 11' First, the12 rounds of calculation W 17 And W is 12' Calculation of W in 13 th round 18 And W is 13' And so on, round 62 calculates W 67 And W is 62' Calculation of W in 63 rd round 63' Subsequent use of W j 、W j' Representing 132 message words.
2) Judging whether the input message data has 512 bits (namely setting bits according to the bit number of the message word), and supplementing less than 512 bits according to the requirement of an SM3 algorithm; over 512 bits, the packets are grouped according to 512 bits of a message block, and the rest of 512 bits are complemented according to the requirements of the SM3 algorithm.
3) The 512-bit message block is divided into 16 message words and the initial 16 message words are assigned to the 16 base message word registers W0, W1, W2, W3, … …, W15 as shown in fig. 2.
The assignment mode is as follows:
where "msg" represents a 512-bit message block.
4) The expansion calculation of 64 rounds is performed, and the expansion calculation of 64 rounds comprises two operations:
for unification with the subscript j of the message word, the 64 rounds of computation are defined as round 0 through round 63, i.e., j may represent the number of rounds of computation, where the first is the 16 base message word registers no reassignment operation.
After the calculation of the 0 th round to the 11 th round, the 16 basic message word registers of W0, W1, W2, W3, … … and W15 are not reassigned, and the 2 dynamic message word registers of Wt1 and Wt2 are reassigned after each round of calculation; the value in the dynamic message word register of W16 may be calculated according to the values in the basic message word registers of W0, W7, W13, W3, W10, specifically:
since the underlying message registers are not reassigned, W is in round 0-11The size assigned in the dynamic message word register of 16 is:
The 2 dynamic message word registers Wt1, wt2 are related to the values in the 16 underlying message registers as:
will W after round 0 calculation 0 Assigning to Wt1, W 0' Assigning the value to Wt2, … … and calculating W in 11 th round 11 Assigning to Wt1, W 11' Assigned to Wt2.
Where j=0, 1, … …, 11 is the subscript of the message word, and may also be used to represent the number of calculation rounds, j=0, representing the 0 th round of calculation.
Second dynamic assignment operation for 16 basic message word registers
In round 12 computation, the relationship between the values in the 2 dynamic message word registers and the other registers of Wt1 and Wt2 is:
as shown in FIG. 3, the 2 dynamic message word registers Wt1, wt2 respectively assign W 12 And W is 12' The specific assignment process is as follows:
w to be stored in dynamic message word register W16 16 And W stored in the base message word register W12 12 Obtaining W after exclusive OR 12' Assigned to Wt2, W stored in base message word register W12 12 Directly assigning to Wt1; simultaneously, the values in the W1, W2, W3, … … and W16 registers are shifted to the left by one register, and are respectively reassigned to the W0, W1, W2, W3, … … and W15 registers;
thereafter, the reassigned size W in W16 is calculated from the values in the basic message word registers W0, W7, W13, W3, W10 17 Since the value in the base message register has been left shifted to reassign value, the calculation formula for the specific message word is:
further calculate W 17 Assigned to the dynamic message word register W16.
In the 13 th round of calculation, the 2 dynamic message word registers Wt1 and Wt2 respectively store W 13 And W is 13' The specific assignment process is as follows:
w to be stored in dynamic message word register W16 17 And W stored in the base message word register W12 13 Obtaining W after exclusive OR 13' Assigned to Wt2, W stored in base message word register W12 13 Directly assigning to Wt1; simultaneously, the values in the W1, W2, W3, … … and W16 registers are shifted to the left by one register, and are respectively reassigned to the W0, W1, W2, W3, … … and W15 registers;
thereafter according to
Calculation of W 18 Assigned to the dynamic message word register W16.
And so on, in round 62 computation, W stored in dynamic message word register W16 66 And W stored in the base message word register W12 62 Obtaining W after exclusive OR 62' Assigned to Wt2, W stored in base message word register W12 62 Directly assigning to Wt1; simultaneously, the values in the W1, W2, W3, … … and W16 registers are shifted to the left by one register, and are respectively reassigned to W0,W1, W2, W3, … …, W15 registers;
thereafter according to
Calculation of W 67 Assigned to the dynamic message word register W16.
In round 63 computation, W stored in dynamic message word register W16 67 And W stored in the base message word register W12 63 Obtaining W after exclusive OR 63 ' assigned to Wt2, W stored in base message word register W12 63 Directly assigning to Wt1; and simultaneously, the values in the W1, W2, W3, … … and W16 registers are shifted one register to the left, and are respectively reassigned to the W0, W1, W2, W3, … … and W15 registers, so that the calculation is finished, and the expansion of 64 rounds and 132 message words is completed.
To sum up, the rule of dynamic assignment of the 16 basic message word registers of the 12 th round to the 63 rd round is summarized as follows: the 16 basic message word registers are encoded in sequence, the assignment in the next basic message word register is given to the previous basic message word register, and the message word of W16 in the dynamic message word register is given to the last basic message word register.
The process of calculating assignments with respect to the 3 dynamic message word registers W16, wt1, wt2 and the relationships with other underlying message word registers, and from the message words, is as follows:
where j=12, 13, … …, 63 is the subscript of the message word, and may also be used to represent the number of calculation rounds, j=12, represent round 12 calculation, and P1 is a permutation function.
The stored values of the 16 basic message word registers W0, W1, W2, W3, … …, W15 and the 3 dynamic message word registers W16, wt1, wt2 after the 12 th round of calculation are:
the values stored in the 16 basic message word registers W0, W1, W2, W3, … …, W15 and the 3 dynamic message word registers W16, wt1, wt2 after the 13 th round of calculation are:
and similarly, the message word expansion of 64 rounds is completed.
Before each round of calculation assignment is performed, the value of output A, B, C, D, E, F, G, H is calculated from the message word stored in the register, with the following calculation formula:
SS1＝((A＜＜＜12)+E+(T j ＜＜＜j))＜＜＜7；
TT1＝FF j (A,B,C)+D+SS2+Wt2；
TT2＝GG j (E,F,G)+H+SS1+Wt1；
A＝TT1；
B＝A；
C＝B＜＜＜9；
D＝C；
E＝P0(TT2)；
F＝E；
G＝F＜＜＜19；
H＝G；
Wt1＝W j ；
wherein T is j Is constant, FF j (A,B,C)、GG j (E, F, G) is a Boolean function, P0, P1 are permutation functions, as shown below, "<" is a cyclic shift left symbol,
is an exclusive or symbol.
For example: after the 12 th round of calculation is finished, W is respectively stored in the 2 dynamic message word registers Wt1 and Wt2 12 And W is 12' Wheel 13 is first according to W 12 And W is 12' Calculate A, B, C, D, E, F, G, H, then calculate W 13' Then the assignment operation of each register is carried out, the 13 th round of calculation is finished, and W is respectively stored in Wt1 and Wt2 13 And W is 13' 。
5) Finally according to the calculated W of the 63 rd round 67 And W is 63' And outputting the final A, B, C, D, E, F, G, H in the 64 th round and performing exclusive OR calculation with the initialization parameters, and splicing the obtained results to obtain the final encryption result.
Calculated W due to round 0 0' Calculation A, B, C, D, E, F, G, H will be performed on round 1; thus, from round 1Each calculation by round 64 outputs A, B, C, D, E, F, G, H of one round, but in round 64, the calculation A, B, C, D, E, F, G, H is only calculated according to the values stored in the registers after the calculation by round 63 is finished, and only the calculation result obtained by round 64 is applied in the final output calculation, and after the encryption result is obtained, the SM3 algorithm calculation is finished.
In the above embodiment, the technology of the interface module is mature, and the corresponding modules with the same functions in the prior art can be adopted. Other memory modules may also be used in relation to the memory module, for example: memory storage modules, etc., to which the present invention is not limited.
In the above embodiment, due to the requirement of the SM3 algorithm, the step of determining the number of bits of the message data in step 2) may be performed without determining if the message data is 512 bits.
The invention realizes SM3 algorithm by the hardware realization device with 19 registers, reduces the number of registers, further reduces the area of the hardware realization device and saves the cost.
Hardware implementation device of SM3 algorithm example 2:
the hardware implementation device of this embodiment is different from embodiment 1 in the number of registers, and includes 16 basic message word registers and 2 dynamic message word registers, so that the number of dynamic message word registers W16 is reduced, the area of the hardware implementation device is reduced, and the cost is saved. Other structures of the hardware implementation device are the same as those of embodiment 1, and are not described here.
For this purpose, the hardware implementation method of the SM3 algorithm is in an extended 64-round calculation:
16 basic message word registers, first storing the initial 16 message words, then operating on the 16 basic message word registers in a 64-round expansion calculation for the SM3 algorithm, the operations comprising: the operation of no reassignment from round 0 to round 11 and the operation of dynamic assignment from round 12 to round 63 are as follows: words of 16 basic messagesThe memory encodes in sequence, assigns the message word in the next basic message word register to the previous basic message word register, and assigns
Assigning the result of (a) to the last basic message word register; the same as the assignment calculation of the dynamic message word register W16 in embodiment 1, but the calculation result is directly assigned here, without a special dynamic message word register.
2 dynamic message word registers, which are used for dynamically storing message words in each round of expansion calculation, and the dynamic update process of each round of message words is as follows:
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register.
The process of dynamically assigning 2 dynamic message word registers and assigning 16 basic message word registers is the same as in embodiment 1, and will not be described here.
Claims (10)
1. A hardware implementation device of SM3 algorithm, comprising:
16 basic message word registers, first storing the initial 16 message words, then operating on the 16 basic message word registers in a 64-round expansion calculation for the SM3 algorithm, the operations comprising: the operation of no reassignment from round 0 to round 11 and the operation of dynamic assignment from round 12 to round 63 are as follows: coding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and assigning the message word in the third dynamic message word register to the last basic message word register;
the 3 dynamic message word registers are used for dynamically storing message words in each round of expansion calculation, and the dynamic updating process of the message words from round 0 to round 11 is as follows:
the dynamic updating process of the message words from the 12 th round to the 63 rd round comprises the following steps:
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register; w16 is a third dynamic message word register; WJ is the base message word register, j=0, 1, … …, 15; p1 is a permutation function.
2. The SM3 algorithm hardware implementation of claim 1, wherein each message word is 32 bits.
3. The hardware implementation device of the SM3 algorithm according to claim 1 or 2, further comprising the step of determining the number of original message data bits before assigning the 16 basic message word registers:
judging whether the bit number of the original message data meets the set bit, if not, filling in; if the number exceeds the set number, the message blocks are grouped according to the set number, and the remainder does not satisfy the filling of the set number.
4. The hardware implementation device of the SM3 algorithm according to claim 1 or 2, further comprising an interface module for receiving the original message data and outputting the encryption result of the SM3 algorithm.
5. The SM3 algorithm hardware implementation device of claim 4, further comprising a FIFO storage module connected to the interface module for storing the raw message data.
6. A hardware implementation device of SM3 algorithm, comprising:
16 basic message word registers, first storing the initial 16 message words, then operating on the 16 basic message word registers in a 64-round expansion calculation for the SM3 algorithm, the operations comprising: the operation of no reassignment from round 0 to round 11 and the operation of dynamic assignment from round 12 to round 63 are as follows: encoding the 16 basic message word registers in sequence, assigning the message word in the next basic message word register to the previous basic message word register, and
assigning the result of (a) to the last basic message word register;
2 dynamic message word registers, which are used for dynamically storing message words in each round of expansion calculation, and the dynamic updating process of the message words from round 0 to round 11 is as follows:
the dynamic updating process of the message words from the 12 th round to the 63 rd round comprises the following steps:
wherein Wt1 is a first dynamic message word register; wt2 is a second dynamic message word register; WJ is the base message word register, j=0, 1, … …, 15; p1 is a permutation function.
7. The SM3 algorithm hardware implementation of claim 6, wherein each message word is 32 bits.
8. The SM3 algorithm hardware implementation device according to claim 6 or 7, further comprising the step of determining the number of original message data bits before assigning the 16 basic message word registers:
judging whether the bit number of the original message data meets the set bit, if not, filling in; if the number exceeds the set number, the message blocks are grouped according to the set number, and the remainder does not satisfy the filling of the set number.
9. The hardware implementation device of the SM3 algorithm according to claim 6 or 7, further comprising an interface module for receiving the original message data and outputting the encryption result of the SM3 algorithm.
10. The hardware implementation of the SM3 algorithm of claim 9, further comprising a FIFO storage module connected to the interface module for storing the raw message data.
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