CN113299241A - GOA circuit, GOA circuit driving method and display panel - Google Patents
GOA circuit, GOA circuit driving method and display panel Download PDFInfo
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- CN113299241A CN113299241A CN202110559906.7A CN202110559906A CN113299241A CN 113299241 A CN113299241 A CN 113299241A CN 202110559906 A CN202110559906 A CN 202110559906A CN 113299241 A CN113299241 A CN 113299241A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the application provides a GOA circuit, a GOA circuit driving method and a display panel, and relates to the technical field of electronics. Meanwhile, the capacitor bootstrap voltage blocking sub-circuit is in a closed state after the STV input is finished, the capacitor leakage current of the bootstrap capacitor can be further reduced, the influence of GOA noise is reduced, and the design of a GOA noise reduction circuit is saved.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a GOA circuit, a GOA circuit driving method, and a display panel.
Background
GOA (Gate Driver on Array) driving of an AMOLED (Active-Matrix Organic Light Emitting Diode) display product has advantages of low cost and narrow frame compared to IC (Integrated Circuit) driving, and has been increasingly widely used in Mobile products. Moreover, the existing OLED flexible products are increasingly applied to vehicle-mounted and outdoor wearable products, and high voltage easily causes reliability failures of TFTs (Thin Film transistors) of the GOA circuit, such as NBTS (negative bias temperature stress) and PBTS (positive bias temperature stress) failures, so that the products have the conditions of screen splitting, abnormal display and the like, and finally the products cannot normally display.
The reliability failure of the field effect transistor mainly occurs on a node with large voltage, a capacitor bootstrap design generally exists in a GOA circuit, the gate voltage of a low-level output tube is pulled down through the capacitor bootstrap, the capacitor bootstrap can cause a very low bootstrap voltage (generally-20V) to locally appear, the design is to enable the specified field effect transistor to be completely turned on, so that the low voltage (generally-7V) is ensured to be completely output, but the bootstrap voltage easily causes the voltage of other field effect transistors to be large, and the reliability failure of other field effect transistors is caused.
Disclosure of Invention
Embodiments of the present disclosure provide a GOA circuit, a GOA circuit driving method, and a display panel, so as to reduce abnormal display. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a GATE GOA circuit, including:
the control sub-circuit, the first output sub-circuit, the second output sub-circuit and the capacitor bootstrap voltage blocking sub-circuit;
the first end of the control sub-circuit is connected with the first output sub-circuit, and the second end of the control sub-circuit is connected with the first end of the capacitor bootstrap voltage blocking sub-circuit;
the second end of the capacitor bootstrap voltage blocking sub-circuit is connected with the second output sub-circuit;
the control sub-circuit is configured to control outputs of the first output sub-circuit and the second output sub-circuit, the second output sub-circuit is a sub-circuit having a capacitor bootstrap function, and the capacitor bootstrap voltage blocking sub-circuit is configured to block a bootstrap voltage flowing to the second output sub-circuit of the control sub-circuit.
In a possible implementation manner, the capacitor bootstrap voltage blocking sub-circuit includes a sixth MOS transistor, a first end of the sixth MOS transistor is connected to the second end of the control sub-circuit, a second end of the sixth MOS transistor is connected to the second output sub-circuit, and a gate of the sixth MOS transistor is connected to a GCK line.
In a possible implementation manner, the control sub-circuit comprises a first MOS transistor, a second MOS transistor and a third MOS transistor;
the first output sub-circuit comprises a fourth MOS tube and a first capacitor;
the second output sub-circuit comprises a fifth MOS tube and a second capacitor;
the first end of the first MOS tube is connected with a GSTV circuit, the second end of the first MOS tube is connected with the grid electrode of the second MOS tube, the second end of the first MOS tube is also connected with the first end of the sixth MOS tube, and the grid electrode of the first MOS tube is connected with a GCK circuit;
the first end of the second MOS tube is connected with the GCK circuit, and the second end of the second MOS tube is respectively connected with the second end of the third MOS tube, the first end of the first capacitor and the grid electrode of the fourth MOS tube;
the first end of the third MOS tube is connected with a VGL circuit, and the grid electrode of the third MOS tube is connected with the GCK circuit;
a second end of the fourth MOS tube is respectively connected with a VGH circuit and a second end of the first capacitor, and a first end of the fourth MOS tube is respectively connected with an output circuit, a second end of the second capacitor and a second end of the fifth MOS tube;
the first end of the fifth MOS tube is connected with a GCB circuit, and the grid electrode of the fifth MOS tube is respectively connected with the first end of the second capacitor and the second end of the sixth MOS tube;
and the grid electrode of the sixth MOS tube is connected with the GCK circuit.
In a possible implementation manner, the first MOS transistor is a thin film transistor with a double-gate structure, and the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are thin film transistors with a single-gate structure.
In a possible implementation manner, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are P-type MOS transistors.
In a second aspect, an embodiment of the present application provides a GATE GOA circuit driving method, which is applied to any one of the GATE GOA circuits in the present application, and the method includes:
a GSTV line inputs a low level signal in a T1 period, a GCK line inputs a low level signal, and a GCB line inputs a high level signal;
a GSTV circuit inputs a high level signal in a T2 period, a GCK circuit inputs a high level signal, and a GCB circuit inputs a low level signal;
a GSTV line inputs a high level signal in a T3 period, a GCK line inputs a low level signal, and a GCB line inputs a high level signal;
the GSTV line receives a high-level signal, the GCK line receives a high-level signal, and the GCB line receives a low-level signal in a period of T4.
In a third aspect, an embodiment of the present application provides an EM GOA circuit, including:
the circuit comprises a first control sub-circuit, a second control sub-circuit, a first output sub-circuit, a second output sub-circuit and a capacitor bootstrap voltage blocking sub-circuit;
the first end of the first control sub-circuit is connected with the first output sub-circuit, and the second end of the first control sub-circuit is connected with the first end of the capacitor bootstrap voltage blocking sub-circuit;
the second end of the capacitor bootstrap voltage blocking sub-circuit is connected with the first end of the second control sub-circuit;
the first end of the second control sub-circuit is connected with the second output sub-circuit;
the first control sub-circuit is configured to control an output of the first output sub-circuit, the first control sub-circuit and the second control sub-circuit are configured to control an output of the second output sub-circuit, the second control sub-circuit is a sub-circuit having a capacitor bootstrap function, and the capacitor bootstrap voltage blocking sub-circuit is configured to block a bootstrap voltage flowing to the second control sub-circuit of the first control sub-circuit.
In a possible implementation manner, the capacitor bootstrap voltage blocking sub-circuit includes a seventh MOS transistor, a first end of the seventh MOS transistor is connected to the second end of the first control sub-circuit, a second end of the seventh MOS transistor is connected to the first end of the second control sub-circuit, and a gate of the seventh MOS transistor is connected to the ECK line.
In a possible implementation manner, the first control sub-circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a third capacitor;
the second control sub-circuit comprises an eighth MOS tube and a second capacitor;
the first output sub-circuit comprises a ninth MOS tube and a first capacitor;
the second output sub-circuit comprises a tenth MOS tube;
the first end of the first MOS tube is connected with the ESTV circuit, the second end of the first MOS tube is respectively connected with the grid electrode of the second MOS tube, the grid electrode of the sixth MOS tube and the first end of the seventh MOS tube, and the grid electrode of the first MOS tube is connected with the ECK circuit;
the first end of the second MOS tube is connected with the ECK circuit, and the second end of the second MOS tube is respectively connected with the second end of the third MOS tube, the first end of the third capacitor and the grid electrode of the fourth MOS tube;
the first end of the third MOS tube is connected with a VGL line, and the grid electrode of the third MOS tube is connected with the ECK line;
the second end ECB line of the fourth MOS tube is connected, and the first end of the fourth MOS tube is respectively connected with the second end of the third capacitor and the first end of the fifth MOS tube;
the second end of the fifth MOS tube is connected with the second end of the sixth MOS tube, the first end of the first capacitor and the grid electrode of the ninth MOS tube respectively, and the grid electrode of the fifth MOS tube is connected with the ECB circuit;
the first end of the sixth MOS tube is connected with a VGH circuit;
a second end of the seventh MOS transistor is connected to a gate of the eighth MOS transistor, a second end of the second capacitor, and a gate of the tenth MOS transistor, respectively, and the gate of the seventh MOS transistor is connected to the ECK line;
the first end of the eighth MOS tube is connected with the ECB line, and the second end of the eighth MOS tube is connected with the first end of the second capacitor;
a first end of the ninth MOS tube is respectively connected with an input circuit and a second end of the tenth MOS tube, and a second end of the ninth MOS tube is respectively connected with a second end of the first capacitor and the VGH circuit;
and the first end of the tenth MOS tube is connected with a VGL circuit.
In a possible implementation manner, the first MOS transistor is a thin film transistor with a dual-gate structure, and the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are thin film transistors with a single-gate structure.
In a possible implementation manner, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are P-type MOS transistors.
In a fourth aspect, an embodiment of the present application provides an EM GOA circuit driving method, which is applied to the EM GOA circuit described in any of the present applications, and the method includes:
t1 period ESTV line inputs high level signal, ECK line inputs low level signal, ECB line inputs high level signal;
t2 period ESTV line inputs high level signal, ECK line inputs high level signal, ECB line inputs low level signal;
t3 period ESTV line inputs high level signal, ECK line inputs low level signal, ECB line inputs high level signal;
t4 period ESTV line input low level signal, ECK line input high level signal, ECB line input low level signal;
t5 period ESTV line input low level signal, ECK line input low level signal, ECB line input high level signal;
t6 cycle ESTV line inputs low level signal, ECK line inputs high level signal, ECB line inputs low level signal.
In a fifth aspect, an embodiment of the present application provides a display panel, including any one of the GATE GOA circuits and/or any one of the EM GOA circuits described in the present application.
The embodiment of the application has the following beneficial effects:
the GOA circuit, the GOA circuit driving method and the display panel provided by the embodiment of the application have the advantages that the capacitor bootstrap voltage blocking sub-circuit is added between the sub-circuit with the capacitor bootstrap function and the control sub-circuit, the capacitor bootstrap voltage blocking sub-circuit is utilized to block the bootstrap voltage flowing to the control sub-circuit, the situation that the reliability of a field effect transistor in the control sub-circuit is invalid due to the fact that too low voltage generated by capacitor bootstrap can be prevented, and therefore the situation of abnormal display is reduced. Meanwhile, the capacitor bootstrap voltage blocking sub-circuit is in a closed state after the STV input is finished, the capacitor leakage current of the bootstrap capacitor can be further reduced, the influence of GOA noise is reduced, and the design of a GOA noise reduction circuit is saved. Of course, not all advantages described above need to be achieved at the same time in the practice of any one product or method of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a first schematic diagram of a GATE GOA circuit according to an embodiment of the present invention;
FIG. 2 is a second schematic diagram of a GATE GOA circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a timing diagram of a GATE GOA circuit according to an embodiment of the present invention;
FIG. 4 is a third schematic diagram of a GATE GOA circuit according to an embodiment of the present invention;
FIG. 5 is a first schematic diagram of an EM GOA circuit according to an embodiment of the present application;
FIG. 6 is a second schematic diagram of an EM GOA circuit in accordance with an embodiment of the present application;
FIG. 7 is a schematic diagram of a timing diagram of an EM GOA circuit according to an embodiment of the present application; (ii) a
Fig. 8 is a third schematic diagram of an EM GOA circuit according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the description herein are intended to be within the scope of the present disclosure.
In order to reduce the situation of reliability failure of the field effect transistor and reduce the display problem, the embodiment of the present application provides a GATE GOA circuit, which is shown in fig. 1 and includes:
the control sub-circuit, the first output sub-circuit, the second output sub-circuit and the capacitor bootstrap voltage blocking sub-circuit;
the first end of the control sub-circuit is connected with the first output sub-circuit, and the second end of the control sub-circuit is connected with the first end of the capacitor bootstrap voltage blocking sub-circuit;
the second end of the capacitor bootstrap voltage blocking sub-circuit is connected with the second output sub-circuit;
the control sub-circuit is configured to control outputs of the first output sub-circuit and the second output sub-circuit, the second output sub-circuit is a sub-circuit having a capacitor bootstrap function, and the capacitor bootstrap voltage blocking sub-circuit is configured to block a bootstrap voltage flowing to the second output sub-circuit of the control sub-circuit.
The second output sub-circuit is a sub-circuit with a capacitance bootstrap function and comprises at least one capacitor, the second output sub-circuit can generate bootstrap voltage in a capacitance bootstrap stage in the second output sub-circuit, and the capacitance bootstrap voltage blocking sub-circuit can block the bootstrap voltage flowing to the control sub-circuit, so that the condition that the reliability of a field effect transistor in the control sub-circuit is invalid due to too low voltage generated by capacitance bootstrap can be reduced, and the condition of abnormal display is reduced. Meanwhile, the capacitor bootstrap voltage blocking sub-circuit is in a closed state after the STV input is finished, the capacitor leakage current of the bootstrap capacitor can be further reduced, the influence of GOA noise is reduced, and the design of a GOA noise reduction circuit is saved.
In a possible implementation manner, the capacitor bootstrap voltage blocking sub-circuit includes a sixth MOS transistor, a first end of the sixth MOS transistor is connected to the second end of the control sub-circuit, a second end of the sixth MOS transistor is connected to the second output sub-circuit, and a gate of the sixth MOS transistor is connected to a GCK line.
The MOS Transistor (Metal Oxide Semiconductor Field Effect Transistor) has a circuit blocking capability, in one example, the sixth MOS Transistor is a P-type MOS Transistor, a source of the sixth MOS Transistor is connected to the second output sub-circuit, and a capacitor bootstrap voltage of the second output sub-circuit is less than a gate voltage (voltage of the GCK line) of the sixth MOS Transistor, so that the capacitor bootstrap voltage flowing to the control sub-circuit can be blocked.
In a possible implementation, referring to fig. 2, the control sub-circuit includes a first MOS transistor T1, a second MOS transistor T2, and a third MOS transistor T3;
the first output sub-circuit comprises a fourth MOS transistor T4 and a first capacitor C1;
the second output sub-circuit comprises a fifth MOS transistor T5 and a second capacitor C2;
a first end of the first MOS transistor T1 is connected to a GSTV line, a second end of the first MOS transistor T1 is connected to a gate of the second MOS transistor T2, a second end of the first MOS transistor T1 is further connected to a first end of the sixth MOS transistor T6, and a gate of the first MOS transistor T1 is connected to a GCK line;
a first end of the second MOS transistor T2 is connected to the GCK line, and a second end of the second MOS transistor T2 is connected to a second end of the third MOS transistor T3, a first end of the first capacitor C1, and a gate of the fourth MOS transistor T4, respectively;
a first end of the third MOS transistor T3 is connected to a VGL line, and a gate of the third MOS transistor T3 is connected to the GCK line;
a second terminal of the fourth MOS transistor T4 is connected to a VGH line and a second terminal of the first capacitor C1, respectively, and a first terminal of the fourth MOS transistor T4 is connected to an Output (OUT) line, a second terminal of the second capacitor C2, and a second terminal of the fifth MOS transistor T5, respectively;
a first end of the fifth MOS transistor T5 is connected to a GCB line, and a gate of the fifth MOS transistor T5 is connected to a first end of the second capacitor T2 and a second end of the sixth MOS transistor T6, respectively;
the gate of the sixth MOS transistor T6 is connected to the GCK line.
Where N1, N2, N3 denote points in the circuit, not the device. For any MOS transistor in the GATE GOA circuit of the present application, a first end of the MOS transistor is a source or a drain, and a second end of the MOS transistor is a drain or a source corresponding to the first end.
GSTV represents the row-driving clock signal of GATE; GCK represents a first gate clock signal; the GCB represents a second gate clock signal, the duty ratio of the first gate clock signal and the second gate clock signal may be the same, and the second gate clock signal is delayed from the first gate clock signal by a set time period, so that the first gate clock signal and the second gate clock signal are not low voltage at the same time. For example, the second gate clock signal is delayed by 1H from the first gate clock signal, where H is the duration required for the data signal to refresh a row of pixels; VGL represents a low potential of a Gate (Gate), and is a voltage for turning on the Gate with respect to the P-type MOS transistor VGL; VGH represents the high potential of the gate, and VGH is the gate-off voltage for the P-type MOS transistor VGH.
In the application, a MOS Transistor is added between N1 and N3 points, specifically, a Thin Film Transistor (TFT) is used for control, and a GCK signal is used to prevent the T1 and T2 reliability failure due to too low voltage generated by capacitor bootstrap. Meanwhile, the MOS tube is in a closed state after STV input is finished, the size of leakage current of a C2 capacitor can be further reduced, the influence of GOA noise is reduced, and the design of a GOA noise reduction circuit is saved.
In a possible implementation manner, the first MOS transistor is a thin film transistor with a double-gate structure, and the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are thin film transistors with a single-gate structure.
In a possible implementation manner, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are P-type MOS transistors.
For the GATE GOA circuit in the present application, an embodiment of the present application further provides a GATE GOA circuit driving method, including:
a GSTV line inputs a low level signal in a T1 period, a GCK line inputs a low level signal, and a GCB line inputs a high level signal;
a GSTV circuit inputs a high level signal in a T2 period, a GCK circuit inputs a high level signal, and a GCB circuit inputs a low level signal;
a GSTV line inputs a high level signal in a T3 period, a GCK line inputs a low level signal, and a GCB line inputs a high level signal;
the GSTV line receives a high-level signal, the GCK line receives a high-level signal, and the GCB line receives a low-level signal in a period of T4.
The driving timing diagram of the GATE GOA circuit in the GATE GOA circuit embodiment of the present application can be shown in fig. 3, where N1 and N2 respectively represent the voltage signals at the N1 point and the N2 point, and OUT represents the voltage signal of the output line.
The GSTV signal is input in a period T1, the GSTV signal is input in a period T2, the GSTV signal is input in periods T3 and T4, the GCK and GCB levels are alternately changed, the output voltage is a low level signal in a period T2, and the input current is a high level signal in periods T1, T3, and T4.
Period T1: t1, T2, T3, T4, T5 and T6 are turned on, GCB is high, and T4 and T5 output high in common.
Period T2: t1, T3, T6 are off, T2 is on (N3 is affected by parasitic capacitance and the state is unchanged), GCK is high input to N2, T4 is off, T5 is on, GCB is low, and low is output.
Period T3: t1, T3, T6 on, T2, T5 off, T4 on, output high.
Period T4: t1, T2, T3, T6 off, T4 on, T5 off, output high.
The period of T2 is a low level output period, GCK is a high level, GCB is a low level, since T6 is turned off, the voltage of N3 is still about-7V, and the large voltage of N1 point does not affect the N3 point, thereby reducing abnormal display conditions.
In one example, the layout of the GATE GOA circuit in the embodiment of the present application can be as shown in fig. 4, where T1 is a double-GATE structure, the rest TFTs are single GATEs, and the purpose of T4 and T5 is to output signals, so the widths and lengths of T4 and T5 are relatively large.
In one example, VGL is DC voltage-7V, VGH is DC voltage 7V, GCK and GCB are a set of inverted Clock signals, and similarly high is 7V and low is-7V. T1 is a double gate TFT, functioning as an input for the GSTV signal; t2 is a single gate for GCK signal input to N2 point; t3 is a reset TFT at N2 point, and the grid is GCK; t4 and T5 are output MOS tubes, T4 outputs high level, T5 outputs low level; t6 is a TFT controlled by a GCK ac signal, prevents a large voltage of N1 from being transmitted to T1, and reduces leakage of a C2 capacitor, thereby reducing circuit noise.
The embodiment of the present application further provides an EM (indicating an emission voltage) GOA circuit, referring to fig. 5, including:
the circuit comprises a first control sub-circuit, a second control sub-circuit, a first output sub-circuit, a second output sub-circuit and a capacitor bootstrap voltage blocking sub-circuit;
the first end of the first control sub-circuit is connected with the first output sub-circuit, and the second end of the first control sub-circuit is connected with the first end of the capacitor bootstrap voltage blocking sub-circuit;
the second end of the capacitor bootstrap voltage blocking sub-circuit is connected with the first end of the second control sub-circuit;
the first end of the second control sub-circuit is connected with the second output sub-circuit;
the first control sub-circuit is configured to control an output of the first output sub-circuit, the first control sub-circuit and the second control sub-circuit are configured to control an output of the second output sub-circuit, the second control sub-circuit is a sub-circuit having a capacitor bootstrap function, and the capacitor bootstrap voltage blocking sub-circuit is configured to block a bootstrap voltage flowing to the second control sub-circuit of the first control sub-circuit.
In a possible implementation manner, the capacitor bootstrap voltage blocking sub-circuit includes a seventh MOS transistor, a first end of the seventh MOS transistor is connected to the second end of the first control sub-circuit, a second end of the seventh MOS transistor is connected to the first end of the second control sub-circuit, and a gate of the seventh MOS transistor is connected to the ECK line.
In a possible implementation, referring to fig. 6, the first control sub-circuit includes a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3, a fourth MOS transistor T4, a fifth MOS transistor T5, a sixth MOS transistor T6, and a third capacitor C3;
the second control sub-circuit comprises an eighth MOS transistor T8 and a second capacitor C2;
the first output sub-circuit comprises a ninth MOS transistor T9 and a first capacitor C1;
the second output sub-circuit comprises a tenth MOS tube T10;
the first end of the first MOS tube is connected with the ESTV circuit, the second end of the first MOS tube is respectively connected with the grid electrode of the second MOS tube, the grid electrode of the sixth MOS tube and the first end of the seventh MOS tube, and the grid electrode of the first MOS tube is connected with the ECK circuit;
the first end of the second MOS tube is connected with the ECK circuit, and the second end of the second MOS tube is respectively connected with the second end of the third MOS tube, the first end of the third capacitor and the grid electrode of the fourth MOS tube;
the first end of the third MOS tube is connected with a VGL line, and the grid electrode of the third MOS tube is connected with the ECK line;
the second end ECB line of the fourth MOS tube is connected, and the first end of the fourth MOS tube is respectively connected with the second end of the third capacitor and the first end of the fifth MOS tube;
the second end of the fifth MOS tube is connected with the second end of the sixth MOS tube, the first end of the first capacitor and the grid electrode of the ninth MOS tube respectively, and the grid electrode of the fifth MOS tube is connected with the ECB circuit;
the first end of the sixth MOS tube is connected with a VGH circuit;
a second end of the seventh MOS transistor is connected to a gate of the eighth MOS transistor, a second end of the second capacitor, and a gate of the tenth MOS transistor, respectively, and the gate of the seventh MOS transistor is connected to the ECK line;
the first end of the eighth MOS tube is connected with the ECB line, and the second end of the eighth MOS tube is connected with the first end of the second capacitor;
a first end of the ninth MOS tube is respectively connected with an input circuit and a second end of the tenth MOS tube, and a second end of the ninth MOS tube is respectively connected with a second end of the first capacitor and the VGH circuit;
and the first end of the tenth MOS tube is connected with a VGL circuit.
Wherein ESTV represents the row drive clock signal of EM; ECK represents a first EM clock signal; ECB represents a second EM clock signal, the duty cycle of the first EM clock signal and the second EM clock signal may be the same, and the second EM clock signal is delayed from the first EM clock signal by a set time period, so that the first EM clock signal and the second EM clock signal are not low voltage at the same time. For example, the second EM clock signal is delayed from the first EM clock signal by 1H, which is the length of time required for the data signal to refresh a row of pixels. For any MOS transistor in the EM GOA circuit of the present application, a first end of the MOS transistor is a source or a drain, and a second end of the MOS transistor is a drain or a source corresponding to the first end.
In a possible implementation manner, the first MOS transistor is a thin film transistor with a dual-gate structure, and the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are thin film transistors with a single-gate structure.
In a possible implementation manner, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are P-type MOS transistors.
For the EM GOA circuit in the present application, an embodiment of the present application further provides a driving method for the EM GOA circuit, including:
t1 period ESTV line inputs high level signal, ECK line inputs low level signal, ECB line inputs high level signal;
t2 period ESTV line inputs high level signal, ECK line inputs high level signal, ECB line inputs low level signal;
t3 period ESTV line inputs high level signal, ECK line inputs low level signal, ECB line inputs high level signal;
t4 period ESTV line input low level signal, ECK line input high level signal, ECB line input low level signal;
t5 period ESTV line input low level signal, ECK line input low level signal, ECB line input high level signal;
t6 cycle ESTV line inputs low level signal, ECK line inputs high level signal, ECB line inputs low level signal.
Fig. 7 shows a driving timing diagram of the EM GOA circuit in the EM GOA circuit embodiment of the present application, where N1 and N2 respectively represent voltage signals at points N1 and N2, and OUT represents a voltage signal of an output line.
In one example, the layout of the EM GOA circuit in the embodiment of the present application can be as shown in fig. 8, T1 is a double-gate structure, the rest TFTs are single gates, and the purpose of T9 and T10 is to output signals, so the widths and lengths of T9 and T10 are relatively large.
Period T1: t1, T3, T4, T7 open; t2, T5, T6, T8, T9, T10 off; o isut is the same as the previous state, and outputs a low level.
Period T2: t4, T5, T9 open; t1, T2, T3, T6, T7, T8, T10 off; and outputting a high level.
Period T3: t1, T3, T4, T7, T9 open; t2, T5, T6, T8, T10 off; and outputting a high level.
Period T4: t4, T5, T9 open; t1, T2, T3, T6, T7, T8, T10 off; and outputting a high level.
Period T5: t1, T2, T3, T4, T6, T7, T8, T10 open; t5, T9 closed; outputting a low level;
period T6: t2, T5, T6, T10 open; t1, T3, T4, T7, T8, T9 off; and outputting a low level.
In the low level stage, the voltage at the point N3 is maintained at about-7V, which prevents the T1 and T2 tubes from reliability failure.
The embodiment of the application also provides a display panel, which comprises any GATE GOA circuit. For other parts of the display panel, reference may be made to the display panel in the related art, and no specific limitation is made in this application.
The embodiment of the application also provides a display panel, which comprises the EM GOA circuit. For other parts of the display panel, reference may be made to the display panel in the related art, and no specific limitation is made in this application.
It should be noted that, in this document, the technical features in the various alternatives can be combined to form the scheme as long as the technical features are not contradictory, and the scheme is within the scope of the disclosure of the present application. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present specification are described in a related manner, each embodiment focuses on differences from other embodiments, and the same and similar parts in the embodiments are referred to each other.
The above description is only for the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (11)
1. A GATE GOA circuit, comprising:
the control sub-circuit, the first output sub-circuit, the second output sub-circuit and the capacitor bootstrap voltage blocking sub-circuit;
the first end of the control sub-circuit is connected with the first output sub-circuit, and the second end of the control sub-circuit is connected with the first end of the capacitor bootstrap voltage blocking sub-circuit;
the second end of the capacitor bootstrap voltage blocking sub-circuit is connected with the second output sub-circuit;
the control sub-circuit is configured to control outputs of the first output sub-circuit and the second output sub-circuit, the second output sub-circuit is a sub-circuit having a capacitor bootstrap function, and the capacitor bootstrap voltage blocking sub-circuit is configured to block a bootstrap voltage flowing to the second output sub-circuit of the control sub-circuit.
2. The circuit of claim 1, wherein the capacitor bootstrap voltage blocking sub-circuit comprises a sixth MOS transistor, a first end of the sixth MOS transistor is connected to the second end of the control sub-circuit, a second end of the sixth MOS transistor is connected to the second output sub-circuit, and a gate of the sixth MOS transistor is connected to a GCK line.
3. The circuit of claim 2, wherein the control sub-circuit comprises a first MOS transistor, a second MOS transistor, and a third MOS transistor;
the first output sub-circuit comprises a fourth MOS tube and a first capacitor;
the second output sub-circuit comprises a fifth MOS tube and a second capacitor;
the first end of the first MOS tube is connected with a GSTV circuit, the second end of the first MOS tube is connected with the grid electrode of the second MOS tube, the second end of the first MOS tube is also connected with the first end of the sixth MOS tube, and the grid electrode of the first MOS tube is connected with a GCK circuit;
the first end of the second MOS tube is connected with the GCK circuit, and the second end of the second MOS tube is respectively connected with the second end of the third MOS tube, the first end of the first capacitor and the grid electrode of the fourth MOS tube;
the first end of the third MOS tube is connected with a VGL circuit, and the grid electrode of the third MOS tube is connected with the GCK circuit;
a second end of the fourth MOS tube is respectively connected with a VGH circuit and a second end of the first capacitor, and a first end of the fourth MOS tube is respectively connected with an output circuit, a second end of the second capacitor and a second end of the fifth MOS tube;
the first end of the fifth MOS tube is connected with a GCB circuit, and the grid electrode of the fifth MOS tube is respectively connected with the first end of the second capacitor and the second end of the sixth MOS tube;
and the grid electrode of the sixth MOS tube is connected with the GCK circuit.
4. The circuit of claim 3, wherein the first MOS transistor is a thin film transistor with a dual-gate structure, and the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor are thin film transistors with a single-gate structure.
5. The circuit of claim 3 or 4, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor are all P-type MOS transistors.
6. A GATE GOA circuit driving method applied to the GATE GOA circuit of any one of claims 1-5, the method comprising:
a GSTV line inputs a low level signal in a T1 period, a GCK line inputs a low level signal, and a GCB line inputs a high level signal;
a GSTV circuit inputs a high level signal in a T2 period, a GCK circuit inputs a high level signal, and a GCB circuit inputs a low level signal;
a GSTV line inputs a high level signal in a T3 period, a GCK line inputs a low level signal, and a GCB line inputs a high level signal;
the GSTV line receives a high-level signal, the GCK line receives a high-level signal, and the GCB line receives a low-level signal in a period of T4.
7. An EM GOA circuit, comprising:
the circuit comprises a first control sub-circuit, a second control sub-circuit, a first output sub-circuit, a second output sub-circuit and a capacitor bootstrap voltage blocking sub-circuit;
the first end of the first control sub-circuit is connected with the first output sub-circuit, and the second end of the first control sub-circuit is connected with the first end of the capacitor bootstrap voltage blocking sub-circuit;
the second end of the capacitor bootstrap voltage blocking sub-circuit is connected with the first end of the second control sub-circuit;
the first end of the second control sub-circuit is connected with the second output sub-circuit;
the first control sub-circuit is configured to control an output of the first output sub-circuit, the first control sub-circuit and the second control sub-circuit are configured to control an output of the second output sub-circuit, the second control sub-circuit is a sub-circuit having a capacitor bootstrap function, and the capacitor bootstrap voltage blocking sub-circuit is configured to block a bootstrap voltage flowing to the second control sub-circuit of the first control sub-circuit.
8. The circuit of claim 7, wherein the capacitor bootstrap voltage blocking sub-circuit comprises a seventh MOS transistor, a first end of the seventh MOS transistor is connected to the second end of the first control sub-circuit, a second end of the seventh MOS transistor is connected to the first end of the second control sub-circuit, and a gate of the seventh MOS transistor is connected to the ECK line.
9. The circuit of claim 8, wherein the first control sub-circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a third capacitor;
the second control sub-circuit comprises an eighth MOS tube and a second capacitor;
the first output sub-circuit comprises a ninth MOS tube and a first capacitor;
the second output sub-circuit comprises a tenth MOS tube;
the first end of the first MOS tube is connected with an ESTV circuit, the second end of the first MOS tube is respectively connected with the grid electrode of the second MOS tube, the grid electrode of the sixth MOS tube and the first end of the seventh MOS tube, and the grid electrode of the first MOS tube is connected with an ECK circuit;
the first end of the second MOS tube is connected with the ECK circuit, and the second end of the second MOS tube is respectively connected with the second end of the third MOS tube, the first end of the third capacitor and the grid electrode of the fourth MOS tube;
the first end of the third MOS tube is connected with a VGL line, and the grid electrode of the third MOS tube is connected with the ECK line;
the second end ECB line of the fourth MOS tube is connected, and the first end of the fourth MOS tube is respectively connected with the second end of the third capacitor and the first end of the fifth MOS tube;
the second end of the fifth MOS tube is connected with the second end of the sixth MOS tube, the first end of the first capacitor and the grid electrode of the ninth MOS tube respectively, and the grid electrode of the fifth MOS tube is connected with the ECB circuit;
the first end of the sixth MOS tube is connected with a VGH circuit;
a second end of the seventh MOS transistor is connected to a gate of the eighth MOS transistor, a second end of the second capacitor, and a gate of the tenth MOS transistor, respectively, and the gate of the seventh MOS transistor is connected to the ECK line;
the first end of the eighth MOS tube is connected with the ECB line, and the second end of the eighth MOS tube is connected with the first end of the second capacitor;
a first end of the ninth MOS tube is respectively connected with an input circuit and a second end of the tenth MOS tube, and a second end of the ninth MOS tube is respectively connected with a second end of the first capacitor and the VGH circuit;
and the first end of the tenth MOS tube is connected with a VGL circuit.
10. An EM GOA circuit driving method applied to the EM GOA circuit of any one of claims 7 to 9, the method comprising:
t1 period ESTV line inputs high level signal, ECK line inputs low level signal, ECB line inputs high level signal;
t2 period ESTV line inputs high level signal, ECK line inputs high level signal, ECB line inputs low level signal;
t3 period ESTV line inputs high level signal, ECK line inputs low level signal, ECB line inputs high level signal;
t4 period ESTV line input low level signal, ECK line input high level signal, ECB line input low level signal;
t5 period ESTV line input low level signal, ECK line input low level signal, ECB line input high level signal;
t6 cycle ESTV line inputs low level signal, ECK line inputs high level signal, ECB line inputs low level signal.
11. A display panel comprising the GATE GOA circuit of any one of claims 1 to 5 and/or the EM GOA circuit of any one of claims 7 to 9.
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| CN202110559906.7A CN113299241A (en) | 2021-05-21 | 2021-05-21 | GOA circuit, GOA circuit driving method and display panel |
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