CN113296735A - Floating point number processing method, equipment and storage medium - Google Patents

Abstract

The embodiment of the application provides a floating point number processing method, floating point number processing equipment and a storage medium. In the embodiment of the application, at least two floating point numbers to be processed can be obtained in response to a floating point number processing instruction; the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component; processing the at least two floating point numbers by using the fixed point number processing assembly to obtain a first processing result; and outputting a second processing result as a response of the floating point number processing instruction according to the respective symbolic attribute of the at least two floating point numbers and the first processing result. Therefore, in the embodiment of the application, under the condition that the upper layer application has no perception, the processing task of the floating point number can be converted into the processing task of the fixed point number, namely the processing task of the floating point number can be executed by the fixed point number processing assembly, so that the processing performance of the processor on the floating point number can be effectively improved, and the overall performance of the processor is further improved.

Description

Floating point number processing method, equipment and storage medium

Technical Field

The present application relates to the field of data processing technologies, and in particular, to a floating-point number processing method, floating-point number processing equipment, and a storage medium.

Background

Compare instructions (compare operations), which are the fundamental functions of comparison in a processor, are used in essentially every application. Especially in applications involving a large number of sequencing and/or querying tasks, the performance of the compare instruction is a key indicator that affects the overall performance of the processor.

At present, in many processors, the function of the compare instruction for a fixed-point number is usually provided, and the performance of the compare instruction for a floating-point number is relatively weak or even none, which seriously affects the performance of the compare instruction of the processor.

Disclosure of Invention

Aspects of the present disclosure provide a floating-point number processing method, apparatus, and storage medium to optimize processing performance of floating-point numbers.

The embodiment of the application provides a floating point number processing method, which comprises the following steps:

responding to a floating point number processing instruction, and acquiring at least two floating point numbers to be processed;

the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component;

processing the at least two floating point numbers by using the fixed point number processing assembly to obtain a first processing result;

and outputting a second processing result as a response of the floating point number processing instruction according to the respective symbolic attribute of the at least two floating point numbers and the first processing result.

The embodiment of the application also provides a processor, which comprises a compiling component and a fixed point processing component, wherein the compiling component is in communication connection with the fixed point processing component;

the compiling component is used for responding to a floating point number processing instruction and acquiring at least two floating point numbers to be processed; the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component; acquiring a first processing result returned by the fixed point number processing component; outputting a second processing result as a response of the floating-point number processing instruction according to the respective symbolic attributes of the at least two floating-point numbers and the first processing result;

the fixed point number processing component is configured to process the at least two floating point numbers to obtain the first processing result, and return the first processing result to the compiling component.

The embodiment of the application also provides a processor, which comprises a compiling component, a floating point number processing component and a fixed point number processing component, wherein the compiling component is in communication connection with the floating point number processing component and the fixed point number processing component;

the compiling component is used for responding to a floating point number processing instruction and acquiring at least two floating point numbers to be processed if the performance of the floating point number processing component is lower than a preset standard; the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component; acquiring a first processing result returned by the fixed point number processing component; outputting a second processing result as a response of the floating-point number processing instruction according to the respective symbolic attributes of the at least two floating-point numbers and the first processing result;

the fixed point number processing component is configured to process the at least two floating point numbers to obtain the first processing result, and return the first processing result to the compiling component.

Embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when executed by one or more processors, cause the one or more processors to perform the aforementioned floating point number processing method.

In the embodiment of the application, at least two floating point numbers to be processed can be obtained in response to a floating point number processing instruction; the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component; processing the at least two floating point numbers by using the fixed point number processing assembly to obtain a first processing result; and outputting a second processing result as a response of the floating point number processing instruction according to the respective symbolic attribute of the at least two floating point numbers and the first processing result. Therefore, in the embodiment of the application, under the condition that the upper layer application has no perception, the processing task of the floating point number can be converted into the processing task of the fixed point number, namely the processing task of the floating point number can be executed by the fixed point number processing assembly, so that the processing performance of the processor on the floating point number can be effectively improved, and the overall performance of the processor is further improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1a is a block diagram of a processor according to an exemplary embodiment of the present disclosure;

FIG. 1b is a block diagram of another processor provided in an exemplary embodiment of the present application;

FIG. 2 is a logic diagram of a floating point number processing scheme provided by an exemplary embodiment of the present application;

FIG. 3 illustrates a floating point data format according to an exemplary embodiment of the present application;

FIG. 4 is a diagram illustrating a storage format of a floating-point number with a non-negative attribute as a signed fixed-point number according to an exemplary embodiment of the present application;

FIG. 5 is a diagram illustrating a storage format of a floating-point number with a negative attribute as a signed fixed-point number according to an exemplary embodiment of the present application;

fig. 6 is a flowchart illustrating a floating-point number processing method according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Aiming at the technical problems that the existing processor can not support the floating point processing function or the floating point processing performance is insufficient, and the like, in some embodiments of the application: the method comprises the steps of responding to a floating point number processing instruction, and obtaining at least two floating point numbers to be processed; the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component; processing the at least two floating point numbers by using the fixed point number processing assembly to obtain a first processing result; and outputting a second processing result as a response of the floating point number processing instruction according to the respective symbolic attribute of the at least two floating point numbers and the first processing result. Therefore, in the embodiment of the application, under the condition that the upper layer application has no perception, the processing task of the floating point number can be converted into the processing task of the fixed point number, namely the processing task of the floating point number can be executed by the fixed point number processing assembly, so that the processing performance of the processor on the floating point number can be effectively improved, and the overall performance of the processor is further improved.

The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Fig. 1a is a schematic structural diagram of a processor according to an exemplary embodiment of the present application. As shown in fig. 1a, the processor may include: the compiling component 10 and the fixed point processing component 20, and the compiling component 10 and the fixed point processing component 20 are connected in communication.

The processor may be an embedded low-power low-cost CPU, such as an Arm core M core. Of course, a single instruction multiple data stream SIMD processor, such as an embedded GPU, etc., is also possible. These are merely exemplary, and the type of processor is not limited in this embodiment.

During the research process, the applicant finds that most processors generally mainly provide fixed-point processing functions, while floating-point processing functions are generally relatively weak or even absent, so that the floating-point processing performance is insufficient, and the overall performance of the processor is affected.

In this regard, applicants propose that the compilation component 10 in a processor may be improved: and at the stage of compiling the upper application program, converting the processing task of the floating point number into the processing task of the fixed point number. In this embodiment, the compiling component 10 may refer to a component in a processor for running a compiler. A compiler is a program that converts a programming language program with a high degree of abstraction (also called a source program) into a programming language program with a low degree of abstraction (also called a target program). In practical applications, the upper layer application program is compiled by the compiling component 10 and then runs under the processor.

For the compiling component 10, during the compiling process, the floating point number processing instruction may be monitored, and at least two floating point numbers to be processed under the floating point number processing instruction may be obtained. The floating-point number processing instruction may be a floating-point number comparison instruction or the like. Of course, other processing instructions derived based on the comparison instruction may also be used, and the floating-point processing instruction is not limited in this embodiment. The number of floating point numbers involved to be processed may not be exactly the same for different floating point number processing instructions. In most cases, a single floating point processing instruction is processed for two floating point numbers, for example, comparing sizes of the two floating point numbers, sorting the two floating point numbers, and the like, so that hereinafter, the technical solution will be described by taking an example of a processing procedure for the two floating point numbers.

FIG. 3 is a diagram illustrating a floating point number format according to an exemplary embodiment of the present application. Referring to FIG. 3, a floating-point number may include a sign bit, an exponent field, and a mantissa field. Wherein the sign bit is used to characterize the sign attribute of the floating point number. The floating point number with non-negative attribute has a value of 1 on the sign bit, the floating point number with negative attribute has a value of 0 on the sign bit. Also shown in FIG. 3 is a single precision floating point float32, float32 may be described as a 32-bit binary number, with the first 23 bits used as the mantissa field, the middle 8 bits used as the exponent field, and the most significant bit used as the sign bit. Of course, in this embodiment, the type of floating point number is not limited, and the floating point number in this embodiment may be a half-precision floating point number float16, a double-precision floating point number double, or the like, in addition to the float32 shown in fig. 3. The number of bits used to describe the binary number of a floating point number may not be exactly the same for different types of floating point numbers.

Based on this, the compiling component 10 may treat at least two floating-point numbers under the floating-point number processing instruction as signed fixed-point numbers and provide the fixed-point number processing component 20 with the signed fixed-point numbers.

The floating-point number is taken as a signed fixed-point number, which may mean that a binary number used for describing the floating-point number is taken as the fixed-point number. It should be noted that there is no need to perform any data conversion, since both fixed point numbers and floating point numbers can be represented by binary numbers in a processor, and therefore, the binary numbers used to describe floating point numbers can be directly regarded as fixed point numbers. For example, for float32 described previously, the 32-bit binary number used to describe float32 can be used as the signed fixed point number.

For the fixed-point number processing component 20, at least two floating-point numbers under a floating-point number processing instruction may be processed. It should be understood that the fixed-point number processing component 20 processes the floating-point number provided by the compiling component 10 as a signed fixed-point number, and it is not perceived by the fixed-point number processing component 20 that the floating-point number is processed. The fixed-point processing component 20 may output the first processing result to the compiling component 10 after processing at least two floating-point numbers under the floating-point number processing instruction.

After receiving the first processing result returned by the fixed-point number processing component 20, the compiling component 10 may output a second processing result as a response of the floating-point number processing instruction according to the respective symbolic attribute of at least two floating-point numbers and the first processing result.

In this embodiment, in some scenarios, the symbolic attributes of at least two floating point numbers under the fixed-point number processing instruction are known, for example, the symbolic attribute identifier of each floating point number is carried in the fixed-point number processing instruction. In this scenario, the second processing result may be output directly according to the respective sign attributes of the at least two floating point numbers and the first processing result. Wherein the sign attribute is used to describe the sign and sign of the floating point number.

In this scenario, if at least one floating point number in the at least two floating point numbers has a non-negative attribute, outputting the first processing result as a second processing result; and if the at least two floating point numbers have negative attributes, outputting a result opposite to the first processing result as a second processing result. Wherein, under the condition of comparing the floating point number, the opposite result of the first processing result is specifically: GT (greater than) LT (less), GE (greater than or equal to) LE (less than or equal to), LT (less than) GT (greater), LE (less than or equal to) GE (greater than or equal to), EQ (equal).

In the following, two floating point numbers are taken as an example, and the verification that the second processing result can be output according to the sign attribute of each of the at least two floating point numbers and the first processing result is performed in three cases.

In the first case: both floating-point numbers have a non-negative attribute at the same time.

Floating point numbers with non-negative attributes may include zero, a reduced number, an un-reduced number, positive infinity + INF, and a non-numeric index NAN, among others. Fig. 4 is a schematic diagram of a storage form of a floating-point number with a non-negative attribute as a signed fixed-point number according to an exemplary embodiment of the present application, and fig. 4 shows 32-bit binary numbers for describing zero, a reduced number, a non-reduced number, positive infinity + INF, and a non-numeric value NAN, respectively.

During research, the applicant finds that floating point numbers with non-negative attributes (positive attributes or 0) are generally processed according to the sequence of sign bits, exponent fields and mantissa fields, which is consistent with the sequence of fields in binary numbers of floating point numbers for describing non-negative attributes, for example, when two floating point numbers need to be compared, the floating point numbers can be compared according to the sequence of sign bits, exponent fields and mantissa fields. For a special floating-point number NaN, in general, when NaN participates in processing together with other floating-point numbers, any result output is correct. Accordingly, the present embodiment proposes that binary numbers corresponding to floating-point numbers having non-negative attributes can be directly treated as fixed-point numbers.

It is noted that when processing floating point numbers as signed fixed point numbers, the compiling component 10 may store the floating point numbers as complements and provide the complements of the floating point numbers to the fixed point number processing component 20. And the highest bit of the binary number of the floating-point number describing the non-negative attribute is not 1, so the binary number will be treated as a non-negative fixed-point number. The complement of the non-negative fixed-point number is the same as the original, and therefore, for the fixed-point number processing component 20, the floating-point number having the non-negative attribute is processed according to the complement of the binary number describing the floating-point number having the non-negative attribute.

Thus, for floating point numbers that are not a negative attribute, the first processing result output by the fixed point number processing component 20 will be identical to the result derived by conventional processing logic for floating point numbers. For example, referring to fig. 4, after comparing each floating point number (32-bit binary number) in fig. 4 as a signed fixed point number, the first processing result will be zero < maximum non-reduced number < minimum reduced number < maximum reduced number < positive infinity, which complies with the conventional floating point number comparison rule zero < positive non-reduced floating point number < positive reduced floating point number < + INF. That is, the correctness of the aforementioned "if at least one of the at least two floating point numbers has a non-negative attribute, the first processing result can be output as the second processing result" is verified.

In this case, there is also a special distribution feature, i.e. two floating-point numbers are zero at the same time. Under the conventional processing rule of floating point numbers, the floating point number 0 with a negative attribute and the floating point number 0 with a positive attribute are equal, but under the processing rule of fixed point numbers, the condition of +0> -0 can occur, and the result is not consistent with the result obtained by the conventional processing logic of floating point numbers simply from the view of comparison results, but the final result is not influenced in the processing scenes of comparison, sorting, addition and subtraction and the like. Therefore, in this embodiment, the floating point number is not considered to be zero at the same time, and if special processing is required for this case, this special case can be found in time by adding the screening condition, and the required processing rule is configured, which does not affect the implementation of the overall scheme of this embodiment.

In the second case: one floating point number has a negative attribute and the other floating point number has a non-negative attribute.

In this case, floating point number processing can typically be done directly based on symbolic attributes. For example, when two floating point numbers need to be compared, a floating point number with a non-negative attribute is typically larger than a floating point number with a negative attribute.

As mentioned earlier, where a floating point number is considered to be a signed fixed point number, the binary number used to describe the floating point number will be stored in complement. Unlike floating point numbers with non-negative attributes, in the process of storing the floating point number with the negative attribute as a complement, bits other than the most significant bit (i.e., the sign bit) need to be inverted (0 to 1,1 to 0) and then added with 1 to obtain the complement corresponding to the floating point number with the negative attribute. FIG. 5 is a diagram illustrating a storage form of a floating-point number with a negative attribute as a signed fixed-point number according to an exemplary embodiment of the present application. The other 31 bits in fig. 5 except the sign bit are the result of negation on the basis of the original code.

On this basis, the fixed-point-number processing component 20 may process a binary number that will be used to describe a floating-point number as a signed fixed-point number. For example, when two floating point numbers need to be compared, the first processing result output by the fixed point processing component 20 is inevitably that the floating point number with non-negative attribute is larger than the floating point number with negative attribute (according to the fixed point processing rule, the fixed point processing component 20 compares the sign based on the fixed point number, that is, the negative fixed point number is usually smaller than the non-negative fixed point number), which is consistent with the result obtained according to the conventional processing logic of the floating point number. That is, the correctness of the aforementioned "if at least one of the at least two floating point numbers has a non-negative attribute, the first processing result can be output as the second processing result" is verified.

In the third case: both floating-point numbers have a negative attribute at the same time.

Referring to FIG. 5, several exemplary storage forms for floating point numbers with negative attributes as signed fixed point numbers are shown in FIG. 5. In the research process, the applicant finds that after the floating point number with the negative attribute is stored in the complement form, the larger the last 31 bits in the complement, the smaller the floating point number represented by the complement. Thus, the first processing result output by fixed-point processing component 20 will be the inverse of the result obtained by conventional processing logic in terms of floating-point numbers. That is, the correctness of the aforementioned "if at least two floating point numbers have a negative attribute, the result opposite to the first processing result is output as the second processing result" is verified.

In summary, in this embodiment, the compiling component 10 may store the at least two floating-point numbers under the floating-point number processing instruction as complements respectively, and provide the complements corresponding to the at least two floating-point numbers to the fixed-point number processing component 20. The fixed-point number processing component 20 may process the complements corresponding to the at least two floating-point numbers to obtain a first processing result. And, according to the distribution of the sign attributes of at least two floating point numbers, determining whether to deform the first processing result to obtain the second processing result.

In other scenarios, the symbolic attributes of at least two floating-point numbers under the fixed-point number processing instruction are unknown. In such a scenario, the second processing result cannot be directly output according to the respective sign attributes of the at least two floating point numbers and the first processing result.

In this scenario, an attribute description parameter may be determined based on sign bits of at least two floating point numbers, where the attribute description parameter is used to describe distribution characteristics of positive and negative attributes of the at least two floating point numbers; and outputting a second processing result according to the attribute description parameter and the first processing result.

The distribution characteristics of the positive and negative attributes of at least two floating point numbers can include simultaneously having a negative attribute, simultaneously having a non-negative attribute, and mixing the negative attribute and the non-negative attribute. The attribute description parameters corresponding to different distribution characteristics may not be identical.

Optionally, compiling component 10 and-es the sign bits of at least two floating point numbers to obtain the attribute description parameter. The compiling component 10 may shift a binary number describing a floating point number to obtain the highest bit of the binary number, i.e. the sign bit of the floating point number. The attribute description parameter may be obtained by performing an and operation on the sign bits of at least two floating point numbers. In practical applications, if the signs of at least two floating point numbers are both 1, that is, under the condition that at least two floating point numbers have negative attributes, the attribute description parameter will be 1, and under other conditions, the attribute description parameter will be 0. Therefore, the attribute description parameter may correspond to the concept of classifying the distribution of the symbolic attribute in the scenario where the symbolic attributes of the at least two floating point numbers are known.

On this basis, the compiling component 10 may perform an exclusive or operation on the attribute description parameter and the first processing result to obtain an evaluation index of the first processing result; if the evaluation index is true, taking the first processing result as a second processing result and outputting; if the evaluation index is false, a result opposite to the first processing result is output as a second processing result.

It should be noted that although the concept of the attribute description parameter is proposed in the present embodiment, in practical applications, it may be determined whether to directly adopt the first processing result output by the fixed-point processing component 20 as the second processing result by means of a logical expression, and for the compiling component 10, the attribute description parameter does not need to be separately provided, but is hidden in the logical expression.

For example, in the event that symbolic attributes of at least two floating point numbers under a floating point number processing instruction are not known, the compilation component 10 may determine the second processing result according to the following exemplary logic:

int a (int) & a; - - - -taking the floating-point number a as the signed fixed-point number

int B ═ int ═ B; taking the floating-point number b as the signed fixed-point number

bool f＝(A>B)^((A&B&0x80000000)>>31

Wherein, the boolean variable is represented by the boolean variable, the boolean variable can be used for a logic expression, and the operation result of the logic expression is true or false. In the above example, the logical expression is (a > B) ^ ((a & B &0x80000000) > >31, where ((a & B &0x80000000) > >31 corresponds to the attribute description parameter in the present embodiment, and (a > B) corresponds to the first processing result in the present embodiment, it should be understood that the first processing result is the actual output of the fixed-point-number processing component 20 to, and is not limited to (a > B) in the above example.

Accordingly, in the present embodiment, even when the sign attribute of the floating point number is unknown, the second processing result can be accurately determined.

In this embodiment, at least two floating point numbers to be processed may be obtained in response to the floating point number processing instruction; providing the at least two floating point numbers as signed fixed point numbers to the fixed point number processing component 20; processing the at least two floating point numbers with the fixed point number processing component 20 to obtain a first processing result; and outputting a second processing result as a response of the floating point number processing instruction according to the respective symbolic attribute of the at least two floating point numbers and the first processing result. Accordingly, in the embodiment of the present application, under the condition that the upper layer application does not sense, the processing task of the floating point number can be converted into the processing task of the fixed point number, that is, the processing task of the floating point number can be executed by using the fixed point number processing component 20, which can effectively improve the processing performance of the processor on the floating point number, and further improve the overall performance of the processor.

Fig. 1b is a schematic structural diagram of another processor according to an exemplary embodiment of the present application. Referring to FIG. 1b, the processor differs from the processor shown in FIG. 1a in that floating point processing component 30 is also included in the processor of FIG. 1 b. FIG. 2 is a logic diagram of a floating point number processing scheme according to an exemplary embodiment of the present application. Referring to FIG. 2, in the above or below embodiments, compilation component 10 may perform hardware detection on a processor.

For compilation component 10, if it is determined that no floating-point processing components are present in the processor as shown in FIG. 1a, compilation component 10 may execute the processing logic of the previous embodiments.

If it is determined that a floating-point processing component 30 is present in the processor as shown in FIG. 1b, the performance of the floating-point processing component 30 may be further examined:

in one case, if it is determined that the performance of floating-point processing component 30 in the processor is lower than the predetermined standard, compiling component 10 may execute the processing logic of the foregoing embodiment.

In another case, if it is determined that the performance of the floating-point number processing component 30 existing in the processor is higher than or equal to the aforementioned preset standard, the compiling component 10 may process the floating-point number that is not processed by using the fixed-point number processing component 20 when the load ratio between the floating-point number processing component 30 and the fixed-point number processing component 20 is higher than the preset load balance exponent until the load ratio satisfies the load balance exponent or all the floating-point numbers that are not processed are processed.

In the case that the performance of the floating-point processing component 30 existing in the processor is higher than or equal to the aforementioned preset standard, the compiling component 10 may count the number of floating-point processing instructions and fixed-point processing instructions initiated by the upper application program in a unit time, and use the ratio of the number of the two processing instructions as the load ratio between the floating-point processing component 30 and the fixed-point processing component 20. Obviously, the load ratio will be higher in the case where the number of floating-point number processing instructions is larger and the number of fixed-point number processing instructions is smaller.

In this embodiment, the preset load balancing index may be 1:1, although this embodiment is not limited thereto, and the load balancing index may also be other proportions, such as a: 1, etc.

In this embodiment, the compiling component 10 may pre-construct a task set, where the task set may be used to accommodate at least one floating-point processing task, and a single floating-point processing task may include at least two floating-point numbers that have not yet been processed. In practical applications, the floating-point processing instruction in the foregoing embodiment will correspondingly generate a floating-point processing task. And floating point number processing tasks may be concurrent or highly concurrent.

Based on this, in this embodiment, the compilation component 10 may configure floating point numbers that have not yet been processed into task sets; selecting a floating point number processing task from the task set as a task to be processed; processing the task to be processed by using the fixed point number processing component 20; processing the tasks based on the residual floating point numbers in the task set, and updating the load ratio; if the updated load ratio does not satisfy the load balancing exponent, the fixed point processing component 20 continues to process the next floating point processing task in the task set, and updates the load ratio again.

Referring to fig. 2, the compiling component 10 may find a floating point number processing task whose symbolic attribute of a floating point number included in the floating point number processing task is known from floating point number processing tasks initiated by an upper layer application, and add the floating point number processing task to the task set. Then, a floating-point processing task (in practical applications, it may be randomly taken out) may be taken out from the task set, and the floating-point number under the floating-point processing task is provided to the fixed-point processing component 20 as a signed fixed-point number for processing. The fixed-point processing component 20 may output the first processing result to the compiling component 10 according to the fixed-point processing rule. The compiling component 10 may output the second processing result according to the sign attribute of the floating point number under the floating point number processing task and the first processing result, and the specific process may refer to the foregoing embodiments and will not be described herein again. Therefore, a floating-point number processing task is reduced from the task set, and the compiling component 10 may update the load ratio according to the reduction, for example, the load ratio may be recalculated after the floating-point number processing task is reduced by 1, of course, the number of the fixed-point number processing tasks may change synchronously, and the compiling component 10 needs to consider the change condition of the fixed-point number processing task when updating the load ratio.

Then, the compiling component 10 may determine again whether the load ratio is higher than the load balancing exponent, and if so, continue to fetch a floating point processing task from the task set, and process the floating point processing task again by using the fixed point processing component 20, and update the load ratio.

And circulating in this way, until the load ratio reaches the load balance index or the task set is empty, stopping circulating, namely stopping processing the floating point number processing task by the borrowing fixed point number processing component 20.

In practical applications, floating-point processing tasks including floating-point numbers with unknown symbolic attributes may be processed by the floating-point processing component 30, and generally, the number of such floating-point processing tasks is small, so that excessive impact on the load of the floating-point processing component 30 is avoided.

It should be noted that, in the present embodiment, the compiling component 10 may also use the load ratio and the load balancing exponent between the fixed-point processing component 20 and the floating-point processing component 30. In this case, the load ratio will be lower when the number of floating-point number processing instructions is larger and the number of fixed-point number processing instructions is smaller, and accordingly, the determination condition for determining whether to borrow the fixed-point number processing component 20 to process the floating-point number will also become a load ratio lower than the load balance exponent. Further details will not be described here.

In summary, in the embodiment, different processing schemes may be adopted for different sensing results based on hardware sensing of the processor, and for a case that floating point processing performance in the processor is relatively weak or does not exist, the fixed point processing component 20 may be directly borrowed to process the floating point, and with the help of the high performance of the fixed point processing component 20, the processing performance of the processor on the floating point may be effectively improved; for the condition that load balancing needs to be performed on the floating-point number processing assembly 30 and the fixed-point number processing assembly 20, the load of the floating-point number processing assembly 30 can be relieved by borrowing the fixed-point number processing assembly 20 to process part of floating-point numbers, so that the load balancing effect between the floating-point number processing assembly 30 and the fixed-point number processing assembly 20 is optimized, and the overall performance of the processor is improved.

Of course, in some possible designs, if it is known whether a floating-point processing element is included in the processor, only adaptive processing logic may be configured for compiling component 10, and hardware detection logic does not need to be configured for compiling component 10.

Fig. 6 is a flowchart illustrating a floating-point number processing method according to an embodiment of the present disclosure. The floating-point number processing method provided by this embodiment may be executed by a floating-point number processing apparatus, which may be implemented as software or as a combination of software and hardware, and may be integrated in a compiling component of a processor. As shown in fig. 6, the method includes:

step 600, responding to a floating point number processing instruction, and acquiring at least two floating point numbers to be processed;

601, taking at least two floating point numbers as fixed point numbers with symbols and providing the fixed point numbers to a fixed point number processing component;

step 602, processing at least two floating point numbers by using a fixed point number processing assembly to obtain a first processing result;

and 603, outputting a second processing result as a response of the floating point number processing instruction according to the respective symbol attributes of the at least two floating point numbers and the first processing result.

In an alternative embodiment, the step of outputting the second processing result based on the sign attribute of each of the at least two floating point numbers and the first processing result includes:

if at least one floating point number in the at least two floating point numbers has a non-negative attribute, outputting the first processing result as a second processing result;

and if the at least two floating point numbers have negative attributes, outputting a result opposite to the first processing result as a second processing result.

In an optional embodiment, the method further comprises:

if the sign attributes of the at least two floating point numbers are unknown, determining an attribute description parameter based on the sign bits of the at least two floating point numbers, wherein the attribute description parameter is used for describing the distribution characteristics of the sign attributes of the at least two floating point numbers;

and outputting a second processing result according to the attribute description parameter and the first processing result.

In an alternative embodiment, the step of determining an attribute description parameter based on the sign bits of at least two floating point numbers includes:

and the sign bits of at least two floating point numbers to obtain the attribute description parameters.

In an optional embodiment, the step of outputting the second processing result according to the attribute description parameter and the first processing result includes:

performing exclusive-or operation processing on the attribute description parameters and the first processing result to obtain an evaluation index of the first processing result;

if the evaluation index is true, taking the first processing result as a second processing result and outputting;

if the evaluation index is false, a result opposite to the first processing result is output as a second processing result.

In an alternative embodiment, the step of providing the fixed-point number processing component with at least two floating-point numbers as signed fixed-point numbers includes:

and storing the at least two floating point numbers as complement codes respectively, and providing the complement codes corresponding to the at least two floating point numbers to the fixed point number processing component.

In an alternative embodiment, the step of processing the at least two floating point numbers with the fixed point number processing component to obtain the first processing result comprises:

and processing the complement codes corresponding to the at least two floating point numbers by using the fixed point number processing assembly to obtain a first processing result.

In an alternative embodiment, prior to processing instructions in response to floating point numbers, the method further comprises:

performing a hardware check on the processor;

and if the floating-point number processing component does not exist in the processor or the performance of the floating-point number processing component is lower than the preset standard, executing the operation responding to the floating-point number processing instruction.

In an optional embodiment, the method further comprises:

if the performance of the floating point number processing assembly in the processor is higher than or equal to the preset standard, under the condition that the load ratio between the floating point number processing assembly and the fixed point number processing assembly is higher than the load balance index, the fixed point number processing assembly is used for processing the floating point number which is not processed until the load ratio meets the load balance index or the floating point number which is not processed is completely processed.

In an alternative embodiment, the step of processing the floating point number not processed by the fixed point number processing component comprises:

the floating point number which is not processed is configured into a task set, the task set comprises at least one floating point number processing task, and a single floating point number processing task comprises at least two floating point numbers which are not processed;

selecting a floating point number processing task from the task set as a task to be processed;

processing the task to be processed by utilizing the fixed point number processing component;

processing the tasks based on the residual floating point numbers in the task set, and updating the load ratio;

and if the updated load ratio does not meet the load balance index, continuing to process the next floating point number processing task in the task set by using the fixed point number processing assembly, and updating the load ratio again.

In an optional embodiment, the method further comprises:

the floating point number which is known in symbolic attribute and is unprocessed is determined as the floating point number which is not processed yet.

In an alternative embodiment, the step of processing the at least two floating point numbers with the fixed point number processing component comprises:

and comparing at least two floating point numbers by using the fixed point number processing component.

The execution subjects of the steps of the method provided by the above embodiments may be the same device, or different devices may also be used as the execution subjects of the method. For example, the execution subjects of steps 601 to 603 may be device a; for another example, the execution subject of steps 601 and 602 may be device a, and the execution subject of step 603 may be device B; and so on.

In addition, in some of the flows described in the above embodiments and the drawings, a plurality of operations are included in a specific order, but it should be clearly understood that the operations may be executed out of the order presented herein or in parallel, and the sequence numbers of the operations, such as 601, 602, etc., are merely used for distinguishing different operations, and the sequence numbers themselves do not represent any execution order. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.

It should be noted that, for the sake of brevity, the technical details of the embodiments of the floating-point number processing method described above may be referred to the related descriptions in the foregoing processor embodiments, and are not described herein again, which should not cause a loss of the scope of the present application.

Accordingly, the present application further provides a computer readable storage medium storing a computer program, where the computer program is capable of implementing the steps that can be executed by a processor in the foregoing method embodiments when executed.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (16)

1. A floating point number processing method, comprising:

responding to a floating point number processing instruction, and acquiring at least two floating point numbers to be processed;

the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component;

processing the at least two floating point numbers by using the fixed point number processing assembly to obtain a first processing result;

and outputting a second processing result as a response of the floating point number processing instruction according to the respective symbolic attribute of the at least two floating point numbers and the first processing result.

2. The method of claim 1, wherein outputting a second processing result based on the symbolic attribute of each of the at least two floating point numbers and the first processing result comprises:

if at least one floating point number in the at least two floating point numbers has a non-negative attribute, outputting the first processing result as the second processing result;

and if the at least two floating point numbers have negative attributes, outputting a result opposite to the first processing result as the second processing result.

3. The method of claim 1, further comprising:

if the sign attributes of the at least two floating point numbers are unknown, determining an attribute description parameter based on the sign bits of the at least two floating point numbers, wherein the attribute description parameter is used for describing the distribution characteristics of the sign attributes of the at least two floating point numbers;

and outputting the second processing result according to the attribute description parameters and the first processing result.

4. The method of claim 3, wherein determining an attribute description parameter based on the sign bits of the at least two floating point numbers comprises:

and the sign bits of the at least two floating point numbers are subjected to AND operation processing to obtain the attribute description parameter.

5. The method of claim 3, wherein outputting the second processing result according to the attribute description parameter and the first processing result comprises:

performing exclusive-or operation processing on the attribute description parameters and the first processing result to obtain an evaluation index of the first processing result;

if the evaluation index is true, taking the first processing result as the second processing result and outputting;

and if the evaluation index is false, outputting a result opposite to the first processing result as the second processing result.

6. The method of claim 1, wherein providing the at least two floating point numbers as signed fixed point numbers to a fixed point number processing component comprises:

and respectively storing the at least two floating point numbers as complement codes, and providing the complement codes corresponding to the at least two floating point numbers to the fixed point number processing component.

7. The method of claim 6, wherein processing the at least two floating point numbers with the fixed point number processing component to obtain a first processing result comprises:

and processing the complement codes corresponding to the at least two floating point numbers by using the fixed point number processing assembly to obtain the first processing result.

8. The method of claim 1, further comprising, prior to responding to floating point number processing instructions:

performing a hardware check on the processor;

and if the floating-point number processing assembly does not exist in the processor or the performance of the floating-point number processing assembly is lower than a preset standard, executing the operation responding to the floating-point number processing instruction.

9. The method of claim 8, further comprising:

if the performance of the floating point number processing assembly in the processor is determined to be higher than or equal to the preset standard, under the condition that the load ratio between the floating point number processing assembly and the fixed point number processing assembly is higher than a preset load balance index, the fixed point number processing assembly is used for processing the floating point number which is not processed until the load ratio meets the load balance index or the floating point number which is not processed is completely processed.

10. The method of claim 9, wherein processing floating point numbers that have not been processed using the fixed point number processing component comprises:

configuring the floating point numbers which are not processed into a task set, wherein the task set comprises at least one floating point number processing task, and a single floating point number processing task comprises at least two floating point numbers which are not processed;

selecting a floating point number processing task from the task set as a task to be processed;

processing the task to be processed by utilizing the fixed point number processing component;

processing tasks based on the remaining floating point numbers in the task set, and updating the load ratio;

and if the updated load ratio does not meet the load balance index, continuing to process the next floating point number processing task in the task set by using the fixed point number processing assembly, and updating the load ratio again.

11. The method of claim 10, further comprising:

and determining the floating point number which has known symbolic attribute and is unprocessed as the unprocessed floating point number.

12. The method of claim 1, wherein the processing the at least two floating point numbers with the fixed point number processing component comprises:

and comparing the at least two floating point numbers by using the fixed point number processing component.

13. A processor comprising a compiling component and a fixed point processing component, wherein the compiling component is communicatively connected with the fixed point processing component;

the compiling component is used for responding to a floating point number processing instruction and acquiring at least two floating point numbers to be processed; the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component; acquiring a first processing result returned by the fixed point number processing component; outputting a second processing result as a response of the floating-point number processing instruction according to the respective symbolic attributes of the at least two floating-point numbers and the first processing result;

the fixed point number processing component is configured to process the at least two floating point numbers to obtain the first processing result, and return the first processing result to the compiling component.

14. A processor is characterized by comprising a compiling component, a floating point number processing component and a fixed point number processing component, wherein the compiling component is in communication connection with the floating point number processing component and the fixed point number processing component;

the compiling component is used for responding to a floating point number processing instruction and acquiring at least two floating point numbers to be processed if the performance of the floating point number processing component is lower than a preset standard; the at least two floating point numbers are used as signed fixed point numbers and are provided for a fixed point number processing component; acquiring a first processing result returned by the fixed point number processing component; outputting a second processing result as a response of the floating-point number processing instruction according to the respective symbolic attributes of the at least two floating-point numbers and the first processing result;

the fixed point number processing component is configured to process the at least two floating point numbers to obtain the first processing result, and return the first processing result to the compiling component.

15. The processor as recited in claim 14, wherein the compiling component is further configured to:

if the performance of the floating point number processing assembly in the processor is determined to be higher than or equal to the preset standard, under the condition that the load ratio between the floating point number processing assembly and the fixed point number processing assembly is higher than a preset load balance index, the fixed point number processing assembly is used for processing the floating point number which is not processed until the load ratio meets the load balance index or the floating point number which is not processed is completely processed.

16. A computer-readable storage medium storing computer instructions, which when executed by one or more processors, cause the one or more processors to perform the floating point number processing method of any one of claims 1-12.

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