CN113286151B - Hardware encoder pipeline circuit - Google Patents
Hardware encoder pipeline circuit Download PDFInfo
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- CN113286151B CN113286151B CN202110820468.5A CN202110820468A CN113286151B CN 113286151 B CN113286151 B CN 113286151B CN 202110820468 A CN202110820468 A CN 202110820468A CN 113286151 B CN113286151 B CN 113286151B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
- H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/96—Tree coding, e.g. quad-tree coding
Abstract
The present disclosure relates to a hardware encoder pipeline circuit, comprising: the sub-pixel estimation unit is used for carrying out sub-pixel search on the coding tree unit; the intra-frame mode pre-decision unit is used for quickly pre-selecting an intra-frame mode; a quadtree QT mode decision unit supporting a maximum coding tree unit; a binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit; the deblocking unit is used for outputting the result to the DDR memory after the coding tree unit processes the result; the sub-pixel estimation unit is sequentially connected with the quad-tree QT mode decision unit supporting the maximum coding tree unit, the binary tree BT and extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and the deblocking unit; the intra mode pre-decision unit is connected to the quad tree QT mode decision unit that supports the largest coding tree unit.
Description
Technical Field
The present disclosure relates to the field of hardware encoding technologies, and more particularly, to a pipeline circuit of a hardware encoder.
Background
The continuously optimized video coding standards help to further improve the compression efficiency of video images and reduce the cost of video image storage and network transmission, including the latest video coding standards such as AVS3, AV1, H.266 and the like. However, these new video coding standards employ larger processing units, more candidate modes, and higher data dependency. This means that the new standard also has higher processing complexity than the previous standard, i.e. longer processing time for video compression, more resources required and higher parallel design difficulties. Specifically, in the AVS3 video coding standard, the coding Tree unit ctu (coding Tree unit) supports a binary Tree BT partition and an extended quad Tree EQT partition in addition to the conventional quad Tree QT partition. Taking the CTU with the maximum size of 128x128 as an example, the partitioning combination of QT/BT/EQT is shown in FIG. 1. During the encoder process, it is necessary to select an optimal partitioning result among QT/BT/EQTs of various sizes (such as 128x128, 64x64, etc.) through mode decision. Clearly, the AVS3 standard presents higher challenges to high performance hardware video encoder design relative to previous generation encoders such as AVS2 (QT only partitioning).
The AVS3 standard is the latest generation of ultra-high definition-oriented video coding standard independently developed in China, and a related scheme in the design aspect of a hardware encoder is not disclosed at present. However, the former generation AVS2 or international standard h.265 hardware encoder typically employs CTU-level-based pipelining, where the CTU-level relationships associated with the module decision module md (mode decision) are shown in fig. 2. In the figure, the MD only supports the QT mode partitioning decision process.
As shown in fig. 2, the conventional CTU-level hardware MD module circuit only supports QT decision, i.e. on the one hand, does not support BT/EQT decision processing. On the other hand, if the BT/EQT processing process is directly merged into the MD process of QT, a one-level MD pipeline processing is adopted, which results in the overall MD processing process being too complex, which means that according to a design method similar to the conventional AVS3, it is difficult to not only process the QT/BT/EQT decision process within the same pipeline time, but also may cause performance loss due to more tool abandonments, and it is difficult to achieve balance between area, speed, and encoder mode decision performance.
In addition to the challenges that the MD module itself may face during QT/BT/EQT processing, in AVS2 hardware encoder design, the inter-frame SKIP mode is a single stage pipeline circuit process that requires all QT interpolated pixel results to be passed to the MD. Although the time for the MD internal interpolation processing can be saved, a large number of different types of SKIP interpolated pixels are required due to the QT/BT/EQT in AVS3 and more size combinations. This means that SKIP individual pipeline stages would result in excessive intermediate storage, which obviously requires more transmission overhead.
Disclosure of Invention
In view of the shortcomings in the prior art noted by the background of the technology, the present invention overcomes the above-listed shortcomings in the prior art and provides a two-stage CTU mode decision pipeline circuit structure.
The present disclosure provides a hardware encoder pipeline circuit, including:
the sub-pixel estimation unit is used for carrying out sub-pixel search on the coding tree unit;
the intra-frame mode pre-decision unit is used for quickly pre-selecting an intra-frame mode;
a quadtree QT mode decision unit supporting a maximum coding tree unit;
a binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit;
the deblocking unit is used for outputting the result to the DDR memory after the coding tree unit processes the result;
the sub-pixel estimation unit is sequentially connected with the quad-tree QT mode decision unit supporting the maximum coding tree unit, the binary tree BT and extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and the deblocking unit;
the intra mode pre-decision unit is connected to the quad tree QT mode decision unit that supports the largest coding tree unit.
Further, the quadtree QT mode decision unit supporting the maximum coding tree unit includes internally:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
Further, the decision unit of the mode of the binary tree BT and the extended quad-tree EQT supporting the maximum coding tree unit internally includes:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
Further, still include:
and the mode decision division unit is used for carrying out intra-frame coding on all the final division sizes according to real peripheral reference pixels for the optimal division mode which is decided by all the sizes of the current coding tree unit CTU.
In order to solve the above technical problem, the present disclosure further provides a hardware encoder pipeline circuit, including:
the sub-pixel estimation unit is used for carrying out sub-pixel search on the coding tree unit;
the intra-frame mode pre-decision unit is used for quickly pre-selecting an intra-frame mode;
a quadtree QT mode decision unit supporting a maximum coding tree unit;
a binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit;
the deblocking unit is used for outputting the result to the DDR memory after the coding tree unit processes the result;
the sub-pixel estimation unit is connected with the quad-tree QT mode decision unit supporting the maximum coding tree unit;
the intra-frame mode pre-decision unit is connected with a binary tree BT and an extended quad-tree EQT mode decision unit which support a maximum coding tree unit;
the quad-tree QT mode decision unit supporting the maximum coding tree unit is connected with the deblocking unit in parallel with the binary tree BT supporting the maximum coding tree unit and the extended quad-tree EQT mode decision unit.
Further, still include:
the comparison unit is used for comparing and analyzing the decision results of the quad-tree QT mode decision unit supporting the maximum coding tree unit and the decision results of the binary tree BT and the extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and preferentially outputting the decision results;
the comparing unit is positioned between the quad-tree QT mode decision unit supporting the maximum coding tree unit and the binary tree BT and extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and the deblocking unit.
Further, the quadtree QT mode decision unit supporting the maximum coding tree unit includes internally:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
Further, the decision unit of the mode of the binary tree BT and the extended quad-tree EQT supporting the maximum coding tree unit internally includes:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
The beneficial effect of this disclosure does:
first, unlike previous generation hardware encoder circuits such as AVS2, in order to save a large amount of storage cost in the middle of the SKIP circuit in the AVS3 hardware encoder, the present disclosure implements the SKIP circuit in mode internal decision.
Secondly, the disclosure provides that the CTU-level MD functional circuit in the AVS3 encoder is divided into QT and BTEQT processing circuits respectively, and two possible implementation schemes are provided, so that the design and implementation difficulty of the MD functional circuit in the AVS3 can be reduced, and the difficulty that the QT/BT/EQT is difficult to process in a centralized manner in one-level CTU MD running water is avoided.
Drawings
FIG. 1 shows a schematic diagram of QT/BT/EQT partitioning pattern of a CTU in AVS 3;
FIG. 2 is a schematic diagram showing the related pipeline relationship of MD modules in an AVS2 hardware encoder;
fig. 3 shows a schematic structural diagram of embodiment 1 of the present disclosure;
FIG. 4 shows a schematic structural diagram of a preferred embodiment of example 1 of the present disclosure;
fig. 5 shows a schematic structural diagram of embodiment 2 of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
TABLE 1 Key Module functional description
| Module | English full scale | Chinese character | Main function |
| SKIP | Skip | Inter prediction skip mode | Inter prediction skip mode |
| FME | Fractional pixel motion estimation | Sub-pixel motion estimation | Pixel-by-pixel search of CTU |
| PreIP | Pre-Intra Prediction | Intra-mode pre-decision unit | Rapid preselection of intra mode |
| MD | Mode Decision | Mode decision | Traditional mode decision circuit |
| MD_QT | Mode Decisionfor Quad Tree | Support forQuad-tree QT mode decision for maximum CTU | Mode decision circuit |
| MD_BTEQT | Mode Decision for Binary Tree and Extended QT | Bitbree BT and EQT mode decisions supporting maximum CTU | Mode decision circuit |
| DBK | De-blocking | Deblocking effect | Coding unit deblocking filter post-processing |
The first embodiment is as follows:
as shown in fig. 3:
the present disclosure provides a hardware encoder pipeline circuit, including:
the sub-pixel estimation unit is used for carrying out sub-pixel search on the coding tree unit;
the intra-frame mode pre-decision unit is used for quickly pre-selecting an intra-frame mode;
a quadtree QT mode decision unit supporting a maximum coding tree unit;
a binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit;
the deblocking unit is used for outputting the result to the DDR memory after the coding tree unit processes the result;
the sub-pixel estimation unit is sequentially connected with the quad-tree QT mode decision unit supporting the maximum coding tree unit, the binary tree BT and extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and the deblocking unit;
the intra mode pre-decision unit is connected to the quad tree QT mode decision unit that supports the largest coding tree unit.
Further, the quadtree QT mode decision unit supporting the maximum coding tree unit includes internally:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
Further, the decision unit of the mode of the binary tree BT and the extended quad-tree EQT supporting the maximum coding tree unit internally includes:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
As shown in fig. 4, the first embodiment of the present application may be further modified as follows:
further, still include:
and the mode decision division unit is used for carrying out intra-frame coding on all the final division sizes according to real peripheral reference pixels for the optimal division mode which is decided by all the sizes of the current coding tree unit CTU.
The beneficial effect of this disclosure does:
first, unlike previous generation hardware encoder circuits such as AVS2, in order to save a large amount of storage cost in the middle of the SKIP circuit in the AVS3 hardware encoder, the present disclosure implements the SKIP circuit in mode internal decision.
Secondly, the disclosure provides that the CTU-level MD functional circuit in the AVS3 encoder is divided into QT and BTEQT processing circuits respectively, and two possible implementation schemes are provided, so that the design and implementation difficulty of the MD functional circuit in the AVS3 can be reduced, and the difficulty that the QT/BT/EQT is difficult to process in a centralized manner in one-level CTU MD running water is avoided.
Example two:
as shown in fig. 5, the present disclosure also provides a hardware encoder pipeline circuit, including:
the sub-pixel estimation unit is used for carrying out sub-pixel search on the coding tree unit;
the intra-frame mode pre-decision unit is used for quickly pre-selecting an intra-frame mode;
a quadtree QT mode decision unit supporting a maximum coding tree unit;
a binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit;
the deblocking unit is used for outputting the result to the DDR memory after the coding tree unit processes the result;
the sub-pixel estimation unit is connected with the quad-tree QT mode decision unit supporting the maximum coding tree unit;
the intra-frame mode pre-decision unit is connected with a binary tree BT and an extended quad-tree EQT mode decision unit which support a maximum coding tree unit;
the quad-tree QT mode decision unit supporting the maximum coding tree unit is connected with the deblocking unit in parallel with the binary tree BT supporting the maximum coding tree unit and the extended quad-tree EQT mode decision unit.
Further, still include:
the comparison unit is used for comparing and analyzing the decision results of the quad-tree QT mode decision unit supporting the maximum coding tree unit and the decision results of the binary tree BT and the extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and preferentially outputting the decision results;
the comparing unit is positioned between the quad-tree QT mode decision unit supporting the maximum coding tree unit and the binary tree BT and extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and the deblocking unit.
Further, the quadtree QT mode decision unit supporting the maximum coding tree unit includes internally:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
Further, the decision unit of the mode of the binary tree BT and the extended quad-tree EQT supporting the maximum coding tree unit internally includes:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
Firstly, in the two schemes, the invention realizes the SKIP inter-frame prediction mode inside the MD.
Second, in the MDQT and MD _ BTEQT pipeline processing schemes shown in fig. 3, it can be seen that for the largest CTU pipeline MD processing circuit, there is a division into two stages of MD pipeline processing without concentrating all candidate division modes into one stage of pipeline processing. However, it should be noted that, in the video coding process, the intra mode decision process needs to rely on the left and top-left MD final pixels of the current CTU unit for prediction to ensure consistent coding and decoding. Normally, intra prediction of CTU1 MD in the figure needs to wait for all MDs of CTU0 to complete before processing. However, due to the use of the fig. 3 scheme, CTU0 and CTU1 would be in two different MD decision processes. That is, the CTU0 enters MD BTEQT after completion of MD _ QT, and the CTU1 enters MD _ QT at this time, meaning that the CTU1 cannot acquire the final mode decision pixel of the CTU 0. The same problem exists between CTU2 and CTU 3. To avoid this problem, MDENC modules are added. In the MD _ BTEQT processing, the intra prediction may refer to the left and upper left original or partially reconstructed pixels, only to the mode decision pixels that have already been obtained above. For example, CTU3 intra prediction may refer to only the pixels of CTU 0. And after the current CTU decision is completed, reforming the code stream by using the MDENC module to the optimal division result so as to realize the code stream meeting the coding standard. Although this approach may increase a portion of the area, the MDENC strategy is adopted to reform the encoding result, so that more flexible algorithms can be adopted in MD _ QT and MD _ BTEQT, which is not necessarily limited by the dependency of the encoding standard intra-frame processing procedure.
Finally, unlike the two-stage pipeline scheme shown in fig. 3, the MD _ QT and MD _ BTEQT processing circuits in fig. 4 are processed in parallel, and finally compared to obtain the optimal mode decision result. This allows the current CTU to reference the true mode decision pixels on the left and top left of the perimeter, avoiding the performance penalty of the scheme of fig. 3 due to data-dependent compromises. However, parallel processing means that MD _ QT and MD _ BTEQT need to be stored separately before comparison. Compared with the scheme of fig. 3, which can be compared in the process (only one optimal result is needed), the scheme of fig. 4 results in twice the storage cost of the final decision result.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (8)
1. A hardware encoder pipeline circuit, comprising:
the sub-pixel estimation unit is used for carrying out sub-pixel search on the coding tree unit;
the intra-frame mode pre-decision unit is used for quickly pre-selecting an intra-frame mode;
a quadtree QT mode decision unit supporting a maximum coding tree unit;
a binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit;
the deblocking unit is used for outputting the result to the DDR memory after the coding tree unit processes the result;
the sub-pixel estimation unit is sequentially connected with the quad-tree QT mode decision unit supporting the maximum coding tree unit, the binary tree BT and extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and the deblocking unit;
the intra mode pre-decision unit is connected to the quad tree QT mode decision unit that supports the largest coding tree unit.
2. The circuit of claim 1, wherein the maximum coding tree unit supported quadtree QT mode decision unit comprises internally:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
3. The circuit of claim 1, wherein the binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit comprises internally:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
4. A circuit according to any one of claims 1 to 3, further comprising:
and the mode decision division unit is used for carrying out intra-frame coding on all the final division sizes according to real peripheral reference pixels for the optimal division mode which is decided by all the sizes of the current coding tree unit CTU.
5. A hardware encoder pipeline circuit, comprising:
the sub-pixel estimation unit is used for carrying out sub-pixel search on the coding tree unit;
the intra-frame mode pre-decision unit is used for quickly pre-selecting an intra-frame mode;
a quadtree QT mode decision unit supporting a maximum coding tree unit;
a binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit;
the deblocking unit is used for outputting the result to the DDR memory after the coding tree unit processes the result;
the sub-pixel estimation unit is connected with the quad-tree QT mode decision unit supporting the maximum coding tree unit;
the intra-frame mode pre-decision unit is connected with a binary tree BT and an extended quad-tree EQT mode decision unit which support a maximum coding tree unit;
the quad-tree QT mode decision unit supporting the maximum coding tree unit is connected with the deblocking unit in parallel with the binary tree BT supporting the maximum coding tree unit and the extended quad-tree EQT mode decision unit.
6. The circuit of claim 5, further comprising:
the comparison unit is used for comparing and analyzing the decision results of the quad-tree QT mode decision unit supporting the maximum coding tree unit and the decision results of the binary tree BT and the extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and preferentially outputting the decision results;
the comparing unit is positioned between the quad-tree QT mode decision unit supporting the maximum coding tree unit and the binary tree BT and extended quad-tree EQT mode decision unit supporting the maximum coding tree unit and the deblocking unit.
7. The circuit of claim 5, wherein the maximum coding tree unit supported Quadtree (QT) mode decision unit comprises internally:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
8. The circuit of claim 5, wherein the binary tree BT and extended quad tree EQT mode decision unit supporting the maximum coding tree unit comprises:
and the skip unit is used for acquiring the skip reference pixel of the coding tree unit.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2019234640A1 (en) * | 2018-06-05 | 2019-12-12 | Beijing Bytedance Network Technology Co., Ltd. | Extended quad-tree with asymmetric sub-blocks |
| CN111385572A (en) * | 2018-12-27 | 2020-07-07 | 华为技术有限公司 | Prediction mode determining method and device, coding equipment and decoding equipment |
| CN111918057A (en) * | 2020-07-02 | 2020-11-10 | 北京大学深圳研究生院 | Hardware-friendly intra-frame coding block dividing method, equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019234640A1 (en) * | 2018-06-05 | 2019-12-12 | Beijing Bytedance Network Technology Co., Ltd. | Extended quad-tree with asymmetric sub-blocks |
| CN111385572A (en) * | 2018-12-27 | 2020-07-07 | 华为技术有限公司 | Prediction mode determining method and device, coding equipment and decoding equipment |
| CN111918057A (en) * | 2020-07-02 | 2020-11-10 | 北京大学深圳研究生院 | Hardware-friendly intra-frame coding block dividing method, equipment and storage medium |
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